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Searched refs:mmCOMPUTE_PGM_RSRC1 (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h333 #define mmCOMPUTE_PGM_RSRC1 0x2E12 macro
Dgfx_7_0_d.h1204 #define mmCOMPUTE_PGM_RSRC1 0x2e12 macro
Dgfx_7_2_d.h1217 #define mmCOMPUTE_PGM_RSRC1 0x2e12 macro
Dgfx_8_1_d.h1302 #define mmCOMPUTE_PGM_RSRC1 0x2e12 macro
Dgfx_8_0_d.h1299 #define mmCOMPUTE_PGM_RSRC1 0x2e12 macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c1462 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1483 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1504 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
Dgfx_v9_0.c4167 …{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x100007f }, /* VGPRS=15 (256 logical VGPRs, SGPRS=…
4180 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 GPRS) */
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2195 #define mmCOMPUTE_PGM_RSRC1 macro
Dgc_9_1_offset.h2494 #define mmCOMPUTE_PGM_RSRC1 macro
Dgc_9_2_1_offset.h2428 #define mmCOMPUTE_PGM_RSRC1 macro
Dgc_10_1_0_offset.h4568 #define mmCOMPUTE_PGM_RSRC1 macro