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Searched refs:mmBL_PWM_PERIOD_CNTL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h11353 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h10408 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h12779 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1865 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … macro