Home
last modified time | relevance | path

Searched refs:mmBL_PWM_GRP1_REG_LOCK_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h11355 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
Ddcn_1_0_offset.h10410 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
Ddcn_2_0_0_offset.h12781 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1867 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX … macro