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Searched refs:mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h7147 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … macro
Ddcn_2_0_0_offset.h8177 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1317 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … macro