Searched refs:min_mem_set_clock (Results 1 – 10 of 10) sorted by relevance
82 uint32_t min_mem_set_clock; member
1488 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()2233 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()2234 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega12_apply_clocks_adjust_rules()2241 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega12_apply_clocks_adjust_rules()
2302 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()3692 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()3693 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()3700 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()3713 …hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].valu… in vega20_apply_clocks_adjust_rules()
1053 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()1054 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
572 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
3180 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()3933 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
2925 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
2158 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()2159 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()2166 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()2258 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in vega20_notify_smc_dispaly_config()
1258 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_dispaly_config()
72 adev->pm.pm_display_cfg.min_mem_set_clock = in dm_pp_apply_display_requirements()