Searched refs:min_clocks (Results 1 – 6 of 6) sorted by relevance
1252 struct smu_clocks min_clocks = {0}; in navi10_notify_smc_dispaly_config() local1256 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_dispaly_config()1257 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_dispaly_config()1258 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_dispaly_config()1262 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_dispaly_config()1267 min_clocks.dcef_clock_in_sr/100); in navi10_notify_smc_dispaly_config()1279 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_dispaly_config()
2252 struct smu_clocks min_clocks = {0}; in vega20_notify_smc_dispaly_config() local2256 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in vega20_notify_smc_dispaly_config()2257 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_dispaly_config()2258 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in vega20_notify_smc_dispaly_config()2262 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in vega20_notify_smc_dispaly_config()2267 min_clocks.dcef_clock_in_sr/100); in vega20_notify_smc_dispaly_config()2279 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100; in vega20_notify_smc_dispaly_config()
1476 struct PP_Clocks min_clocks = {0}; in vega12_notify_smc_display_config_after_ps_adjustment() local1486 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()1487 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()1488 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()1492 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; in vega12_notify_smc_display_config_after_ps_adjustment()1498 min_clocks.dcefClockInSR /100), in vega12_notify_smc_display_config_after_ps_adjustment()
2296 struct PP_Clocks min_clocks = {0}; in vega20_notify_smc_display_config_after_ps_adjustment() local2300 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()2301 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()2302 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()2306 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()2311 min_clocks.dcefClockInSR / 100)) == 0, in vega20_notify_smc_display_config_after_ps_adjustment()2320 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; in vega20_notify_smc_display_config_after_ps_adjustment()
3920 struct PP_Clocks min_clocks = {0}; in vega10_notify_smc_display_config_after_ps_adjustment() local3931 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()3932 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()3933 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()3936 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) in vega10_notify_smc_display_config_after_ps_adjustment()3946 min_clocks.dcefClockInSR / 100); in vega10_notify_smc_display_config_after_ps_adjustment()3954 if (min_clocks.memoryClock != 0) { in vega10_notify_smc_display_config_after_ps_adjustment()3955 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); in vega10_notify_smc_display_config_after_ps_adjustment()
3605 struct PP_Clocks min_clocks = {0}; in smu7_find_dpm_states_clocks_in_dpm_table() local3622 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && in smu7_find_dpm_states_clocks_in_dpm_table()3623 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || in smu7_find_dpm_states_clocks_in_dpm_table()
