Home
last modified time | relevance | path

Searched refs:microcode (Results 1 – 25 of 64) sorted by relevance

123

/Linux-v5.4/Documentation/x86/
Dmicrocode.rst10 The kernel has a x86 microcode loading facility which is supposed to
11 provide microcode loading methods in the OS. Potential use cases are
12 updating the microcode on platforms beyond the OEM End-Of-Life support,
13 and updating the microcode on long-running systems without rebooting.
17 Early load microcode
20 The kernel can update microcode very early during boot. Loading
21 microcode early can fix CPU issues before they are observed during
24 The microcode is stored in an initrd file. During boot, it is read from
27 The format of the combined initrd image is microcode in (uncompressed)
31 The microcode files in cpio name space are:
[all …]
Dmds.rst77 instruction in combination with a microcode update. The microcode clears
87 executed on a CPU without the microcode update there is no side effect
102 the microcode updated, but the hypervisor does not (yet) expose the
124 scenarios where the host has the updated microcode but the
191 functionality in microcode. Aside of that the IO-Port mechanism is a
193 not affected or do not receive microcode updates anymore.
Dindex.rst28 microcode
Dtsx_async_abort.rst26 microcode update which can be used to disable TSX. In addition, it
48 scenarios where the host has the updated microcode but the
/Linux-v5.4/Documentation/powerpc/
Dqe_firmware.rst44 In this document, the term 'microcode' refers to the sequence of 32-bit
45 integers that compose the actual QE microcode.
47 The term 'firmware' refers to a binary blob that contains the microcode as
50 1) describes the microcode's purpose
51 2) describes how and where to upload the microcode
60 The QE architecture allows for only one microcode present in I-RAM for each
61 RISC processor. To replace any current microcode, a full QE reset (which
62 disables the microcode) must be performed first.
64 QE microcode is uploaded using the following procedure:
66 1) The microcode is placed into I-RAM at a specific location, using the
[all …]
/Linux-v5.4/arch/x86/kernel/cpu/microcode/
DMakefile2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_MICROCODE_INTEL) += intel.o
5 microcode-$(CONFIG_MICROCODE_AMD) += amd.o
Dintel.c778 csig->rev = c->microcode; in collect_cpu_info()
852 c->microcode = rev; in apply_microcode_intel()
856 boot_cpu_data.microcode = rev; in apply_microcode_intel()
959 c->microcode < 0x0b000021) { in is_blacklisted()
960 …rr_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); in is_blacklisted()
Damd.c654 csig->rev = c->microcode; in collect_cpu_info_amd()
710 c->microcode = rev; in apply_microcode_amd()
714 boot_cpu_data.microcode = rev; in apply_microcode_amd()
856 if (boot_cpu_data.microcode >= p->patch_id) in load_microcode_amd()
/Linux-v5.4/Documentation/power/
Dsuspend-and-cpuhotplug.rst175 There are some interesting situations involving CPU hotplug and microcode
178 [Please bear in mind that the kernel requests the microcode images from
186 to apply the same microcode revision to each of the CPUs.
189 and thereby in applying the correct microcode revision to it.
190 But note that the kernel does not maintain a common microcode image for the
196 In this case since we probably need to apply different microcode revisions
197 to different CPUs, the kernel maintains a copy of the correct microcode
207 (which is sent by the CPU hotplug code), the microcode update driver's
209 microcode image for that CPU.
212 doesn't have the microcode image, it does the CPU type/model discovery
[all …]
/Linux-v5.4/Documentation/admin-guide/hw-vuln/
Dtsx_async_abort.rst99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101 - The system tries to clear the buffers but the microcode might not support the operation.
103 - The microcode has been updated to clear the buffers. TSX is still enabled.
114 If the processor is vulnerable, but the availability of the microcode-based
120 microcode update applied, but the hypervisor is not yet updated to expose the
121 CPUID to the guest. If the host has updated microcode the protection takes
131 The kernel detects the affected CPUs and the presence of the microcode which is
132 required. If a CPU is affected and the microcode is available, then the kernel
144 Affected systems where the host has TAA microcode and TAA is mitigated by
[all …]
Dmds.rst104 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
105 - The processor is vulnerable but microcode is not updated.
127 If the processor is vulnerable, but the availability of the microcode based
133 microcode update applied, but the hypervisor is not yet updated to expose
134 the CPUID to the guest. If the host has updated microcode the protection
143 The kernel detects the affected CPUs and the presence of the microcode
146 If a CPU is affected and the microcode is available, then the kernel
176 If the L1D flush mitigation is enabled and up to date microcode is
/Linux-v5.4/drivers/net/wireless/intel/iwlegacy/
DKconfig23 In order to use this driver, you will need a microcode (uCode)
24 image for it. You can obtain the microcode from:
28 The microcode is typically installed in /lib/firmware. You can
49 In order to use this driver, you will need a microcode (uCode)
50 image for it. You can obtain the microcode from:
54 The microcode is typically installed in /lib/firmware. You can
/Linux-v5.4/drivers/crypto/cavium/cpt/
Dcptpf.h22 struct microcode { struct
53 struct microcode mcode[CPT_MAX_CORE_GROUPS]; argument
Dcptpf_main.c123 static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) in cpt_load_microcode()
161 static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) in do_cpt_init()
257 struct microcode *mcode; in cpt_ucode_load_fw()
416 struct microcode *mcode = &cpt->mcode[grp]; in cpt_unload_microcode()
/Linux-v5.4/arch/x86/kernel/cpu/
Dproc.c79 if (c->microcode) in show_cpuinfo()
80 seq_printf(m, "microcode\t: 0x%x\n", c->microcode); in show_cpuinfo()
Dintel.c142 u32 microcode; member
185 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
208 c->microcode = intel_get_microcode_revision(); in early_init_intel()
235 c->microcode < 0x20e) { in early_init_intel()
Dmatch.c76 if (!res || res->x86_microcode_rev > boot_cpu_data.microcode) in x86_cpu_has_min_microcode_rev()
DMakefile46 obj-$(CONFIG_MICROCODE) += microcode/
/Linux-v5.4/arch/x86/include/uapi/asm/
Dmce.h37 __u32 microcode; /* Microcode revision */ member
/Linux-v5.4/Documentation/networking/
Ddevlink-info-versions.rst48 Data path microcode controlling high-speed packet processing.
/Linux-v5.4/Documentation/
DChanges222 Intel IA32 microcode
225 A driver has been added to allow updating of Intel IA32 microcode,
230 mknod /dev/cpu/microcode c 10 184
231 chmod 0644 /dev/cpu/microcode
414 Intel P6 microcode
/Linux-v5.4/Documentation/process/
Dchanges.rst222 Intel IA32 microcode
225 A driver has been added to allow updating of Intel IA32 microcode,
230 mknod /dev/cpu/microcode c 10 184
231 chmod 0644 /dev/cpu/microcode
414 Intel P6 microcode
/Linux-v5.4/drivers/net/wan/
Dcosa.c1385 static int download(struct cosa_data *cosa, const char __user *microcode, int length, int address) in download() argument
1405 if (get_user(c, microcode)) in download()
1408 c = *microcode; in download()
1412 microcode++; in download()
1459 static int readmem(struct cosa_data *cosa, char __user *microcode, int length, int address) in readmem() argument
1483 if (put_user(c, microcode)) in readmem()
1486 *microcode = c; in readmem()
1488 microcode++; in readmem()
/Linux-v5.4/drivers/soc/fsl/qe/
Dqe.c493 be32_to_cpu(firmware->microcode[i].count); in qe_upload_firmware()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware()
/Linux-v5.4/drivers/scsi/
Dwd33c93.h222 uchar microcode; /* microcode rev */ member

123