Searched refs:mg_pll_div0 (Results 1 – 5 of 5) sorted by relevance
204 u32 mg_pll_div0; member
2804 pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) | in icl_calc_mg_pll_state()3077 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()3219 I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()3425 hw_state->mg_pll_div0, in icl_dump_hw_state()
1417 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_calc_mg_pll_link()1418 m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ? in icl_calc_mg_pll_link()1419 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >> in icl_calc_mg_pll_link()
12819 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); in intel_pipe_config_compare()
2854 pll->state.hw_state.mg_pll_div0); in i915_shared_dplls_info()
