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Searched refs:mec_int_cntl_reg (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c4727 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4738 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4741 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4744 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4747 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4760 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4762 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4765 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4767 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c4859 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
4870 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4879 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
4892 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
4895 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
4898 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
4901 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
Dgfx_v9_0.c5503 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
5514 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5517 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5520 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5523 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5536 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5539 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5542 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5545 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6532 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6543 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6546 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6549 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6552 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6565 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6567 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6570 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6572 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()