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Searched refs:mec_int_cntl (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c4727 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4760 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4761 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4762 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4765 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4766 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_compute_eop_interrupt_state()
4767 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
Dgfx_v10_0.c4859 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
4892 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
4893 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
4895 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
4898 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
4899 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_compute_eop_interrupt_state()
4901 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
Dgfx_v9_0.c5503 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
5536 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5537 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5539 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5542 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5543 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_compute_eop_interrupt_state()
5545 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
Dgfx_v8_0.c6532 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6565 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6566 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6567 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6570 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6571 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v8_0_set_compute_eop_interrupt_state()
6572 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()