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Searched refs:mclk_table (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_hwmgr.c638 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
706 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v0()
708 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
710 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
712 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
713 data->dpm_table.mclk_table.count++; in smu7_setup_dpm_tables_v0()
801 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v1()
803 if (i == 0 || data->dpm_table.mclk_table.dpm_levels in smu7_setup_dpm_tables_v1()
804 [data->dpm_table.mclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
806 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
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Dsmu10_hwmgr.c834 struct smu10_voltage_dependency_table *mclk_table = in smu10_force_clock_level() local
862 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) in smu10_force_clock_level()
867 mclk_table->entries[low].clk/100); in smu10_force_clock_level()
871 mclk_table->entries[high].clk/100); in smu10_force_clock_level()
885 struct smu10_voltage_dependency_table *mclk_table = in smu10_print_clock_levels() local
916 for (i = 0; i < mclk_table->count; i++) in smu10_print_clock_levels()
919 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
920 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
Dvega10_processpptables.c609 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
618 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
620 if (!mclk_table) in get_mclk_voltage_dependency_table()
623 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
626 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
628 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
630 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
632 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
636 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
Dvega10_hwmgr.c667 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = in vega10_patch_voltage_dependency_tables_with_lookup_table() local
694 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
695 voltage_id = mclk_table->entries[entry_id].vddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
696 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
698 voltage_id = mclk_table->entries[entry_id].vddciInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
699 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
701 voltage_id = mclk_table->entries[entry_id].mvddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
702 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3293 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3310 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
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Dprocess_pptables_v1_0.c374 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
384 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
386 if (NULL == mclk_table) in get_mclk_voltage_dependency_table()
389 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
394 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
405 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
Dsmu7_hwmgr.h105 struct smu7_single_dpm_table mclk_table; member
Dvega12_hwmgr.c2532 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2535 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
Dvega20_hwmgr.c1488 struct vega20_single_dpm_table *mclk_table = in vega20_get_mclk_od() local
1492 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; in vega20_get_mclk_od()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dci_dpm.c2556 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2559 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3336 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3337 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3340 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3348 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3358 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3360 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3362 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3467 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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Dci_dpm.h70 struct ci_single_dpm_table mclk_table; member
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/
Dvegam_smumgr.c1046 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1047 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1051 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1064 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1066 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in vegam_populate_all_memory_levels()
1068 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1072 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in vegam_populate_all_memory_levels()
1177 data->dpm_table.mclk_table.dpm_levels[0].value, in vegam_populate_smc_acpi_level()
1297 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1300 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
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Diceland_smumgr.c1361 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1382 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1383 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1385 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
1622 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1667 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1761 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
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Dfiji_smumgr.c1238 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1239 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1243 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1261 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1263 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1265 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1378 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1399 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1538 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1541 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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Dci_smumgr.c1314 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1315 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1317 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1327 if ((dpm_table->mclk_table.count >= 2) in ci_populate_all_memory_levels()
1337 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
1338 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
1339 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in ci_populate_all_memory_levels()
1659 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1662 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1704 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in ci_populate_smc_boot_level()
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Dpolaris10_smumgr.c1139 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1140 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1144 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1146 if (i == dpm_table->mclk_table.count - 1) { in polaris10_populate_all_memory_levels()
1163 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
1165 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1262 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1371 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1374 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1377 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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Dtonga_smumgr.c1107 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1130 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1131 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1133 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1498 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1545 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2140 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
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