Searched refs:max_backends_per_se (Results 1 – 19 of 19) sorted by relevance
910 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()948 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()962 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()976 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()983 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()1104 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1108 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1138 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()1150 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
338 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()341 *value = rdev->config.si.max_backends_per_se * in radeon_info_ioctl()344 *value = rdev->config.cayman.max_backends_per_se * in radeon_info_ioctl()
3108 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3125 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3143 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3160 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()3177 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()3294 rdev->config.si.max_backends_per_se); in si_gpu_init()
2094 unsigned max_backends_per_se; member2133 unsigned max_backends_per_se; member2164 unsigned max_backends_per_se; member
2343 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()3196 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3213 rdev->config.cik.max_backends_per_se = 4; in cik_gpu_init()3229 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3249 rdev->config.cik.max_backends_per_se = 1; in cik_gpu_init()3351 rdev->config.cik.max_backends_per_se); in cik_gpu_init()
446 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
131 unsigned max_backends_per_se; member
1335 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()1469 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()1488 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()1590 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1607 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1624 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1641 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_constants_init()1658 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_constants_init()
399 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1631 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()1793 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()1811 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()4271 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4288 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()4304 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4324 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
1724 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1741 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()1788 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1804 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1821 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()1839 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()3486 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()3648 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()3666 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
490 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
745 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; in amdgpu_atombios_get_gfx_info()
694 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
1532 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()1543 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
1475 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
2415 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()2426 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
1227 uint8_t max_backends_per_se; member1247 uint8_t max_backends_per_se; member1272 uint8_t max_backends_per_se; member
5654 UCHAR max_backends_per_se; member
