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Searched refs:masks (Results 1 – 25 of 168) sorted by relevance

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/Linux-v5.4/drivers/clk/mmp/
Dclk-frac.c37 (factor->ftbl[i].num * factor->masks->factor)) * 10000; in clk_factor_round_rate()
55 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local
61 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate()
64 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate()
70 (num * factor->masks->factor)) * 10000; in clk_factor_recalc_rate()
78 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local
86 (factor->ftbl[i].num * factor->masks->factor)) * 10000; in clk_factor_set_rate()
98 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate()
99 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; in clk_factor_set_rate()
101 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate()
[all …]
/Linux-v5.4/drivers/clk/spear/
Dclk-aux-synth.c80 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate()
81 if (eqn == aux->masks->eq1_mask) in clk_aux_recalc_rate()
85 num = (val >> aux->masks->xscale_sel_shift) & in clk_aux_recalc_rate()
86 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate()
89 den *= (val >> aux->masks->yscale_sel_shift) & in clk_aux_recalc_rate()
90 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate()
114 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate()
115 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << in clk_aux_set_rate()
116 aux->masks->eq_sel_shift; in clk_aux_set_rate()
117 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate()
[all …]
Dclk.h52 const struct aux_clk_masks *masks; member
115 const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
/Linux-v5.4/kernel/irq/
Daffinity.c45 cpumask_var_t *masks; in alloc_node_to_cpumask() local
48 masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL); in alloc_node_to_cpumask()
49 if (!masks) in alloc_node_to_cpumask()
53 if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL)) in alloc_node_to_cpumask()
57 return masks; in alloc_node_to_cpumask()
61 free_cpumask_var(masks[node]); in alloc_node_to_cpumask()
62 kfree(masks); in alloc_node_to_cpumask()
66 static void free_node_to_cpumask(cpumask_var_t *masks) in free_node_to_cpumask() argument
71 free_cpumask_var(masks[node]); in free_node_to_cpumask()
72 kfree(masks); in free_node_to_cpumask()
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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c139 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
141 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
234 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
236 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
281 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
283 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
285 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
287 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
290 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
292 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; in dpp1_cm_get_reg_field()
[all …]
Ddcn10_cm_common.h71 struct xfer_func_mask masks; member
86 struct cm_color_matrix_mask masks; member
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_i2c_hw.c41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) in get_channel_status()
82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) in get_channel_status()
84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) in get_channel_status()
86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status()
283 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) in set_speed()
621 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument
628 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct()
645 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument
655 masks); in dce100_i2c_hw_construct()
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Ddce_i2c_hw.h280 const struct dce_i2c_mask *masks; member
289 const struct dce_i2c_mask *masks);
297 const struct dce_i2c_mask *masks);
305 const struct dce_i2c_mask *masks);
313 const struct dce_i2c_mask *masks);
322 const struct dce_i2c_mask *masks);
Ddce_hwseq.c38 hws->shifts->field_name, hws->masks->field_name
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
120 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
/Linux-v5.4/drivers/clk/uniphier/
Dclk-uniphier-mux.c17 const unsigned int *masks; member
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
77 mux->masks = data->masks; in uniphier_clk_register_mux()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mpc.c149 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
151 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
189 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
191 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
215 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
217 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
219 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
221 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
223 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
225 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
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Ddcn20_dpp_cm.c211 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
213 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
215 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
217 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
220 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
222 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
224 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
226 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
228 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn20_dpp_cm_get_reg_field()
230 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; in dcn20_dpp_cm_get_reg_field()
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dtdm-slot.txt20 tx and rx masks.
22 For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
24 the masks.
26 The explicit masks are given as array of integers, where the first
/Linux-v5.4/drivers/s390/char/
Dsclp.h106 u8 masks[4 * 1021]; /* variable length */ member
117 static inline sccb_mask_t sccb_get_mask(u8 *masks, size_t len, int i) in sccb_get_mask() argument
121 memcpy(&res, masks + i * len, min(sizeof(res), len)); in sccb_get_mask()
125 static inline void sccb_set_mask(u8 *masks, size_t len, int i, sccb_mask_t val) in sccb_set_mask() argument
127 memset(masks + i * len, 0, len); in sccb_set_mask()
128 memcpy(masks + i * len, &val, min(sizeof(val), len)); in sccb_set_mask()
135 sccb_get_mask(__sccb->masks, __sccb->mask_length, i); \
146 sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \
/Linux-v5.4/tools/perf/trace/beauty/
Dprctl.c64 const u8 masks[] = { in syscall_arg__scnprintf_prctl_option() local
77 if (option < ARRAY_SIZE(masks)) in syscall_arg__scnprintf_prctl_option()
78 arg->mask |= masks[option]; in syscall_arg__scnprintf_prctl_option()
/Linux-v5.4/drivers/gpu/drm/via/
Dvia_irq.c211 maskarray_t *masks; in via_driver_irq_wait() local
234 masks = dev_priv->irq_masks; in via_driver_irq_wait()
237 if (masks[real_irq][2] && !force_sequence) { in via_driver_irq_wait()
239 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == in via_driver_irq_wait()
240 masks[irq][4])); in via_driver_irq_wait()
/Linux-v5.4/Documentation/devicetree/bindings/mux/
Dreg-mux.txt11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
21 pair in the mux-reg-masks array.
35 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
97 mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_factory_dcn10.c157 generic->masks = &generic_mask[en]; in define_generic_registers()
182 ddc->masks = &ddc_mask; in define_ddc_registers()
192 hpd->masks = &hpd_mask; in define_hpd_registers()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_factory_dcn21.c166 generic->masks = &generic_mask[en]; in define_generic_registers()
191 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
201 hpd->masks = &hpd_mask; in define_hpd_registers()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_factory_dcn20.c189 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
199 hpd->masks = &hpd_mask; in define_hpd_registers()
209 generic->masks = &generic_mask[en]; in define_generic_registers()
/Linux-v5.4/drivers/char/agp/
Dintel-agp.c461 .masks = intel_generic_masks,
488 .masks = intel_generic_masks,
515 .masks = intel_generic_masks,
542 .masks = intel_generic_masks,
569 .masks = intel_generic_masks,
596 .masks = intel_generic_masks,
623 .masks = intel_generic_masks,
650 .masks = intel_generic_masks,
677 .masks = intel_generic_masks,
/Linux-v5.4/drivers/scsi/aic7xxx/aicasm/
Daicasm_symbol.c468 symlist_t masks; in symtable_dump() local
485 SLIST_INIT(&masks); in symtable_dump()
505 symlist_add(&masks, cursym, SYMLIST_SORT); in symtable_dump()
576 while (SLIST_FIRST(&masks) != NULL) { in symtable_dump()
579 curnode = SLIST_FIRST(&masks); in symtable_dump()
580 SLIST_REMOVE_HEAD(&masks, links); in symtable_dump()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dce110/
Dhw_factory_dce110.c137 ddc->masks = &ddc_mask; in define_ddc_registers()
147 hpd->masks = &hpd_mask; in define_hpd_registers()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/dce80/
Dhw_factory_dce80.c137 ddc->masks = &ddc_mask; in define_ddc_registers()
147 hpd->masks = &hpd_mask; in define_hpd_registers()
/Linux-v5.4/Documentation/filesystems/
Dadfs.txt44 Hence, with the default masks, if a file is owner read/write, and
49 However, if the masks were ownmask=0770,othmask=0007, then this would
53 There is no restriction on what you can do with these masks. You may

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