Searched refs:ltq_cgu_r32 (Results 1 – 4 of 4) sorted by relevance
22 #define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]35 if (ltq_cgu_r32(CGU_SYS) & 0x40) in ltq_danube_fpi_hz()42 switch (ltq_cgu_r32(CGU_SYS) & 0xc) { in ltq_danube_cpu_hz()56 unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3; in ltq_danube_pp32_hz()79 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) in ltq_ar9_sys_hz()88 if (ltq_cgu_r32(CGU_SYS) & BIT(0)) in ltq_ar9_fpi_hz()96 if (ltq_cgu_r32(CGU_SYS) & BIT(2)) in ltq_ar9_cpu_hz()107 cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf; in ltq_vr9_cpu_hz()148 ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3; in ltq_vr9_fpi_hz()177 unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7; in ltq_vr9_pp32_hz()[all …]
188 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); in cgu_enable()195 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); in cgu_disable()250 unsigned int val = ltq_cgu_r32(ifccr); in pci_enable()274 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); in pci_ext_enable()282 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); in pci_ext_disable()296 unsigned int val = ltq_cgu_r32(ifccr); in clkout_enable()483 if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) in ltq_soc_init()
23 ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR); in ltq_cputemp_enable()28 ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR); in ltq_cputemp_disable()39 value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF; in ltq_read()
71 #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) macro
