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Searched refs:lower_32_bits (Results 1 – 25 of 431) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue_v9.c93 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
95 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
98 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
102 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
141 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
166 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_v9()
169 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_v9()
228 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
234 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
337 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_v9()
[all …]
Dkfd_kernel_queue_v10.c95 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v10()
98 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v10()
102 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v10()
106 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v10()
145 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v10()
195 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_v10()
201 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v10()
294 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_v10()
296 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_v10()
Dkfd_kernel_queue_vi.c109 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
148 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
173 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
176 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
226 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
232 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
324 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
326 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
Dkfd_mqd_manager_vi.c115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
129 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
131 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
141 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
183 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
186 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
188 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
214 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
360 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
362 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_v10.c127 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
146 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
187 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
190 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
192 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
213 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
361 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
363 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_v9.c146 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
167 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
205 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
208 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
210 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
233 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
379 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
381 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_cik.c115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
206 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
208 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
247 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
249 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
329 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
331 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_hiq()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c378 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
390 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
398 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
436 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
457 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
477 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
716 lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
1038 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1049 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1196 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
[all …]
Dsi_dma.c60 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in si_dma_ring_set_wptr()
72 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
158 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
177 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in si_dma_start()
224 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
275 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
322 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
323 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
346 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
349 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
[all …]
Dsdma_v2_4.c226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_ring_set_wptr()
258 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); in sdma_v2_4_ring_emit_ib()
263 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
314 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
316 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
322 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
458 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
466 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_gfx_resume()
570 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
623 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
[all …]
Dsdma_v3_0.c392 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
393 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
397 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
432 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); in sdma_v3_0_ring_emit_ib()
437 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
488 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
490 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
496 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
697 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
[all …]
Dvcn_v2_5.c395 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
406 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
414 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
664 lower_32_bits(ring->gpu_addr)); in jpeg_v2_5_start()
859 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
868 lower_32_bits(ring->wptr)); in vcn_v2_5_start()
870 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
871 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
877 WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
878 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
[all …]
Dvcn_v1_0.c309 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
321 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
329 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
379 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
391 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
401 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
921 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
932 lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
938 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
939 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
[all …]
Dsdma_v5_0.c237 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
333 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
336 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
346 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
350 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
386 sdma_v5_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); in sdma_v5_0_ring_emit_ib()
391 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
394 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
447 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
449 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
[all …]
Dcik_sdma.c198 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in cik_sdma_ring_set_wptr()
231 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); in cik_sdma_ring_emit_ib()
282 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
284 amdgpu_ring_write(ring, lower_32_bits(seq)); in cik_sdma_ring_emit_fence()
290 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
488 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in cik_sdma_gfx_resume()
635 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
688 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
738 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pte()
740 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pte()
[all …]
Dvce_v4_0.c108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
109 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
115 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
118 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
121 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
163 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); in vce_v4_0_mmsch_start()
234 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
342 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
343 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
350 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()
[all …]
Dvce_v3_0.c153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
155 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
157 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
281 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
282 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
288 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
289 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
295 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start()
296 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start()
843 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
[all …]
Duvd_v7_0.c140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
163 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
166 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
672 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
683 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume()
690 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
720 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in uvd_v7_0_mmsch_start()
814 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
[all …]
/Linux-v5.4/arch/x86/include/asm/
Dmshyperv.h93 u32 input_address_lo = lower_32_bits(input_address); in hv_do_hypercall()
95 u32 output_address_lo = lower_32_bits(output_address); in hv_do_hypercall()
128 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall8()
161 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall16()
163 u32 input2_lo = lower_32_bits(input2); in hv_do_fast_hypercall16()
/Linux-v5.4/include/linux/
Dgoldfish.h16 writel(lower_32_bits(addr), portl); in gf_write_ptr()
26 writel(lower_32_bits(addr), portl); in gf_write_dma_addr()
/Linux-v5.4/drivers/media/pci/pt3/
Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/Linux-v5.4/drivers/pci/controller/
Dpci-xgene.c294 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
298 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
391 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
393 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
395 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
403 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
456 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
459 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
522 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
528 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
/Linux-v5.4/drivers/pci/controller/dwc/
Dpcie-designware.c248 lower_32_bits(cpu_addr)); in dw_pcie_prog_outbound_atu_unroll()
252 lower_32_bits(cpu_addr + size - 1)); in dw_pcie_prog_outbound_atu_unroll()
254 lower_32_bits(pci_addr)); in dw_pcie_prog_outbound_atu_unroll()
294 lower_32_bits(cpu_addr)); in dw_pcie_prog_outbound_atu()
298 lower_32_bits(cpu_addr + size - 1)); in dw_pcie_prog_outbound_atu()
300 lower_32_bits(pci_addr)); in dw_pcie_prog_outbound_atu()
343 lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu_unroll()
392 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
/Linux-v5.4/drivers/firmware/xilinx/
Dzynqmp.c90 ret_payload[0] = lower_32_bits(res.a0); in do_fw_call_smc()
92 ret_payload[2] = lower_32_bits(res.a1); in do_fw_call_smc()
120 ret_payload[0] = lower_32_bits(res.a0); in do_fw_call_hvc()
122 ret_payload[2] = lower_32_bits(res.a1); in do_fw_call_hvc()
399 lower_32_bits(rate), in zynqmp_pm_clock_setrate()
558 return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), in zynqmp_pm_fpga_load()
/Linux-v5.4/drivers/soc/fsl/qbman/
Ddpaa_sys.c76 res_array[1] = cpu_to_be32(lower_32_bits(*addr)); in qbman_init_private_mem()
78 res_array[3] = cpu_to_be32(lower_32_bits(*size)); in qbman_init_private_mem()

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