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Searched refs:link_width_cntl (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Drv770.c2027 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2050 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2051 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2052 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2053 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2054 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2055 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2056 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2058 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2060 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
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Dr300.c504 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
541 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
545 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
549 link_width_cntl |= mask; in rv370_set_pcie_lanes()
550 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
551 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
555 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
556 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
557 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
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Dr600.c4403 u32 link_width_cntl, mask; in r600_set_pcie_lanes() local
4445 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_set_pcie_lanes()
4446 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; in r600_set_pcie_lanes()
4447 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; in r600_set_pcie_lanes()
4448 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | in r600_set_pcie_lanes()
4451 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in r600_set_pcie_lanes()
4456 u32 link_width_cntl; in r600_get_pcie_lanes() local
4470 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_get_pcie_lanes()
4472 …switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIF… in r600_get_pcie_lanes()
4493 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
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Devergreen.c5327 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5357 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5358 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5359 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
5378 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5381 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5383 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5384 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dsi.c1276 u32 link_width_cntl; in si_get_pcie_lanes() local
1281 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_get_pcie_lanes()
1283 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes()
1301 u32 link_width_cntl, mask; in si_set_pcie_lanes() local
1330 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_set_pcie_lanes()
1331 link_width_cntl &= ~LC_LINK_WIDTH_MASK; in si_set_pcie_lanes()
1332 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; in si_set_pcie_lanes()
1333 link_width_cntl |= (LC_RECONFIG_NOW | in si_set_pcie_lanes()
1336 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in si_set_pcie_lanes()