Searched refs:level1 (Results 1 – 8 of 8) sorted by relevance
94 u32 level1; member106 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_suspend()118 writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_resume()
734 u32 level1; in mtu3_irq() local739 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR); in mtu3_irq()740 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER); in mtu3_irq()742 if (level1 & EP_CTRL_INTR) in mtu3_irq()745 if (level1 & MAC2_INTR) in mtu3_irq()748 if (level1 & MAC3_INTR) in mtu3_irq()751 if (level1 & BMU_INTR) in mtu3_irq()754 if (level1 & QMU_INTR) in mtu3_irq()
71 struct i40iw_pble_info level1; member
516 struct i40iw_pble_info *lvl1 = &palloc->level1; in get_lvl1_pble()609 gen_pool_free(pool, palloc->level1.addr, in i40iw_free_pble()610 (palloc->level1.cnt << 3)); in i40iw_free_pble()
1366 arr = (u64 *)palloc->level1.addr; in i40iw_check_mr_contiguous()1411 pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf; in i40iw_setup_pbles()1462 arr = (u64 *)palloc->level1.addr; in i40iw_handle_q_mem()1475 hmc_p->idx = palloc->level1.idx; in i40iw_handle_q_mem()1477 hmc_p->idx = palloc->level1.idx + req->sq_pages; in i40iw_handle_q_mem()1491 hmc_p->idx = palloc->level1.idx; in i40iw_handle_q_mem()1620 pbl = (u64 *)palloc->level1.addr; in i40iw_set_page()1703 stag_info->first_pm_pbl_index = palloc->level1.idx; in i40iw_hwreg_mr()2251 info.reg_addr_pa = *(u64 *)palloc->level1.addr; in i40iw_post_send()2252 info.first_pm_pbl_index = palloc->level1.idx; in i40iw_post_send()
319 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0343 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
92 ldr r12, omap_ih1_base @ set pointer to level1 handler
3434 int level1 = 0, level2 = 0; in ilk_find_best_result() local3438 level1 = level; in ilk_find_best_result()3443 if (level1 == level2) { in ilk_find_best_result()3448 } else if (level1 > level2) { in ilk_find_best_result()
