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Searched refs:lane_width (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dhwmgr_ppt.h97 uint8_t lane_width; member
Dvega20_hwmgr.c3267 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3364 lane_width = data->pcie_width_level1; in vega20_print_clock_levels()
3367 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3374 (lane_width == 1) ? "x1" : in vega20_print_clock_levels()
3375 (lane_width == 2) ? "x2" : in vega20_print_clock_levels()
3376 (lane_width == 3) ? "x4" : in vega20_print_clock_levels()
3377 (lane_width == 4) ? "x8" : in vega20_print_clock_levels()
3378 (lane_width == 5) ? "x12" : in vega20_print_clock_levels()
3379 (lane_width == 6) ? "x16" : "", in vega20_print_clock_levels()
3382 (current_lane_width == lane_width) ? in vega20_print_clock_levels()
Dprocess_pptables_v1_0.c537 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
577 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
Dvega10_processpptables.c843 pcie_table->entries[i].lane_width = in get_pcie_table()
Dsmu7_hwmgr.c569 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
Dvega10_hwmgr.c1268 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dsi_dpm.c4702 u32 lane_width; in si_init_smc_table() local
4771 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4772 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5918 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5926 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5927 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/
Dvega20_ppt.c945 uint32_t gen_speed, lane_width; in vega20_print_clk_levels() local
1063 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_print_clk_levels()
1080 (lane_width == pptable->PcieLaneCount[i]) ? in vega20_print_clk_levels()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c5164 u32 lane_width; in si_init_smc_table() local
5233 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5234 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6376 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6384 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6385 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()