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Searched refs:lane_count (Results 1 – 25 of 43) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c47 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
85 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
86 len = intel_dp->lane_count + 1; in intel_dp_set_link_train()
112 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
114 return ret == intel_dp->lane_count; in intel_dp_update_link_train()
121 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
152 link_config[1] = intel_dp->lane_count; in intel_dp_link_training_clock_recovery()
200 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { in intel_dp_link_training_clock_recovery()
312 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
320 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
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Dintel_dpio_phy.c574 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
576 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
584 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
661 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
674 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
682 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
690 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
713 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
727 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
753 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
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Dintel_dp.h46 int link_rate, u8 lane_count,
49 int link_rate, u8 lane_count);
112 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
114 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
Dvlv_dsi.c44 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
48 8 * 100), lane_count); in txbyteclkhs()
52 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
55 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1039 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1088 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1090 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1092 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1142 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1144 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
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Dintel_combo_phy.c216 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
224 switch (lane_count) { in intel_combo_phy_power_up_lanes()
235 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
242 switch (lane_count) { in intel_combo_phy_power_up_lanes()
252 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
Dvlv_dsi_pll.c44 int lane_count) in dsi_clk_from_pclk() argument
51 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
125 intel_dsi->lane_count); in vlv_dsi_pll_compute()
313 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_get_pclk()
334 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_get_pclk()
463 intel_dsi->lane_count); in bxt_dsi_pll_compute()
Dintel_combo_phy.h18 int lane_count, bool lane_reversal);
Dintel_dp.c427 u8 lane_count) in intel_dp_link_params_valid() argument
438 if (lane_count == 0 || in intel_dp_link_params_valid()
439 lane_count > intel_dp_max_lane_count(intel_dp)) in intel_dp_link_params_valid()
447 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument
454 max_rate = intel_dp_max_data_rate(link_rate, lane_count); in intel_dp_can_link_train_fallback_for_edp()
462 int link_rate, u8 lane_count) in intel_dp_get_link_train_fallback_values() argument
473 lane_count)) { in intel_dp_get_link_train_fallback_values()
478 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
479 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
483 lane_count >> 1)) { in intel_dp_get_link_train_fallback_values()
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Dintel_dpio_phy.h29 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
Dintel_dsi.c16 return intel_dsi->pclk * bpp / intel_dsi->lane_count; in intel_dsi_bitrate()
Dintel_dp_mst.c57 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_compute_link_config()
80 crtc_state->lane_count, in intel_dp_mst_compute_link_config()
153 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_dp_mst_compute_config()
Dintel_ddi.c1205 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
1842 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_transcoder_func()
1845 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_transcoder_func()
2402 width = intel_dp->lane_count; in cnl_ddi_vswing_sequence()
2528 width = intel_dp->lane_count; in icl_combo_phy_ddi_vswing_sequence()
3178 crtc_state->lane_count, is_mst); in intel_ddi_pre_enable_dp()
3207 crtc_state->lane_count, in intel_ddi_pre_enable_dp()
3692 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
3720 intel_tc_port_get_link(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3731 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
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Dintel_dsi.h69 unsigned int lane_count; member
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c141 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
176 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
186 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
256 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
273 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); in dpcd_set_lt_pattern_and_lane_settings()
354 for (lane = 0; lane < src.link_settings.lane_count; lane++) { in update_drive_settings()
416 for (lane = 1; lane < link_training_setting->link_settings.lane_count; in find_max_drive_settings()
474 max_lt_setting->link_settings.lane_count = in find_max_drive_settings()
475 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
480 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
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Ddc_link.c546 link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET; in read_edp_current_link_settings_on_detect()
1483 (link->cur_link_settings.lane_count != link_settings.lane_count || in enable_link_dp()
1565 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) in enable_link_dp_mst()
3037 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) && in dc_link_set_preferred_link_settings()
3056 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN; in dc_link_set_preferred_training_settings()
3098 link_bw_kbps *= link_setting->lane_count; in dc_link_bandwidth_kbps()
3134 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && in dc_link_get_link_cap()
/Linux-v5.4/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c260 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
262 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
267 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
272 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
276 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
288 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
314 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
319 lane_count); in analogix_dp_link_start()
334 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
339 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
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/Linux-v5.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c100 link->cur_link_settings.lane_count, in dp_link_settings_read()
107 link->verified_link_cap.lane_count, in dp_link_settings_read()
114 link->reported_link_cap.lane_count, in dp_link_settings_read()
121 link->preferred_link_setting.lane_count, in dp_link_settings_read()
230 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
390 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
391 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
397 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
398 link->cur_link_settings.lane_count; in dp_phy_settings_write()
406 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { in dp_phy_settings_write()
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/Linux-v5.4/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c265 uint8_t lane_count; member
901 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
914 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
916 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
920 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
924 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
932 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
937 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
994 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1011 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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Dmdfld_dsi_dpi.c472 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
487 val = lane_count; in mdfld_dsi_dpi_controller_init()
508 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
525 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
751 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
775 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
789 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
Dmdfld_dsi_output.c419 config->lane_count = 4; in mdfld_dsi_get_default_config()
421 config->lane_count = 2; in mdfld_dsi_get_default_config()
/Linux-v5.4/drivers/gpu/drm/bridge/
Dparade-ps8622.c55 u32 lane_count; member
191 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
568 &ps8622->lane_count)) { in ps8622_probe()
569 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
570 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
573 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c155 cfg->link_settings.lane_count = in dce110_fill_display_configs()
156 stream->link->cur_link_settings.lane_count; in dce110_fill_display_configs()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in enc1_configure_encoder()
969 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_output()
1008 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_mst_output()
1091 cntl.lanes_number = link_settings->link_settings.lane_count; in dcn10_link_encoder_dp_set_lane_settings()
1096 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dcn10_link_encoder_dp_set_lane_settings()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.c486 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
1007 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1046 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1125 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings()
1130 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
/Linux-v5.4/drivers/gpu/drm/
Ddrm_dp_helper.c63 int lane_count) in drm_dp_channel_eq_ok() argument
73 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
83 int lane_count) in drm_dp_clock_recovery_ok() argument
88 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()

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