1  /*
2   * DCE_11_2 Register documentation
3   *
4   * Copyright (C) 2016  Advanced Micro Devices, Inc.
5   *
6   * Permission is hereby granted, free of charge, to any person obtaining a
7   * copy of this software and associated documentation files (the "Software"),
8   * to deal in the Software without restriction, including without limitation
9   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10   * and/or sell copies of the Software, and to permit persons to whom the
11   * Software is furnished to do so, subject to the following conditions:
12   *
13   * The above copyright notice and this permission notice shall be included
14   * in all copies or substantial portions of the Software.
15   *
16   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17   * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19   * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20   * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21   * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22   */
23  
24  #ifndef DCE_11_2_D_H
25  #define DCE_11_2_D_H
26  
27  #define mmPIPE0_PG_CONFIG                                                       0x2c0
28  #define mmPIPE0_PG_ENABLE                                                       0x2c1
29  #define mmPIPE0_PG_STATUS                                                       0x2c2
30  #define mmPIPE1_PG_CONFIG                                                       0x2c3
31  #define mmPIPE1_PG_ENABLE                                                       0x2c4
32  #define mmPIPE1_PG_STATUS                                                       0x2c5
33  #define mmPIPE2_PG_CONFIG                                                       0x2c6
34  #define mmPIPE2_PG_ENABLE                                                       0x2c7
35  #define mmPIPE2_PG_STATUS                                                       0x2c8
36  #define mmPIPE3_PG_CONFIG                                                       0x2c9
37  #define mmPIPE3_PG_ENABLE                                                       0x2ca
38  #define mmPIPE3_PG_STATUS                                                       0x2cb
39  #define mmPIPE4_PG_CONFIG                                                       0x2cc
40  #define mmPIPE4_PG_ENABLE                                                       0x2cd
41  #define mmPIPE4_PG_STATUS                                                       0x2ce
42  #define mmPIPE5_PG_CONFIG                                                       0x2cf
43  #define mmPIPE5_PG_ENABLE                                                       0x2d0
44  #define mmPIPE5_PG_STATUS                                                       0x2d1
45  #define mmDCPG_INTERRUPT_STATUS                                                 0x2de
46  #define mmDCPG_INTERRUPT_CONTROL                                                0x2df
47  #define mmDCPG_INTERRUPT_CONTROL2                                               0x2e0
48  #define mmDC_IP_REQUEST_CNTL                                                    0x2d2
49  #define mmDC_PGFSM_CONFIG_REG                                                   0x2d3
50  #define mmDC_PGFSM_WRITE_REG                                                    0x2d4
51  #define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
52  #define mmDCPG_TEST_DEBUG_INDEX                                                 0x2d6
53  #define mmDCPG_TEST_DEBUG_DATA                                                  0x2d7
54  #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                           0x1628
55  #define mmBL1_PWM_USER_LEVEL                                                    0x1629
56  #define mmBL1_PWM_TARGET_ABM_LEVEL                                              0x162a
57  #define mmBL1_PWM_CURRENT_ABM_LEVEL                                             0x162b
58  #define mmBL1_PWM_FINAL_DUTY_CYCLE                                              0x162c
59  #define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                            0x162d
60  #define mmBL1_PWM_ABM_CNTL                                                      0x162e
61  #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                         0x162f
62  #define mmBL1_PWM_GRP2_REG_LOCK                                                 0x1630
63  #define mmDC_ABM1_CNTL                                                          0x1638
64  #define mmDC_ABM1_IPCSC_COEFF_SEL                                               0x1639
65  #define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                            0x163a
66  #define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                            0x163b
67  #define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                            0x163c
68  #define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                            0x163d
69  #define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                            0x163e
70  #define mmDC_ABM1_ACE_THRES_12                                                  0x163f
71  #define mmDC_ABM1_ACE_THRES_34                                                  0x1640
72  #define mmDC_ABM1_ACE_CNTL_MISC                                                 0x1641
73  #define mmDC_ABM1_DEBUG_MISC                                                    0x1649
74  #define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                        0x164a
75  #define mmDC_ABM1_HG_MISC_CTRL                                                  0x164b
76  #define mmDC_ABM1_LS_SUM_OF_LUMA                                                0x164c
77  #define mmDC_ABM1_LS_MIN_MAX_LUMA                                               0x164d
78  #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                      0x164e
79  #define mmDC_ABM1_LS_PIXEL_COUNT                                                0x164f
80  #define mmDC_ABM1_LS_OVR_SCAN_BIN                                               0x1650
81  #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                  0x1651
82  #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                      0x1652
83  #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                      0x1653
84  #define mmDC_ABM1_HG_SAMPLE_RATE                                                0x1654
85  #define mmDC_ABM1_LS_SAMPLE_RATE                                                0x1655
86  #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                        0x1656
87  #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                        0x1657
88  #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                       0x1658
89  #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                      0x1659
90  #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                      0x165a
91  #define mmDC_ABM1_HG_RESULT_1                                                   0x165b
92  #define mmDC_ABM1_HG_RESULT_2                                                   0x165c
93  #define mmDC_ABM1_HG_RESULT_3                                                   0x165d
94  #define mmDC_ABM1_HG_RESULT_4                                                   0x165e
95  #define mmDC_ABM1_HG_RESULT_5                                                   0x165f
96  #define mmDC_ABM1_HG_RESULT_6                                                   0x1660
97  #define mmDC_ABM1_HG_RESULT_7                                                   0x1661
98  #define mmDC_ABM1_HG_RESULT_8                                                   0x1662
99  #define mmDC_ABM1_HG_RESULT_9                                                   0x1663
100  #define mmDC_ABM1_HG_RESULT_10                                                  0x1664
101  #define mmDC_ABM1_HG_RESULT_11                                                  0x1665
102  #define mmDC_ABM1_HG_RESULT_12                                                  0x1666
103  #define mmDC_ABM1_HG_RESULT_13                                                  0x1667
104  #define mmDC_ABM1_HG_RESULT_14                                                  0x1668
105  #define mmDC_ABM1_HG_RESULT_15                                                  0x1669
106  #define mmDC_ABM1_HG_RESULT_16                                                  0x166a
107  #define mmDC_ABM1_HG_RESULT_17                                                  0x166b
108  #define mmDC_ABM1_HG_RESULT_18                                                  0x166c
109  #define mmDC_ABM1_HG_RESULT_19                                                  0x166d
110  #define mmDC_ABM1_HG_RESULT_20                                                  0x166e
111  #define mmDC_ABM1_HG_RESULT_21                                                  0x166f
112  #define mmDC_ABM1_HG_RESULT_22                                                  0x1670
113  #define mmDC_ABM1_HG_RESULT_23                                                  0x1671
114  #define mmDC_ABM1_HG_RESULT_24                                                  0x1672
115  #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                          0x169b
116  #define mmDC_ABM1_BL_MASTER_LOCK                                                0x169c
117  #define mmABM_TEST_DEBUG_INDEX                                                  0x169e
118  #define mmABM_TEST_DEBUG_DATA                                                   0x169f
119  #define mmCRTC_H_BLANK_EARLY_NUM                                                0x1b7d
120  #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                          0x1b7d
121  #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                          0x1d7d
122  #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                          0x1f7d
123  #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                          0x417d
124  #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                          0x437d
125  #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                          0x457d
126  #define mmCRTC_H_TOTAL                                                          0x1b80
127  #define mmCRTC0_CRTC_H_TOTAL                                                    0x1b80
128  #define mmCRTC1_CRTC_H_TOTAL                                                    0x1d80
129  #define mmCRTC2_CRTC_H_TOTAL                                                    0x1f80
130  #define mmCRTC3_CRTC_H_TOTAL                                                    0x4180
131  #define mmCRTC4_CRTC_H_TOTAL                                                    0x4380
132  #define mmCRTC5_CRTC_H_TOTAL                                                    0x4580
133  #define mmCRTC_H_BLANK_START_END                                                0x1b81
134  #define mmCRTC0_CRTC_H_BLANK_START_END                                          0x1b81
135  #define mmCRTC1_CRTC_H_BLANK_START_END                                          0x1d81
136  #define mmCRTC2_CRTC_H_BLANK_START_END                                          0x1f81
137  #define mmCRTC3_CRTC_H_BLANK_START_END                                          0x4181
138  #define mmCRTC4_CRTC_H_BLANK_START_END                                          0x4381
139  #define mmCRTC5_CRTC_H_BLANK_START_END                                          0x4581
140  #define mmCRTC_H_SYNC_A                                                         0x1b82
141  #define mmCRTC0_CRTC_H_SYNC_A                                                   0x1b82
142  #define mmCRTC1_CRTC_H_SYNC_A                                                   0x1d82
143  #define mmCRTC2_CRTC_H_SYNC_A                                                   0x1f82
144  #define mmCRTC3_CRTC_H_SYNC_A                                                   0x4182
145  #define mmCRTC4_CRTC_H_SYNC_A                                                   0x4382
146  #define mmCRTC5_CRTC_H_SYNC_A                                                   0x4582
147  #define mmCRTC_H_SYNC_A_CNTL                                                    0x1b83
148  #define mmCRTC0_CRTC_H_SYNC_A_CNTL                                              0x1b83
149  #define mmCRTC1_CRTC_H_SYNC_A_CNTL                                              0x1d83
150  #define mmCRTC2_CRTC_H_SYNC_A_CNTL                                              0x1f83
151  #define mmCRTC3_CRTC_H_SYNC_A_CNTL                                              0x4183
152  #define mmCRTC4_CRTC_H_SYNC_A_CNTL                                              0x4383
153  #define mmCRTC5_CRTC_H_SYNC_A_CNTL                                              0x4583
154  #define mmCRTC_H_SYNC_B                                                         0x1b84
155  #define mmCRTC0_CRTC_H_SYNC_B                                                   0x1b84
156  #define mmCRTC1_CRTC_H_SYNC_B                                                   0x1d84
157  #define mmCRTC2_CRTC_H_SYNC_B                                                   0x1f84
158  #define mmCRTC3_CRTC_H_SYNC_B                                                   0x4184
159  #define mmCRTC4_CRTC_H_SYNC_B                                                   0x4384
160  #define mmCRTC5_CRTC_H_SYNC_B                                                   0x4584
161  #define mmCRTC_H_SYNC_B_CNTL                                                    0x1b85
162  #define mmCRTC0_CRTC_H_SYNC_B_CNTL                                              0x1b85
163  #define mmCRTC1_CRTC_H_SYNC_B_CNTL                                              0x1d85
164  #define mmCRTC2_CRTC_H_SYNC_B_CNTL                                              0x1f85
165  #define mmCRTC3_CRTC_H_SYNC_B_CNTL                                              0x4185
166  #define mmCRTC4_CRTC_H_SYNC_B_CNTL                                              0x4385
167  #define mmCRTC5_CRTC_H_SYNC_B_CNTL                                              0x4585
168  #define mmCRTC_VBI_END                                                          0x1b86
169  #define mmCRTC0_CRTC_VBI_END                                                    0x1b86
170  #define mmCRTC1_CRTC_VBI_END                                                    0x1d86
171  #define mmCRTC2_CRTC_VBI_END                                                    0x1f86
172  #define mmCRTC3_CRTC_VBI_END                                                    0x4186
173  #define mmCRTC4_CRTC_VBI_END                                                    0x4386
174  #define mmCRTC5_CRTC_VBI_END                                                    0x4586
175  #define mmCRTC_V_TOTAL                                                          0x1b87
176  #define mmCRTC0_CRTC_V_TOTAL                                                    0x1b87
177  #define mmCRTC1_CRTC_V_TOTAL                                                    0x1d87
178  #define mmCRTC2_CRTC_V_TOTAL                                                    0x1f87
179  #define mmCRTC3_CRTC_V_TOTAL                                                    0x4187
180  #define mmCRTC4_CRTC_V_TOTAL                                                    0x4387
181  #define mmCRTC5_CRTC_V_TOTAL                                                    0x4587
182  #define mmCRTC_V_TOTAL_MIN                                                      0x1b88
183  #define mmCRTC0_CRTC_V_TOTAL_MIN                                                0x1b88
184  #define mmCRTC1_CRTC_V_TOTAL_MIN                                                0x1d88
185  #define mmCRTC2_CRTC_V_TOTAL_MIN                                                0x1f88
186  #define mmCRTC3_CRTC_V_TOTAL_MIN                                                0x4188
187  #define mmCRTC4_CRTC_V_TOTAL_MIN                                                0x4388
188  #define mmCRTC5_CRTC_V_TOTAL_MIN                                                0x4588
189  #define mmCRTC_V_TOTAL_MAX                                                      0x1b89
190  #define mmCRTC0_CRTC_V_TOTAL_MAX                                                0x1b89
191  #define mmCRTC1_CRTC_V_TOTAL_MAX                                                0x1d89
192  #define mmCRTC2_CRTC_V_TOTAL_MAX                                                0x1f89
193  #define mmCRTC3_CRTC_V_TOTAL_MAX                                                0x4189
194  #define mmCRTC4_CRTC_V_TOTAL_MAX                                                0x4389
195  #define mmCRTC5_CRTC_V_TOTAL_MAX                                                0x4589
196  #define mmCRTC_V_TOTAL_CONTROL                                                  0x1b8a
197  #define mmCRTC0_CRTC_V_TOTAL_CONTROL                                            0x1b8a
198  #define mmCRTC1_CRTC_V_TOTAL_CONTROL                                            0x1d8a
199  #define mmCRTC2_CRTC_V_TOTAL_CONTROL                                            0x1f8a
200  #define mmCRTC3_CRTC_V_TOTAL_CONTROL                                            0x418a
201  #define mmCRTC4_CRTC_V_TOTAL_CONTROL                                            0x438a
202  #define mmCRTC5_CRTC_V_TOTAL_CONTROL                                            0x458a
203  #define mmCRTC_V_TOTAL_INT_STATUS                                               0x1b8b
204  #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                         0x1b8b
205  #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                         0x1d8b
206  #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                         0x1f8b
207  #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                         0x418b
208  #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                         0x438b
209  #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                         0x458b
210  #define mmCRTC_VSYNC_NOM_INT_STATUS                                             0x1b8c
211  #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                       0x1b8c
212  #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                       0x1d8c
213  #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                       0x1f8c
214  #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                       0x418c
215  #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                       0x438c
216  #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                       0x458c
217  #define mmCRTC_V_BLANK_START_END                                                0x1b8d
218  #define mmCRTC0_CRTC_V_BLANK_START_END                                          0x1b8d
219  #define mmCRTC1_CRTC_V_BLANK_START_END                                          0x1d8d
220  #define mmCRTC2_CRTC_V_BLANK_START_END                                          0x1f8d
221  #define mmCRTC3_CRTC_V_BLANK_START_END                                          0x418d
222  #define mmCRTC4_CRTC_V_BLANK_START_END                                          0x438d
223  #define mmCRTC5_CRTC_V_BLANK_START_END                                          0x458d
224  #define mmCRTC_V_SYNC_A                                                         0x1b8e
225  #define mmCRTC0_CRTC_V_SYNC_A                                                   0x1b8e
226  #define mmCRTC1_CRTC_V_SYNC_A                                                   0x1d8e
227  #define mmCRTC2_CRTC_V_SYNC_A                                                   0x1f8e
228  #define mmCRTC3_CRTC_V_SYNC_A                                                   0x418e
229  #define mmCRTC4_CRTC_V_SYNC_A                                                   0x438e
230  #define mmCRTC5_CRTC_V_SYNC_A                                                   0x458e
231  #define mmCRTC_V_SYNC_A_CNTL                                                    0x1b8f
232  #define mmCRTC0_CRTC_V_SYNC_A_CNTL                                              0x1b8f
233  #define mmCRTC1_CRTC_V_SYNC_A_CNTL                                              0x1d8f
234  #define mmCRTC2_CRTC_V_SYNC_A_CNTL                                              0x1f8f
235  #define mmCRTC3_CRTC_V_SYNC_A_CNTL                                              0x418f
236  #define mmCRTC4_CRTC_V_SYNC_A_CNTL                                              0x438f
237  #define mmCRTC5_CRTC_V_SYNC_A_CNTL                                              0x458f
238  #define mmCRTC_V_SYNC_B                                                         0x1b90
239  #define mmCRTC0_CRTC_V_SYNC_B                                                   0x1b90
240  #define mmCRTC1_CRTC_V_SYNC_B                                                   0x1d90
241  #define mmCRTC2_CRTC_V_SYNC_B                                                   0x1f90
242  #define mmCRTC3_CRTC_V_SYNC_B                                                   0x4190
243  #define mmCRTC4_CRTC_V_SYNC_B                                                   0x4390
244  #define mmCRTC5_CRTC_V_SYNC_B                                                   0x4590
245  #define mmCRTC_V_SYNC_B_CNTL                                                    0x1b91
246  #define mmCRTC0_CRTC_V_SYNC_B_CNTL                                              0x1b91
247  #define mmCRTC1_CRTC_V_SYNC_B_CNTL                                              0x1d91
248  #define mmCRTC2_CRTC_V_SYNC_B_CNTL                                              0x1f91
249  #define mmCRTC3_CRTC_V_SYNC_B_CNTL                                              0x4191
250  #define mmCRTC4_CRTC_V_SYNC_B_CNTL                                              0x4391
251  #define mmCRTC5_CRTC_V_SYNC_B_CNTL                                              0x4591
252  #define mmCRTC_DTMTEST_CNTL                                                     0x1b92
253  #define mmCRTC0_CRTC_DTMTEST_CNTL                                               0x1b92
254  #define mmCRTC1_CRTC_DTMTEST_CNTL                                               0x1d92
255  #define mmCRTC2_CRTC_DTMTEST_CNTL                                               0x1f92
256  #define mmCRTC3_CRTC_DTMTEST_CNTL                                               0x4192
257  #define mmCRTC4_CRTC_DTMTEST_CNTL                                               0x4392
258  #define mmCRTC5_CRTC_DTMTEST_CNTL                                               0x4592
259  #define mmCRTC_DTMTEST_STATUS_POSITION                                          0x1b93
260  #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                    0x1b93
261  #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                    0x1d93
262  #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                    0x1f93
263  #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                    0x4193
264  #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                    0x4393
265  #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                    0x4593
266  #define mmCRTC_TRIGA_CNTL                                                       0x1b94
267  #define mmCRTC0_CRTC_TRIGA_CNTL                                                 0x1b94
268  #define mmCRTC1_CRTC_TRIGA_CNTL                                                 0x1d94
269  #define mmCRTC2_CRTC_TRIGA_CNTL                                                 0x1f94
270  #define mmCRTC3_CRTC_TRIGA_CNTL                                                 0x4194
271  #define mmCRTC4_CRTC_TRIGA_CNTL                                                 0x4394
272  #define mmCRTC5_CRTC_TRIGA_CNTL                                                 0x4594
273  #define mmCRTC_TRIGA_MANUAL_TRIG                                                0x1b95
274  #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                          0x1b95
275  #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                          0x1d95
276  #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                          0x1f95
277  #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                          0x4195
278  #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                          0x4395
279  #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                          0x4595
280  #define mmCRTC_TRIGB_CNTL                                                       0x1b96
281  #define mmCRTC0_CRTC_TRIGB_CNTL                                                 0x1b96
282  #define mmCRTC1_CRTC_TRIGB_CNTL                                                 0x1d96
283  #define mmCRTC2_CRTC_TRIGB_CNTL                                                 0x1f96
284  #define mmCRTC3_CRTC_TRIGB_CNTL                                                 0x4196
285  #define mmCRTC4_CRTC_TRIGB_CNTL                                                 0x4396
286  #define mmCRTC5_CRTC_TRIGB_CNTL                                                 0x4596
287  #define mmCRTC_TRIGB_MANUAL_TRIG                                                0x1b97
288  #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                          0x1b97
289  #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                          0x1d97
290  #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                          0x1f97
291  #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                          0x4197
292  #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                          0x4397
293  #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                          0x4597
294  #define mmCRTC_FORCE_COUNT_NOW_CNTL                                             0x1b98
295  #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1b98
296  #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1d98
297  #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                       0x1f98
298  #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4198
299  #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4398
300  #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                       0x4598
301  #define mmCRTC_FLOW_CONTROL                                                     0x1b99
302  #define mmCRTC0_CRTC_FLOW_CONTROL                                               0x1b99
303  #define mmCRTC1_CRTC_FLOW_CONTROL                                               0x1d99
304  #define mmCRTC2_CRTC_FLOW_CONTROL                                               0x1f99
305  #define mmCRTC3_CRTC_FLOW_CONTROL                                               0x4199
306  #define mmCRTC4_CRTC_FLOW_CONTROL                                               0x4399
307  #define mmCRTC5_CRTC_FLOW_CONTROL                                               0x4599
308  #define mmCRTC_STEREO_FORCE_NEXT_EYE                                            0x1b9a
309  #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1b9a
310  #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1d9a
311  #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                      0x1f9a
312  #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                      0x419a
313  #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                      0x439a
314  #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                      0x459a
315  #define mmCRTC_AVSYNC_COUNTER                                                   0x1b9b
316  #define mmCRTC0_CRTC_AVSYNC_COUNTER                                             0x1b9b
317  #define mmCRTC1_CRTC_AVSYNC_COUNTER                                             0x1d9b
318  #define mmCRTC2_CRTC_AVSYNC_COUNTER                                             0x1f9b
319  #define mmCRTC3_CRTC_AVSYNC_COUNTER                                             0x419b
320  #define mmCRTC4_CRTC_AVSYNC_COUNTER                                             0x439b
321  #define mmCRTC5_CRTC_AVSYNC_COUNTER                                             0x459b
322  #define mmCRTC_CONTROL                                                          0x1b9c
323  #define mmCRTC0_CRTC_CONTROL                                                    0x1b9c
324  #define mmCRTC1_CRTC_CONTROL                                                    0x1d9c
325  #define mmCRTC2_CRTC_CONTROL                                                    0x1f9c
326  #define mmCRTC3_CRTC_CONTROL                                                    0x419c
327  #define mmCRTC4_CRTC_CONTROL                                                    0x439c
328  #define mmCRTC5_CRTC_CONTROL                                                    0x459c
329  #define mmCRTC_BLANK_CONTROL                                                    0x1b9d
330  #define mmCRTC0_CRTC_BLANK_CONTROL                                              0x1b9d
331  #define mmCRTC1_CRTC_BLANK_CONTROL                                              0x1d9d
332  #define mmCRTC2_CRTC_BLANK_CONTROL                                              0x1f9d
333  #define mmCRTC3_CRTC_BLANK_CONTROL                                              0x419d
334  #define mmCRTC4_CRTC_BLANK_CONTROL                                              0x439d
335  #define mmCRTC5_CRTC_BLANK_CONTROL                                              0x459d
336  #define mmCRTC_INTERLACE_CONTROL                                                0x1b9e
337  #define mmCRTC0_CRTC_INTERLACE_CONTROL                                          0x1b9e
338  #define mmCRTC1_CRTC_INTERLACE_CONTROL                                          0x1d9e
339  #define mmCRTC2_CRTC_INTERLACE_CONTROL                                          0x1f9e
340  #define mmCRTC3_CRTC_INTERLACE_CONTROL                                          0x419e
341  #define mmCRTC4_CRTC_INTERLACE_CONTROL                                          0x439e
342  #define mmCRTC5_CRTC_INTERLACE_CONTROL                                          0x459e
343  #define mmCRTC_INTERLACE_STATUS                                                 0x1b9f
344  #define mmCRTC0_CRTC_INTERLACE_STATUS                                           0x1b9f
345  #define mmCRTC1_CRTC_INTERLACE_STATUS                                           0x1d9f
346  #define mmCRTC2_CRTC_INTERLACE_STATUS                                           0x1f9f
347  #define mmCRTC3_CRTC_INTERLACE_STATUS                                           0x419f
348  #define mmCRTC4_CRTC_INTERLACE_STATUS                                           0x439f
349  #define mmCRTC5_CRTC_INTERLACE_STATUS                                           0x459f
350  #define mmCRTC_FIELD_INDICATION_CONTROL                                         0x1ba0
351  #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                   0x1ba0
352  #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                   0x1da0
353  #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                   0x1fa0
354  #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                   0x41a0
355  #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                   0x43a0
356  #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                   0x45a0
357  #define mmCRTC_PIXEL_DATA_READBACK0                                             0x1ba1
358  #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                       0x1ba1
359  #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                       0x1da1
360  #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                       0x1fa1
361  #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                       0x41a1
362  #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                       0x43a1
363  #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                       0x45a1
364  #define mmCRTC_PIXEL_DATA_READBACK1                                             0x1ba2
365  #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                       0x1ba2
366  #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                       0x1da2
367  #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                       0x1fa2
368  #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                       0x41a2
369  #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                       0x43a2
370  #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                       0x45a2
371  #define mmCRTC_STATUS                                                           0x1ba3
372  #define mmCRTC0_CRTC_STATUS                                                     0x1ba3
373  #define mmCRTC1_CRTC_STATUS                                                     0x1da3
374  #define mmCRTC2_CRTC_STATUS                                                     0x1fa3
375  #define mmCRTC3_CRTC_STATUS                                                     0x41a3
376  #define mmCRTC4_CRTC_STATUS                                                     0x43a3
377  #define mmCRTC5_CRTC_STATUS                                                     0x45a3
378  #define mmCRTC_STATUS_POSITION                                                  0x1ba4
379  #define mmCRTC0_CRTC_STATUS_POSITION                                            0x1ba4
380  #define mmCRTC1_CRTC_STATUS_POSITION                                            0x1da4
381  #define mmCRTC2_CRTC_STATUS_POSITION                                            0x1fa4
382  #define mmCRTC3_CRTC_STATUS_POSITION                                            0x41a4
383  #define mmCRTC4_CRTC_STATUS_POSITION                                            0x43a4
384  #define mmCRTC5_CRTC_STATUS_POSITION                                            0x45a4
385  #define mmCRTC_NOM_VERT_POSITION                                                0x1ba5
386  #define mmCRTC0_CRTC_NOM_VERT_POSITION                                          0x1ba5
387  #define mmCRTC1_CRTC_NOM_VERT_POSITION                                          0x1da5
388  #define mmCRTC2_CRTC_NOM_VERT_POSITION                                          0x1fa5
389  #define mmCRTC3_CRTC_NOM_VERT_POSITION                                          0x41a5
390  #define mmCRTC4_CRTC_NOM_VERT_POSITION                                          0x43a5
391  #define mmCRTC5_CRTC_NOM_VERT_POSITION                                          0x45a5
392  #define mmCRTC_STATUS_FRAME_COUNT                                               0x1ba6
393  #define mmCRTC0_CRTC_STATUS_FRAME_COUNT                                         0x1ba6
394  #define mmCRTC1_CRTC_STATUS_FRAME_COUNT                                         0x1da6
395  #define mmCRTC2_CRTC_STATUS_FRAME_COUNT                                         0x1fa6
396  #define mmCRTC3_CRTC_STATUS_FRAME_COUNT                                         0x41a6
397  #define mmCRTC4_CRTC_STATUS_FRAME_COUNT                                         0x43a6
398  #define mmCRTC5_CRTC_STATUS_FRAME_COUNT                                         0x45a6
399  #define mmCRTC_STATUS_VF_COUNT                                                  0x1ba7
400  #define mmCRTC0_CRTC_STATUS_VF_COUNT                                            0x1ba7
401  #define mmCRTC1_CRTC_STATUS_VF_COUNT                                            0x1da7
402  #define mmCRTC2_CRTC_STATUS_VF_COUNT                                            0x1fa7
403  #define mmCRTC3_CRTC_STATUS_VF_COUNT                                            0x41a7
404  #define mmCRTC4_CRTC_STATUS_VF_COUNT                                            0x43a7
405  #define mmCRTC5_CRTC_STATUS_VF_COUNT                                            0x45a7
406  #define mmCRTC_STATUS_HV_COUNT                                                  0x1ba8
407  #define mmCRTC0_CRTC_STATUS_HV_COUNT                                            0x1ba8
408  #define mmCRTC1_CRTC_STATUS_HV_COUNT                                            0x1da8
409  #define mmCRTC2_CRTC_STATUS_HV_COUNT                                            0x1fa8
410  #define mmCRTC3_CRTC_STATUS_HV_COUNT                                            0x41a8
411  #define mmCRTC4_CRTC_STATUS_HV_COUNT                                            0x43a8
412  #define mmCRTC5_CRTC_STATUS_HV_COUNT                                            0x45a8
413  #define mmCRTC_COUNT_CONTROL                                                    0x1ba9
414  #define mmCRTC0_CRTC_COUNT_CONTROL                                              0x1ba9
415  #define mmCRTC1_CRTC_COUNT_CONTROL                                              0x1da9
416  #define mmCRTC2_CRTC_COUNT_CONTROL                                              0x1fa9
417  #define mmCRTC3_CRTC_COUNT_CONTROL                                              0x41a9
418  #define mmCRTC4_CRTC_COUNT_CONTROL                                              0x43a9
419  #define mmCRTC5_CRTC_COUNT_CONTROL                                              0x45a9
420  #define mmCRTC_COUNT_RESET                                                      0x1baa
421  #define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
422  #define mmCRTC1_CRTC_COUNT_RESET                                                0x1daa
423  #define mmCRTC2_CRTC_COUNT_RESET                                                0x1faa
424  #define mmCRTC3_CRTC_COUNT_RESET                                                0x41aa
425  #define mmCRTC4_CRTC_COUNT_RESET                                                0x43aa
426  #define mmCRTC5_CRTC_COUNT_RESET                                                0x45aa
427  #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                     0x1bab
428  #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1bab
429  #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1dab
430  #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x1fab
431  #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x41ab
432  #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x43ab
433  #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                               0x45ab
434  #define mmCRTC_VERT_SYNC_CONTROL                                                0x1bac
435  #define mmCRTC0_CRTC_VERT_SYNC_CONTROL                                          0x1bac
436  #define mmCRTC1_CRTC_VERT_SYNC_CONTROL                                          0x1dac
437  #define mmCRTC2_CRTC_VERT_SYNC_CONTROL                                          0x1fac
438  #define mmCRTC3_CRTC_VERT_SYNC_CONTROL                                          0x41ac
439  #define mmCRTC4_CRTC_VERT_SYNC_CONTROL                                          0x43ac
440  #define mmCRTC5_CRTC_VERT_SYNC_CONTROL                                          0x45ac
441  #define mmCRTC_STEREO_STATUS                                                    0x1bad
442  #define mmCRTC0_CRTC_STEREO_STATUS                                              0x1bad
443  #define mmCRTC1_CRTC_STEREO_STATUS                                              0x1dad
444  #define mmCRTC2_CRTC_STEREO_STATUS                                              0x1fad
445  #define mmCRTC3_CRTC_STEREO_STATUS                                              0x41ad
446  #define mmCRTC4_CRTC_STEREO_STATUS                                              0x43ad
447  #define mmCRTC5_CRTC_STEREO_STATUS                                              0x45ad
448  #define mmCRTC_STEREO_CONTROL                                                   0x1bae
449  #define mmCRTC0_CRTC_STEREO_CONTROL                                             0x1bae
450  #define mmCRTC1_CRTC_STEREO_CONTROL                                             0x1dae
451  #define mmCRTC2_CRTC_STEREO_CONTROL                                             0x1fae
452  #define mmCRTC3_CRTC_STEREO_CONTROL                                             0x41ae
453  #define mmCRTC4_CRTC_STEREO_CONTROL                                             0x43ae
454  #define mmCRTC5_CRTC_STEREO_CONTROL                                             0x45ae
455  #define mmCRTC_SNAPSHOT_STATUS                                                  0x1baf
456  #define mmCRTC0_CRTC_SNAPSHOT_STATUS                                            0x1baf
457  #define mmCRTC1_CRTC_SNAPSHOT_STATUS                                            0x1daf
458  #define mmCRTC2_CRTC_SNAPSHOT_STATUS                                            0x1faf
459  #define mmCRTC3_CRTC_SNAPSHOT_STATUS                                            0x41af
460  #define mmCRTC4_CRTC_SNAPSHOT_STATUS                                            0x43af
461  #define mmCRTC5_CRTC_SNAPSHOT_STATUS                                            0x45af
462  #define mmCRTC_SNAPSHOT_CONTROL                                                 0x1bb0
463  #define mmCRTC0_CRTC_SNAPSHOT_CONTROL                                           0x1bb0
464  #define mmCRTC1_CRTC_SNAPSHOT_CONTROL                                           0x1db0
465  #define mmCRTC2_CRTC_SNAPSHOT_CONTROL                                           0x1fb0
466  #define mmCRTC3_CRTC_SNAPSHOT_CONTROL                                           0x41b0
467  #define mmCRTC4_CRTC_SNAPSHOT_CONTROL                                           0x43b0
468  #define mmCRTC5_CRTC_SNAPSHOT_CONTROL                                           0x45b0
469  #define mmCRTC_SNAPSHOT_POSITION                                                0x1bb1
470  #define mmCRTC0_CRTC_SNAPSHOT_POSITION                                          0x1bb1
471  #define mmCRTC1_CRTC_SNAPSHOT_POSITION                                          0x1db1
472  #define mmCRTC2_CRTC_SNAPSHOT_POSITION                                          0x1fb1
473  #define mmCRTC3_CRTC_SNAPSHOT_POSITION                                          0x41b1
474  #define mmCRTC4_CRTC_SNAPSHOT_POSITION                                          0x43b1
475  #define mmCRTC5_CRTC_SNAPSHOT_POSITION                                          0x45b1
476  #define mmCRTC_SNAPSHOT_FRAME                                                   0x1bb2
477  #define mmCRTC0_CRTC_SNAPSHOT_FRAME                                             0x1bb2
478  #define mmCRTC1_CRTC_SNAPSHOT_FRAME                                             0x1db2
479  #define mmCRTC2_CRTC_SNAPSHOT_FRAME                                             0x1fb2
480  #define mmCRTC3_CRTC_SNAPSHOT_FRAME                                             0x41b2
481  #define mmCRTC4_CRTC_SNAPSHOT_FRAME                                             0x43b2
482  #define mmCRTC5_CRTC_SNAPSHOT_FRAME                                             0x45b2
483  #define mmCRTC_START_LINE_CONTROL                                               0x1bb3
484  #define mmCRTC0_CRTC_START_LINE_CONTROL                                         0x1bb3
485  #define mmCRTC1_CRTC_START_LINE_CONTROL                                         0x1db3
486  #define mmCRTC2_CRTC_START_LINE_CONTROL                                         0x1fb3
487  #define mmCRTC3_CRTC_START_LINE_CONTROL                                         0x41b3
488  #define mmCRTC4_CRTC_START_LINE_CONTROL                                         0x43b3
489  #define mmCRTC5_CRTC_START_LINE_CONTROL                                         0x45b3
490  #define mmCRTC_INTERRUPT_CONTROL                                                0x1bb4
491  #define mmCRTC0_CRTC_INTERRUPT_CONTROL                                          0x1bb4
492  #define mmCRTC1_CRTC_INTERRUPT_CONTROL                                          0x1db4
493  #define mmCRTC2_CRTC_INTERRUPT_CONTROL                                          0x1fb4
494  #define mmCRTC3_CRTC_INTERRUPT_CONTROL                                          0x41b4
495  #define mmCRTC4_CRTC_INTERRUPT_CONTROL                                          0x43b4
496  #define mmCRTC5_CRTC_INTERRUPT_CONTROL                                          0x45b4
497  #define mmCRTC_UPDATE_LOCK                                                      0x1bb5
498  #define mmCRTC0_CRTC_UPDATE_LOCK                                                0x1bb5
499  #define mmCRTC1_CRTC_UPDATE_LOCK                                                0x1db5
500  #define mmCRTC2_CRTC_UPDATE_LOCK                                                0x1fb5
501  #define mmCRTC3_CRTC_UPDATE_LOCK                                                0x41b5
502  #define mmCRTC4_CRTC_UPDATE_LOCK                                                0x43b5
503  #define mmCRTC5_CRTC_UPDATE_LOCK                                                0x45b5
504  #define mmCRTC_DOUBLE_BUFFER_CONTROL                                            0x1bb6
505  #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1bb6
506  #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1db6
507  #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                      0x1fb6
508  #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                      0x41b6
509  #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                      0x43b6
510  #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                      0x45b6
511  #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE                                       0x1bb7
512  #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1bb7
513  #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1db7
514  #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x1fb7
515  #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x41b7
516  #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x43b7
517  #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                 0x45b7
518  #define mmCRTC_TEST_PATTERN_CONTROL                                             0x1bba
519  #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                       0x1bba
520  #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                       0x1dba
521  #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                       0x1fba
522  #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                       0x41ba
523  #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                       0x43ba
524  #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                       0x45ba
525  #define mmCRTC_TEST_PATTERN_PARAMETERS                                          0x1bbb
526  #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                    0x1bbb
527  #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                    0x1dbb
528  #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                    0x1fbb
529  #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                    0x41bb
530  #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                    0x43bb
531  #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                    0x45bb
532  #define mmCRTC_TEST_PATTERN_COLOR                                               0x1bbc
533  #define mmCRTC0_CRTC_TEST_PATTERN_COLOR                                         0x1bbc
534  #define mmCRTC1_CRTC_TEST_PATTERN_COLOR                                         0x1dbc
535  #define mmCRTC2_CRTC_TEST_PATTERN_COLOR                                         0x1fbc
536  #define mmCRTC3_CRTC_TEST_PATTERN_COLOR                                         0x41bc
537  #define mmCRTC4_CRTC_TEST_PATTERN_COLOR                                         0x43bc
538  #define mmCRTC5_CRTC_TEST_PATTERN_COLOR                                         0x45bc
539  #define mmCRTC_MASTER_UPDATE_LOCK                                               0x1bbd
540  #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK                                         0x1bbd
541  #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK                                         0x1dbd
542  #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK                                         0x1fbd
543  #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK                                         0x41bd
544  #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK                                         0x43bd
545  #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK                                         0x45bd
546  #define mmCRTC_MASTER_UPDATE_MODE                                               0x1bbe
547  #define mmCRTC0_CRTC_MASTER_UPDATE_MODE                                         0x1bbe
548  #define mmCRTC1_CRTC_MASTER_UPDATE_MODE                                         0x1dbe
549  #define mmCRTC2_CRTC_MASTER_UPDATE_MODE                                         0x1fbe
550  #define mmCRTC3_CRTC_MASTER_UPDATE_MODE                                         0x41be
551  #define mmCRTC4_CRTC_MASTER_UPDATE_MODE                                         0x43be
552  #define mmCRTC5_CRTC_MASTER_UPDATE_MODE                                         0x45be
553  #define mmCRTC_MVP_INBAND_CNTL_INSERT                                           0x1bbf
554  #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1bbf
555  #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1dbf
556  #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                     0x1fbf
557  #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                     0x41bf
558  #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                     0x43bf
559  #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                     0x45bf
560  #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER                                     0x1bc0
561  #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1bc0
562  #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1dc0
563  #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x1fc0
564  #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x41c0
565  #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x43c0
566  #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                               0x45c0
567  #define mmCRTC_MVP_STATUS                                                       0x1bc1
568  #define mmCRTC0_CRTC_MVP_STATUS                                                 0x1bc1
569  #define mmCRTC1_CRTC_MVP_STATUS                                                 0x1dc1
570  #define mmCRTC2_CRTC_MVP_STATUS                                                 0x1fc1
571  #define mmCRTC3_CRTC_MVP_STATUS                                                 0x41c1
572  #define mmCRTC4_CRTC_MVP_STATUS                                                 0x43c1
573  #define mmCRTC5_CRTC_MVP_STATUS                                                 0x45c1
574  #define mmCRTC_MASTER_EN                                                        0x1bc2
575  #define mmCRTC0_CRTC_MASTER_EN                                                  0x1bc2
576  #define mmCRTC1_CRTC_MASTER_EN                                                  0x1dc2
577  #define mmCRTC2_CRTC_MASTER_EN                                                  0x1fc2
578  #define mmCRTC3_CRTC_MASTER_EN                                                  0x41c2
579  #define mmCRTC4_CRTC_MASTER_EN                                                  0x43c2
580  #define mmCRTC5_CRTC_MASTER_EN                                                  0x45c2
581  #define mmCRTC_ALLOW_STOP_OFF_V_CNT                                             0x1bc3
582  #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1bc3
583  #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1dc3
584  #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x1fc3
585  #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x41c3
586  #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x43c3
587  #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                       0x45c3
588  #define mmCRTC_V_UPDATE_INT_STATUS                                              0x1bc4
589  #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                        0x1bc4
590  #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                        0x1dc4
591  #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                        0x1fc4
592  #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                        0x41c4
593  #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                        0x43c4
594  #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                        0x45c4
595  #define mmCRTC_OVERSCAN_COLOR                                                   0x1bc8
596  #define mmCRTC0_CRTC_OVERSCAN_COLOR                                             0x1bc8
597  #define mmCRTC1_CRTC_OVERSCAN_COLOR                                             0x1dc8
598  #define mmCRTC2_CRTC_OVERSCAN_COLOR                                             0x1fc8
599  #define mmCRTC3_CRTC_OVERSCAN_COLOR                                             0x41c8
600  #define mmCRTC4_CRTC_OVERSCAN_COLOR                                             0x43c8
601  #define mmCRTC5_CRTC_OVERSCAN_COLOR                                             0x45c8
602  #define mmCRTC_OVERSCAN_COLOR_EXT                                               0x1bc9
603  #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                         0x1bc9
604  #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                         0x1dc9
605  #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                         0x1fc9
606  #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                         0x41c9
607  #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                         0x43c9
608  #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                         0x45c9
609  #define mmCRTC_BLANK_DATA_COLOR                                                 0x1bca
610  #define mmCRTC0_CRTC_BLANK_DATA_COLOR                                           0x1bca
611  #define mmCRTC1_CRTC_BLANK_DATA_COLOR                                           0x1dca
612  #define mmCRTC2_CRTC_BLANK_DATA_COLOR                                           0x1fca
613  #define mmCRTC3_CRTC_BLANK_DATA_COLOR                                           0x41ca
614  #define mmCRTC4_CRTC_BLANK_DATA_COLOR                                           0x43ca
615  #define mmCRTC5_CRTC_BLANK_DATA_COLOR                                           0x45ca
616  #define mmCRTC_BLANK_DATA_COLOR_EXT                                             0x1bcb
617  #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                       0x1bcb
618  #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                       0x1dcb
619  #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                       0x1fcb
620  #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                       0x41cb
621  #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                       0x43cb
622  #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                       0x45cb
623  #define mmCRTC_BLACK_COLOR                                                      0x1bcc
624  #define mmCRTC0_CRTC_BLACK_COLOR                                                0x1bcc
625  #define mmCRTC1_CRTC_BLACK_COLOR                                                0x1dcc
626  #define mmCRTC2_CRTC_BLACK_COLOR                                                0x1fcc
627  #define mmCRTC3_CRTC_BLACK_COLOR                                                0x41cc
628  #define mmCRTC4_CRTC_BLACK_COLOR                                                0x43cc
629  #define mmCRTC5_CRTC_BLACK_COLOR                                                0x45cc
630  #define mmCRTC_BLACK_COLOR_EXT                                                  0x1bcd
631  #define mmCRTC0_CRTC_BLACK_COLOR_EXT                                            0x1bcd
632  #define mmCRTC1_CRTC_BLACK_COLOR_EXT                                            0x1dcd
633  #define mmCRTC2_CRTC_BLACK_COLOR_EXT                                            0x1fcd
634  #define mmCRTC3_CRTC_BLACK_COLOR_EXT                                            0x41cd
635  #define mmCRTC4_CRTC_BLACK_COLOR_EXT                                            0x43cd
636  #define mmCRTC5_CRTC_BLACK_COLOR_EXT                                            0x45cd
637  #define mmCRTC_VERTICAL_INTERRUPT0_POSITION                                     0x1bce
638  #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1bce
639  #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1dce
640  #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x1fce
641  #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x41ce
642  #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x43ce
643  #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                               0x45ce
644  #define mmCRTC_VERTICAL_INTERRUPT0_CONTROL                                      0x1bcf
645  #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1bcf
646  #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1dcf
647  #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x1fcf
648  #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x41cf
649  #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x43cf
650  #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                0x45cf
651  #define mmCRTC_VERTICAL_INTERRUPT1_POSITION                                     0x1bd0
652  #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1bd0
653  #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1dd0
654  #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x1fd0
655  #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x41d0
656  #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x43d0
657  #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                               0x45d0
658  #define mmCRTC_VERTICAL_INTERRUPT1_CONTROL                                      0x1bd1
659  #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1bd1
660  #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1dd1
661  #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x1fd1
662  #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x41d1
663  #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x43d1
664  #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                0x45d1
665  #define mmCRTC_VERTICAL_INTERRUPT2_POSITION                                     0x1bd2
666  #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1bd2
667  #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1dd2
668  #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x1fd2
669  #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x41d2
670  #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x43d2
671  #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                               0x45d2
672  #define mmCRTC_VERTICAL_INTERRUPT2_CONTROL                                      0x1bd3
673  #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1bd3
674  #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1dd3
675  #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x1fd3
676  #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x41d3
677  #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x43d3
678  #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                0x45d3
679  #define mmCRTC_CRC_CNTL                                                         0x1bd4
680  #define mmCRTC0_CRTC_CRC_CNTL                                                   0x1bd4
681  #define mmCRTC1_CRTC_CRC_CNTL                                                   0x1dd4
682  #define mmCRTC2_CRTC_CRC_CNTL                                                   0x1fd4
683  #define mmCRTC3_CRTC_CRC_CNTL                                                   0x41d4
684  #define mmCRTC4_CRTC_CRC_CNTL                                                   0x43d4
685  #define mmCRTC5_CRTC_CRC_CNTL                                                   0x45d4
686  #define mmCRTC_CRC0_WINDOWA_X_CONTROL                                           0x1bd5
687  #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1bd5
688  #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1dd5
689  #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x1fd5
690  #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x41d5
691  #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x43d5
692  #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                     0x45d5
693  #define mmCRTC_CRC0_WINDOWA_Y_CONTROL                                           0x1bd6
694  #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1bd6
695  #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1dd6
696  #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x1fd6
697  #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x41d6
698  #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x43d6
699  #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                     0x45d6
700  #define mmCRTC_CRC0_WINDOWB_X_CONTROL                                           0x1bd7
701  #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1bd7
702  #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1dd7
703  #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x1fd7
704  #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x41d7
705  #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x43d7
706  #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                     0x45d7
707  #define mmCRTC_CRC0_WINDOWB_Y_CONTROL                                           0x1bd8
708  #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1bd8
709  #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1dd8
710  #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x1fd8
711  #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x41d8
712  #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x43d8
713  #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                     0x45d8
714  #define mmCRTC_CRC0_DATA_RG                                                     0x1bd9
715  #define mmCRTC0_CRTC_CRC0_DATA_RG                                               0x1bd9
716  #define mmCRTC1_CRTC_CRC0_DATA_RG                                               0x1dd9
717  #define mmCRTC2_CRTC_CRC0_DATA_RG                                               0x1fd9
718  #define mmCRTC3_CRTC_CRC0_DATA_RG                                               0x41d9
719  #define mmCRTC4_CRTC_CRC0_DATA_RG                                               0x43d9
720  #define mmCRTC5_CRTC_CRC0_DATA_RG                                               0x45d9
721  #define mmCRTC_CRC0_DATA_B                                                      0x1bda
722  #define mmCRTC0_CRTC_CRC0_DATA_B                                                0x1bda
723  #define mmCRTC1_CRTC_CRC0_DATA_B                                                0x1dda
724  #define mmCRTC2_CRTC_CRC0_DATA_B                                                0x1fda
725  #define mmCRTC3_CRTC_CRC0_DATA_B                                                0x41da
726  #define mmCRTC4_CRTC_CRC0_DATA_B                                                0x43da
727  #define mmCRTC5_CRTC_CRC0_DATA_B                                                0x45da
728  #define mmCRTC_CRC1_WINDOWA_X_CONTROL                                           0x1bdb
729  #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1bdb
730  #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1ddb
731  #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x1fdb
732  #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x41db
733  #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x43db
734  #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                     0x45db
735  #define mmCRTC_CRC1_WINDOWA_Y_CONTROL                                           0x1bdc
736  #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1bdc
737  #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1ddc
738  #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x1fdc
739  #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x41dc
740  #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x43dc
741  #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                     0x45dc
742  #define mmCRTC_CRC1_WINDOWB_X_CONTROL                                           0x1bdd
743  #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1bdd
744  #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1ddd
745  #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x1fdd
746  #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x41dd
747  #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x43dd
748  #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                     0x45dd
749  #define mmCRTC_CRC1_WINDOWB_Y_CONTROL                                           0x1bde
750  #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1bde
751  #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1dde
752  #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x1fde
753  #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x41de
754  #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x43de
755  #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                     0x45de
756  #define mmCRTC_CRC1_DATA_RG                                                     0x1bdf
757  #define mmCRTC0_CRTC_CRC1_DATA_RG                                               0x1bdf
758  #define mmCRTC1_CRTC_CRC1_DATA_RG                                               0x1ddf
759  #define mmCRTC2_CRTC_CRC1_DATA_RG                                               0x1fdf
760  #define mmCRTC3_CRTC_CRC1_DATA_RG                                               0x41df
761  #define mmCRTC4_CRTC_CRC1_DATA_RG                                               0x43df
762  #define mmCRTC5_CRTC_CRC1_DATA_RG                                               0x45df
763  #define mmCRTC_CRC1_DATA_B                                                      0x1be0
764  #define mmCRTC0_CRTC_CRC1_DATA_B                                                0x1be0
765  #define mmCRTC1_CRTC_CRC1_DATA_B                                                0x1de0
766  #define mmCRTC2_CRTC_CRC1_DATA_B                                                0x1fe0
767  #define mmCRTC3_CRTC_CRC1_DATA_B                                                0x41e0
768  #define mmCRTC4_CRTC_CRC1_DATA_B                                                0x43e0
769  #define mmCRTC5_CRTC_CRC1_DATA_B                                                0x45e0
770  #define mmCRTC_EXT_TIMING_SYNC_CONTROL                                          0x1be1
771  #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1be1
772  #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1de1
773  #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x1fe1
774  #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x41e1
775  #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x43e1
776  #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                                    0x45e1
777  #define mmCRTC_EXT_TIMING_SYNC_WINDOW_START                                     0x1be2
778  #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1be2
779  #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1de2
780  #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x1fe2
781  #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x41e2
782  #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x43e2
783  #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                               0x45e2
784  #define mmCRTC_EXT_TIMING_SYNC_WINDOW_END                                       0x1be3
785  #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1be3
786  #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1de3
787  #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x1fe3
788  #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x41e3
789  #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x43e3
790  #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                                 0x45e3
791  #define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                           0x1be4
792  #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1be4
793  #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1de4
794  #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x1fe4
795  #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x41e4
796  #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x43e4
797  #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                     0x45e4
798  #define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                0x1be5
799  #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1be5
800  #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1de5
801  #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x1fe5
802  #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x41e5
803  #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x43e5
804  #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                          0x45e5
805  #define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                         0x1be6
806  #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1be6
807  #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1de6
808  #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x1fe6
809  #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x41e6
810  #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x43e6
811  #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                   0x45e6
812  #define mmCRTC_STATIC_SCREEN_CONTROL                                            0x1be7
813  #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                      0x1be7
814  #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                      0x1de7
815  #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                      0x1fe7
816  #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                      0x41e7
817  #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                      0x43e7
818  #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                      0x45e7
819  #define mmCRTC_3D_STRUCTURE_CONTROL                                             0x1b78
820  #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                       0x1b78
821  #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                       0x1d78
822  #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                       0x1f78
823  #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                       0x4178
824  #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                       0x4378
825  #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                       0x4578
826  #define mmCRTC_GSL_VSYNC_GAP                                                    0x1b79
827  #define mmCRTC0_CRTC_GSL_VSYNC_GAP                                              0x1b79
828  #define mmCRTC1_CRTC_GSL_VSYNC_GAP                                              0x1d79
829  #define mmCRTC2_CRTC_GSL_VSYNC_GAP                                              0x1f79
830  #define mmCRTC3_CRTC_GSL_VSYNC_GAP                                              0x4179
831  #define mmCRTC4_CRTC_GSL_VSYNC_GAP                                              0x4379
832  #define mmCRTC5_CRTC_GSL_VSYNC_GAP                                              0x4579
833  #define mmCRTC_GSL_WINDOW                                                       0x1b7a
834  #define mmCRTC0_CRTC_GSL_WINDOW                                                 0x1b7a
835  #define mmCRTC1_CRTC_GSL_WINDOW                                                 0x1d7a
836  #define mmCRTC2_CRTC_GSL_WINDOW                                                 0x1f7a
837  #define mmCRTC3_CRTC_GSL_WINDOW                                                 0x417a
838  #define mmCRTC4_CRTC_GSL_WINDOW                                                 0x437a
839  #define mmCRTC5_CRTC_GSL_WINDOW                                                 0x457a
840  #define mmCRTC_GSL_CONTROL                                                      0x1b7b
841  #define mmCRTC0_CRTC_GSL_CONTROL                                                0x1b7b
842  #define mmCRTC1_CRTC_GSL_CONTROL                                                0x1d7b
843  #define mmCRTC2_CRTC_GSL_CONTROL                                                0x1f7b
844  #define mmCRTC3_CRTC_GSL_CONTROL                                                0x417b
845  #define mmCRTC4_CRTC_GSL_CONTROL                                                0x437b
846  #define mmCRTC5_CRTC_GSL_CONTROL                                                0x457b
847  #define mmCRTC_TEST_DEBUG_INDEX                                                 0x1bc6
848  #define mmCRTC0_CRTC_TEST_DEBUG_INDEX                                           0x1bc6
849  #define mmCRTC1_CRTC_TEST_DEBUG_INDEX                                           0x1dc6
850  #define mmCRTC2_CRTC_TEST_DEBUG_INDEX                                           0x1fc6
851  #define mmCRTC3_CRTC_TEST_DEBUG_INDEX                                           0x41c6
852  #define mmCRTC4_CRTC_TEST_DEBUG_INDEX                                           0x43c6
853  #define mmCRTC5_CRTC_TEST_DEBUG_INDEX                                           0x45c6
854  #define mmCRTC_TEST_DEBUG_DATA                                                  0x1bc7
855  #define mmCRTC0_CRTC_TEST_DEBUG_DATA                                            0x1bc7
856  #define mmCRTC1_CRTC_TEST_DEBUG_DATA                                            0x1dc7
857  #define mmCRTC2_CRTC_TEST_DEBUG_DATA                                            0x1fc7
858  #define mmCRTC3_CRTC_TEST_DEBUG_DATA                                            0x41c7
859  #define mmCRTC4_CRTC_TEST_DEBUG_DATA                                            0x43c7
860  #define mmCRTC5_CRTC_TEST_DEBUG_DATA                                            0x45c7
861  #define mmDAC_ENABLE                                                            0x16aa
862  #define mmDAC_SOURCE_SELECT                                                     0x16ab
863  #define mmDAC_CRC_EN                                                            0x16ac
864  #define mmDAC_CRC_CONTROL                                                       0x16ad
865  #define mmDAC_CRC_SIG_RGB_MASK                                                  0x16ae
866  #define mmDAC_CRC_SIG_CONTROL_MASK                                              0x16af
867  #define mmDAC_CRC_SIG_RGB                                                       0x16b0
868  #define mmDAC_CRC_SIG_CONTROL                                                   0x16b1
869  #define mmDAC_SYNC_TRISTATE_CONTROL                                             0x16b2
870  #define mmDAC_STEREOSYNC_SELECT                                                 0x16b3
871  #define mmDAC_AUTODETECT_CONTROL                                                0x16b4
872  #define mmDAC_AUTODETECT_CONTROL2                                               0x16b5
873  #define mmDAC_AUTODETECT_CONTROL3                                               0x16b6
874  #define mmDAC_AUTODETECT_STATUS                                                 0x16b7
875  #define mmDAC_AUTODETECT_INT_CONTROL                                            0x16b8
876  #define mmDAC_FORCE_OUTPUT_CNTL                                                 0x16b9
877  #define mmDAC_FORCE_DATA                                                        0x16ba
878  #define mmDAC_POWERDOWN                                                         0x16bb
879  #define mmDAC_CONTROL                                                           0x16bc
880  #define mmDAC_COMPARATOR_ENABLE                                                 0x16bd
881  #define mmDAC_COMPARATOR_OUTPUT                                                 0x16be
882  #define mmDAC_PWR_CNTL                                                          0x16bf
883  #define mmDAC_DFT_CONFIG                                                        0x16c0
884  #define mmDAC_FIFO_STATUS                                                       0x16c1
885  #define mmDAC_TEST_DEBUG_INDEX                                                  0x16c2
886  #define mmDAC_TEST_DEBUG_DATA                                                   0x16c3
887  #define mmPERFCOUNTER_CNTL                                                      0x170
888  #define mmDC_PERFMON0_PERFCOUNTER_CNTL                                          0x170
889  #define mmDC_PERFMON1_PERFCOUNTER_CNTL                                          0x358
890  #define mmDC_PERFMON2_PERFCOUNTER_CNTL                                          0x364
891  #define mmDC_PERFMON3_PERFCOUNTER_CNTL                                          0x18c8
892  #define mmDC_PERFMON4_PERFCOUNTER_CNTL                                          0x1b24
893  #define mmDC_PERFMON5_PERFCOUNTER_CNTL                                          0x1d24
894  #define mmDC_PERFMON6_PERFCOUNTER_CNTL                                          0x1f24
895  #define mmDC_PERFMON7_PERFCOUNTER_CNTL                                          0x4124
896  #define mmDC_PERFMON8_PERFCOUNTER_CNTL                                          0x4324
897  #define mmDC_PERFMON9_PERFCOUNTER_CNTL                                          0x4524
898  #define mmDC_PERFMON10_PERFCOUNTER_CNTL                                         0x4724
899  #define mmDC_PERFMON11_PERFCOUNTER_CNTL                                         0x59a0
900  #define mmDC_PERFMON12_PERFCOUNTER_CNTL                                         0x5f68
901  #define mmDC_PERFMON13_PERFCOUNTER_CNTL                                         0x9924
902  #define mmPERFCOUNTER_STATE                                                     0x171
903  #define mmDC_PERFMON0_PERFCOUNTER_STATE                                         0x171
904  #define mmDC_PERFMON1_PERFCOUNTER_STATE                                         0x359
905  #define mmDC_PERFMON2_PERFCOUNTER_STATE                                         0x365
906  #define mmDC_PERFMON3_PERFCOUNTER_STATE                                         0x18c9
907  #define mmDC_PERFMON4_PERFCOUNTER_STATE                                         0x1b25
908  #define mmDC_PERFMON5_PERFCOUNTER_STATE                                         0x1d25
909  #define mmDC_PERFMON6_PERFCOUNTER_STATE                                         0x1f25
910  #define mmDC_PERFMON7_PERFCOUNTER_STATE                                         0x4125
911  #define mmDC_PERFMON8_PERFCOUNTER_STATE                                         0x4325
912  #define mmDC_PERFMON9_PERFCOUNTER_STATE                                         0x4525
913  #define mmDC_PERFMON10_PERFCOUNTER_STATE                                        0x4725
914  #define mmDC_PERFMON11_PERFCOUNTER_STATE                                        0x59a1
915  #define mmDC_PERFMON12_PERFCOUNTER_STATE                                        0x5f69
916  #define mmDC_PERFMON13_PERFCOUNTER_STATE                                        0x9925
917  #define mmPERFMON_CNTL                                                          0x173
918  #define mmDC_PERFMON0_PERFMON_CNTL                                              0x173
919  #define mmDC_PERFMON1_PERFMON_CNTL                                              0x35b
920  #define mmDC_PERFMON2_PERFMON_CNTL                                              0x367
921  #define mmDC_PERFMON3_PERFMON_CNTL                                              0x18cb
922  #define mmDC_PERFMON4_PERFMON_CNTL                                              0x1b27
923  #define mmDC_PERFMON5_PERFMON_CNTL                                              0x1d27
924  #define mmDC_PERFMON6_PERFMON_CNTL                                              0x1f27
925  #define mmDC_PERFMON7_PERFMON_CNTL                                              0x4127
926  #define mmDC_PERFMON8_PERFMON_CNTL                                              0x4327
927  #define mmDC_PERFMON9_PERFMON_CNTL                                              0x4527
928  #define mmDC_PERFMON10_PERFMON_CNTL                                             0x4727
929  #define mmDC_PERFMON11_PERFMON_CNTL                                             0x59a3
930  #define mmDC_PERFMON12_PERFMON_CNTL                                             0x5f6b
931  #define mmDC_PERFMON13_PERFMON_CNTL                                             0x9927
932  #define mmPERFMON_CNTL2                                                         0x17a
933  #define mmDC_PERFMON0_PERFMON_CNTL2                                             0x17a
934  #define mmDC_PERFMON1_PERFMON_CNTL2                                             0x362
935  #define mmDC_PERFMON2_PERFMON_CNTL2                                             0x36e
936  #define mmDC_PERFMON3_PERFMON_CNTL2                                             0x18d2
937  #define mmDC_PERFMON4_PERFMON_CNTL2                                             0x1b2e
938  #define mmDC_PERFMON5_PERFMON_CNTL2                                             0x1d2e
939  #define mmDC_PERFMON6_PERFMON_CNTL2                                             0x1f2e
940  #define mmDC_PERFMON7_PERFMON_CNTL2                                             0x412e
941  #define mmDC_PERFMON8_PERFMON_CNTL2                                             0x432e
942  #define mmDC_PERFMON9_PERFMON_CNTL2                                             0x452e
943  #define mmDC_PERFMON10_PERFMON_CNTL2                                            0x472e
944  #define mmDC_PERFMON11_PERFMON_CNTL2                                            0x59aa
945  #define mmDC_PERFMON12_PERFMON_CNTL2                                            0x5f72
946  #define mmDC_PERFMON13_PERFMON_CNTL2                                            0x992e
947  #define mmPERFMON_CVALUE_INT_MISC                                               0x172
948  #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                   0x172
949  #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                   0x35a
950  #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                   0x366
951  #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                   0x18ca
952  #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                   0x1b26
953  #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                   0x1d26
954  #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                   0x1f26
955  #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                   0x4126
956  #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                   0x4326
957  #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                   0x4526
958  #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                  0x4726
959  #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                  0x59a2
960  #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                  0x5f6a
961  #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                  0x9926
962  #define mmPERFMON_CVALUE_LOW                                                    0x174
963  #define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                        0x174
964  #define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                        0x35c
965  #define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                        0x368
966  #define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                        0x18cc
967  #define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                        0x1b28
968  #define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                        0x1d28
969  #define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                        0x1f28
970  #define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                        0x4128
971  #define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                        0x4328
972  #define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                        0x4528
973  #define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                       0x4728
974  #define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                       0x59a4
975  #define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                       0x5f6c
976  #define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                       0x9928
977  #define mmPERFMON_HI                                                            0x175
978  #define mmDC_PERFMON0_PERFMON_HI                                                0x175
979  #define mmDC_PERFMON1_PERFMON_HI                                                0x35d
980  #define mmDC_PERFMON2_PERFMON_HI                                                0x369
981  #define mmDC_PERFMON3_PERFMON_HI                                                0x18cd
982  #define mmDC_PERFMON4_PERFMON_HI                                                0x1b29
983  #define mmDC_PERFMON5_PERFMON_HI                                                0x1d29
984  #define mmDC_PERFMON6_PERFMON_HI                                                0x1f29
985  #define mmDC_PERFMON7_PERFMON_HI                                                0x4129
986  #define mmDC_PERFMON8_PERFMON_HI                                                0x4329
987  #define mmDC_PERFMON9_PERFMON_HI                                                0x4529
988  #define mmDC_PERFMON10_PERFMON_HI                                               0x4729
989  #define mmDC_PERFMON11_PERFMON_HI                                               0x59a5
990  #define mmDC_PERFMON12_PERFMON_HI                                               0x5f6d
991  #define mmDC_PERFMON13_PERFMON_HI                                               0x9929
992  #define mmPERFMON_LOW                                                           0x176
993  #define mmDC_PERFMON0_PERFMON_LOW                                               0x176
994  #define mmDC_PERFMON1_PERFMON_LOW                                               0x35e
995  #define mmDC_PERFMON2_PERFMON_LOW                                               0x36a
996  #define mmDC_PERFMON3_PERFMON_LOW                                               0x18ce
997  #define mmDC_PERFMON4_PERFMON_LOW                                               0x1b2a
998  #define mmDC_PERFMON5_PERFMON_LOW                                               0x1d2a
999  #define mmDC_PERFMON6_PERFMON_LOW                                               0x1f2a
1000  #define mmDC_PERFMON7_PERFMON_LOW                                               0x412a
1001  #define mmDC_PERFMON8_PERFMON_LOW                                               0x432a
1002  #define mmDC_PERFMON9_PERFMON_LOW                                               0x452a
1003  #define mmDC_PERFMON10_PERFMON_LOW                                              0x472a
1004  #define mmDC_PERFMON11_PERFMON_LOW                                              0x59a6
1005  #define mmDC_PERFMON12_PERFMON_LOW                                              0x5f6e
1006  #define mmDC_PERFMON13_PERFMON_LOW                                              0x992a
1007  #define mmPERFMON_TEST_DEBUG_INDEX                                              0x177
1008  #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX                                  0x177
1009  #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX                                  0x35f
1010  #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX                                  0x36b
1011  #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX                                  0x18cf
1012  #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX                                  0x1b2b
1013  #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX                                  0x1d2b
1014  #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX                                  0x1f2b
1015  #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX                                  0x412b
1016  #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX                                  0x432b
1017  #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX                                  0x452b
1018  #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX                                 0x472b
1019  #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX                                 0x59a7
1020  #define mmDC_PERFMON12_PERFMON_TEST_DEBUG_INDEX                                 0x5f6f
1021  #define mmDC_PERFMON13_PERFMON_TEST_DEBUG_INDEX                                 0x992b
1022  #define mmPERFMON_TEST_DEBUG_DATA                                               0x178
1023  #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA                                   0x178
1024  #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA                                   0x360
1025  #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA                                   0x36c
1026  #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA                                   0x18d0
1027  #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA                                   0x1b2c
1028  #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA                                   0x1d2c
1029  #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA                                   0x1f2c
1030  #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA                                   0x412c
1031  #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA                                   0x432c
1032  #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA                                   0x452c
1033  #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA                                  0x472c
1034  #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA                                  0x59a8
1035  #define mmDC_PERFMON12_PERFMON_TEST_DEBUG_DATA                                  0x5f70
1036  #define mmDC_PERFMON13_PERFMON_TEST_DEBUG_DATA                                  0x992c
1037  #define mmREFCLK_CNTL                                                           0x109
1038  #define mmDCCG_CBUS_ANTIGLITCH_RESETB                                           0x15c
1039  #define mmDCCG_CBUS_SPARE                                                       0x15d
1040  #define mmDCCG_CBUS_WRCMD_DELAY                                                 0x110
1041  #define mmDPREFCLK_CNTL                                                         0x118
1042  #define mmDCE_VERSION                                                           0x11e
1043  #define mmAVSYNC_COUNTER_WRITE                                                  0x12a
1044  #define mmAVSYNC_COUNTER_CONTROL                                                0x12b
1045  #define mmAVSYNC_COUNTER_READ                                                   0x12f
1046  #define mmDCCG_GTC_CNTL                                                         0x120
1047  #define mmDCCG_GTC_DTO_INCR                                                     0x121
1048  #define mmDCCG_GTC_DTO_MODULO                                                   0x122
1049  #define mmDCCG_GTC_CURRENT                                                      0x123
1050  #define mmDCCG_DS_DTO_INCR                                                      0x113
1051  #define mmDCCG_DS_DTO_MODULO                                                    0x114
1052  #define mmDCCG_DS_CNTL                                                          0x115
1053  #define mmDCCG_DS_HW_CAL_INTERVAL                                               0x116
1054  #define mmDCCG_DS_DEBUG_CNTL                                                    0x112
1055  #define mmDMCU_SMU_INTERRUPT_CNTL                                               0x12c
1056  #define mmSMU_CONTROL                                                           0x12d
1057  #define mmSMU_INTERRUPT_CONTROL                                                 0x12e
1058  #define mmDAC_CLK_ENABLE                                                        0x128
1059  #define mmDVO_CLK_ENABLE                                                        0x129
1060  #define mmDCCG_GATE_DISABLE_CNTL                                                0x134
1061  #define mmDCCG_GATE_DISABLE_CNTL2                                               0x13c
1062  #define mmDISPCLK_CGTT_BLK_CTRL_REG                                             0x135
1063  #define mmSCLK_CGTT_BLK_CTRL_REG                                                0x136
1064  #define mmDPREFCLK_CGTT_BLK_CTRL_REG                                            0x108
1065  #define mmREFCLK_CGTT_BLK_CTRL_REG                                              0x10b
1066  #define mmSYMCLK_CGTT_BLK_CTRL_REG                                              0x13d
1067  #define mmDCCG_CAC_STATUS                                                       0x137
1068  #define mmPIXCLK0_RESYNC_CNTL                                                   0x13a
1069  #define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                            0x100
1070  #define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                            0x101
1071  #define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                            0x102
1072  #define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                            0x103
1073  #define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                            0x10c
1074  #define mmPHYPLLF_PIXCLK_RESYNC_CNTL                                            0x13e
1075  #define mmMICROSECOND_TIME_BASE_DIV                                             0x13b
1076  #define mmDCCG_DISP_CNTL_REG                                                    0x13f
1077  #define mmMILLISECOND_TIME_BASE_DIV                                             0x130
1078  #define mmDISPCLK_FREQ_CHANGE_CNTL                                              0x131
1079  #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                            0x132
1080  #define mmDCCG_PERFMON_CNTL                                                     0x133
1081  #define mmDCCG_PERFMON_CNTL2                                                    0x10e
1082  #define mmCRTC0_PIXEL_RATE_CNTL                                                 0x140
1083  #define mmDP_DTO0_PHASE                                                         0x141
1084  #define mmDP_DTO0_MODULO                                                        0x142
1085  #define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL                                          0x143
1086  #define mmCRTC1_PIXEL_RATE_CNTL                                                 0x144
1087  #define mmDP_DTO1_PHASE                                                         0x145
1088  #define mmDP_DTO1_MODULO                                                        0x146
1089  #define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL                                          0x147
1090  #define mmCRTC2_PIXEL_RATE_CNTL                                                 0x148
1091  #define mmDP_DTO2_PHASE                                                         0x149
1092  #define mmDP_DTO2_MODULO                                                        0x14a
1093  #define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL                                          0x14b
1094  #define mmCRTC3_PIXEL_RATE_CNTL                                                 0x14c
1095  #define mmDP_DTO3_PHASE                                                         0x14d
1096  #define mmDP_DTO3_MODULO                                                        0x14e
1097  #define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL                                          0x14f
1098  #define mmCRTC4_PIXEL_RATE_CNTL                                                 0x150
1099  #define mmDP_DTO4_PHASE                                                         0x151
1100  #define mmDP_DTO4_MODULO                                                        0x152
1101  #define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL                                          0x153
1102  #define mmCRTC5_PIXEL_RATE_CNTL                                                 0x154
1103  #define mmDP_DTO5_PHASE                                                         0x155
1104  #define mmDP_DTO5_MODULO                                                        0x156
1105  #define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL                                          0x157
1106  #define mmDCCG_SOFT_RESET                                                       0x15f
1107  #define mmSYMCLKA_CLOCK_ENABLE                                                  0x160
1108  #define mmSYMCLKB_CLOCK_ENABLE                                                  0x161
1109  #define mmSYMCLKC_CLOCK_ENABLE                                                  0x162
1110  #define mmSYMCLKD_CLOCK_ENABLE                                                  0x163
1111  #define mmSYMCLKE_CLOCK_ENABLE                                                  0x164
1112  #define mmSYMCLKF_CLOCK_ENABLE                                                  0x165
1113  #define mmDPDBG_CLK_FORCE_CONTROL                                               0x10d
1114  #define mmDCCG_AUDIO_DTO_SOURCE                                                 0x16b
1115  #define mmDCCG_AUDIO_DTO0_PHASE                                                 0x16c
1116  #define mmDCCG_AUDIO_DTO0_MODULE                                                0x16d
1117  #define mmDCCG_AUDIO_DTO1_PHASE                                                 0x16e
1118  #define mmDCCG_AUDIO_DTO1_MODULE                                                0x16f
1119  #define mmDCCG_TEST_DEBUG_INDEX                                                 0x17c
1120  #define mmDCCG_TEST_DEBUG_DATA                                                  0x17d
1121  #define mmDCCG_TEST_CLK_SEL                                                     0x17e
1122  #define mmCPLL_MACRO_CNTL_RESERVED0                                             0x5fd0
1123  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0                                  0x5fd0
1124  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0                                  0x5fdc
1125  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0                                  0x5fe8
1126  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0                                  0x5ff4
1127  #define mmCPLL_MACRO_CNTL_RESERVED1                                             0x5fd1
1128  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1                                  0x5fd1
1129  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1                                  0x5fdd
1130  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1                                  0x5fe9
1131  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1                                  0x5ff5
1132  #define mmCPLL_MACRO_CNTL_RESERVED2                                             0x5fd2
1133  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2                                  0x5fd2
1134  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2                                  0x5fde
1135  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2                                  0x5fea
1136  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2                                  0x5ff6
1137  #define mmCPLL_MACRO_CNTL_RESERVED3                                             0x5fd3
1138  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3                                  0x5fd3
1139  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3                                  0x5fdf
1140  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3                                  0x5feb
1141  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3                                  0x5ff7
1142  #define mmCPLL_MACRO_CNTL_RESERVED4                                             0x5fd4
1143  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4                                  0x5fd4
1144  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4                                  0x5fe0
1145  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4                                  0x5fec
1146  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4                                  0x5ff8
1147  #define mmCPLL_MACRO_CNTL_RESERVED5                                             0x5fd5
1148  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5                                  0x5fd5
1149  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5                                  0x5fe1
1150  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5                                  0x5fed
1151  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5                                  0x5ff9
1152  #define mmCPLL_MACRO_CNTL_RESERVED6                                             0x5fd6
1153  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6                                  0x5fd6
1154  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6                                  0x5fe2
1155  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6                                  0x5fee
1156  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6                                  0x5ffa
1157  #define mmCPLL_MACRO_CNTL_RESERVED7                                             0x5fd7
1158  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7                                  0x5fd7
1159  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7                                  0x5fe3
1160  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7                                  0x5fef
1161  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7                                  0x5ffb
1162  #define mmCPLL_MACRO_CNTL_RESERVED8                                             0x5fd8
1163  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8                                  0x5fd8
1164  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8                                  0x5fe4
1165  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8                                  0x5ff0
1166  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8                                  0x5ffc
1167  #define mmCPLL_MACRO_CNTL_RESERVED9                                             0x5fd9
1168  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9                                  0x5fd9
1169  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9                                  0x5fe5
1170  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9                                  0x5ff1
1171  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9                                  0x5ffd
1172  #define mmCPLL_MACRO_CNTL_RESERVED10                                            0x5fda
1173  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10                                 0x5fda
1174  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10                                 0x5fe6
1175  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10                                 0x5ff2
1176  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10                                 0x5ffe
1177  #define mmCPLL_MACRO_CNTL_RESERVED11                                            0x5fdb
1178  #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11                                 0x5fdb
1179  #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11                                 0x5fe7
1180  #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11                                 0x5ff3
1181  #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11                                 0x5fff
1182  #define mmPLL_MACRO_CNTL_RESERVED0                                              0x1700
1183  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0                                    0x1700
1184  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0                                    0x172a
1185  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0                                    0x1754
1186  #define mmPLL_MACRO_CNTL_RESERVED1                                              0x1701
1187  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1                                    0x1701
1188  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1                                    0x172b
1189  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1                                    0x1755
1190  #define mmPLL_MACRO_CNTL_RESERVED2                                              0x1702
1191  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2                                    0x1702
1192  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2                                    0x172c
1193  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2                                    0x1756
1194  #define mmPLL_MACRO_CNTL_RESERVED3                                              0x1703
1195  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3                                    0x1703
1196  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3                                    0x172d
1197  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3                                    0x1757
1198  #define mmPLL_MACRO_CNTL_RESERVED4                                              0x1704
1199  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4                                    0x1704
1200  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4                                    0x172e
1201  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4                                    0x1758
1202  #define mmPLL_MACRO_CNTL_RESERVED5                                              0x1705
1203  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5                                    0x1705
1204  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5                                    0x172f
1205  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5                                    0x1759
1206  #define mmPLL_MACRO_CNTL_RESERVED6                                              0x1706
1207  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6                                    0x1706
1208  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6                                    0x1730
1209  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6                                    0x175a
1210  #define mmPLL_MACRO_CNTL_RESERVED7                                              0x1707
1211  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7                                    0x1707
1212  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7                                    0x1731
1213  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7                                    0x175b
1214  #define mmPLL_MACRO_CNTL_RESERVED8                                              0x1708
1215  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8                                    0x1708
1216  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8                                    0x1732
1217  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8                                    0x175c
1218  #define mmPLL_MACRO_CNTL_RESERVED9                                              0x1709
1219  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9                                    0x1709
1220  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9                                    0x1733
1221  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9                                    0x175d
1222  #define mmPLL_MACRO_CNTL_RESERVED10                                             0x170a
1223  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10                                   0x170a
1224  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10                                   0x1734
1225  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10                                   0x175e
1226  #define mmPLL_MACRO_CNTL_RESERVED11                                             0x170b
1227  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11                                   0x170b
1228  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11                                   0x1735
1229  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11                                   0x175f
1230  #define mmPLL_MACRO_CNTL_RESERVED12                                             0x170c
1231  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12                                   0x170c
1232  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12                                   0x1736
1233  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12                                   0x1760
1234  #define mmPLL_MACRO_CNTL_RESERVED13                                             0x170d
1235  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13                                   0x170d
1236  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13                                   0x1737
1237  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13                                   0x1761
1238  #define mmPLL_MACRO_CNTL_RESERVED14                                             0x170e
1239  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14                                   0x170e
1240  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14                                   0x1738
1241  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14                                   0x1762
1242  #define mmPLL_MACRO_CNTL_RESERVED15                                             0x170f
1243  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15                                   0x170f
1244  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15                                   0x1739
1245  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15                                   0x1763
1246  #define mmPLL_MACRO_CNTL_RESERVED16                                             0x1710
1247  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16                                   0x1710
1248  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16                                   0x173a
1249  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16                                   0x1764
1250  #define mmPLL_MACRO_CNTL_RESERVED17                                             0x1711
1251  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17                                   0x1711
1252  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17                                   0x173b
1253  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17                                   0x1765
1254  #define mmPLL_MACRO_CNTL_RESERVED18                                             0x1712
1255  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18                                   0x1712
1256  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18                                   0x173c
1257  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18                                   0x1766
1258  #define mmPLL_MACRO_CNTL_RESERVED19                                             0x1713
1259  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19                                   0x1713
1260  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19                                   0x173d
1261  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19                                   0x1767
1262  #define mmPLL_MACRO_CNTL_RESERVED20                                             0x1714
1263  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20                                   0x1714
1264  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20                                   0x173e
1265  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20                                   0x1768
1266  #define mmPLL_MACRO_CNTL_RESERVED21                                             0x1715
1267  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21                                   0x1715
1268  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21                                   0x173f
1269  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21                                   0x1769
1270  #define mmPLL_MACRO_CNTL_RESERVED22                                             0x1716
1271  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22                                   0x1716
1272  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22                                   0x1740
1273  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22                                   0x176a
1274  #define mmPLL_MACRO_CNTL_RESERVED23                                             0x1717
1275  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23                                   0x1717
1276  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23                                   0x1741
1277  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23                                   0x176b
1278  #define mmPLL_MACRO_CNTL_RESERVED24                                             0x1718
1279  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24                                   0x1718
1280  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24                                   0x1742
1281  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24                                   0x176c
1282  #define mmPLL_MACRO_CNTL_RESERVED25                                             0x1719
1283  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25                                   0x1719
1284  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25                                   0x1743
1285  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25                                   0x176d
1286  #define mmPLL_MACRO_CNTL_RESERVED26                                             0x171a
1287  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26                                   0x171a
1288  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26                                   0x1744
1289  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26                                   0x176e
1290  #define mmPLL_MACRO_CNTL_RESERVED27                                             0x171b
1291  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27                                   0x171b
1292  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27                                   0x1745
1293  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27                                   0x176f
1294  #define mmPLL_MACRO_CNTL_RESERVED28                                             0x171c
1295  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28                                   0x171c
1296  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28                                   0x1746
1297  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28                                   0x1770
1298  #define mmPLL_MACRO_CNTL_RESERVED29                                             0x171d
1299  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29                                   0x171d
1300  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29                                   0x1747
1301  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29                                   0x1771
1302  #define mmPLL_MACRO_CNTL_RESERVED30                                             0x171e
1303  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30                                   0x171e
1304  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30                                   0x1748
1305  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30                                   0x1772
1306  #define mmPLL_MACRO_CNTL_RESERVED31                                             0x171f
1307  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31                                   0x171f
1308  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31                                   0x1749
1309  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31                                   0x1773
1310  #define mmPLL_MACRO_CNTL_RESERVED32                                             0x1720
1311  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32                                   0x1720
1312  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32                                   0x174a
1313  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32                                   0x1774
1314  #define mmPLL_MACRO_CNTL_RESERVED33                                             0x1721
1315  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33                                   0x1721
1316  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33                                   0x174b
1317  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33                                   0x1775
1318  #define mmPLL_MACRO_CNTL_RESERVED34                                             0x1722
1319  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34                                   0x1722
1320  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34                                   0x174c
1321  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34                                   0x1776
1322  #define mmPLL_MACRO_CNTL_RESERVED35                                             0x1723
1323  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35                                   0x1723
1324  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35                                   0x174d
1325  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35                                   0x1777
1326  #define mmPLL_MACRO_CNTL_RESERVED36                                             0x1724
1327  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36                                   0x1724
1328  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36                                   0x174e
1329  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36                                   0x1778
1330  #define mmPLL_MACRO_CNTL_RESERVED37                                             0x1725
1331  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37                                   0x1725
1332  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37                                   0x174f
1333  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37                                   0x1779
1334  #define mmPLL_MACRO_CNTL_RESERVED38                                             0x1726
1335  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38                                   0x1726
1336  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38                                   0x1750
1337  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38                                   0x177a
1338  #define mmPLL_MACRO_CNTL_RESERVED39                                             0x1727
1339  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39                                   0x1727
1340  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39                                   0x1751
1341  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39                                   0x177b
1342  #define mmPLL_MACRO_CNTL_RESERVED40                                             0x1728
1343  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40                                   0x1728
1344  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40                                   0x1752
1345  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40                                   0x177c
1346  #define mmPLL_MACRO_CNTL_RESERVED41                                             0x1729
1347  #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41                                   0x1729
1348  #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41                                   0x1753
1349  #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41                                   0x177d
1350  #define mmDENTIST_DISPCLK_CNTL                                                  0x124
1351  #define mmDCDEBUG_BUS_CLK1_SEL                                                  0x16c4
1352  #define mmDCDEBUG_BUS_CLK2_SEL                                                  0x16c5
1353  #define mmDCDEBUG_BUS_CLK3_SEL                                                  0x16c6
1354  #define mmDCDEBUG_BUS_CLK4_SEL                                                  0x16c7
1355  #define mmDCDEBUG_BUS_CLK5_SEL                                                  0x16c8
1356  #define mmDCDEBUG_OUT_PIN_OVERRIDE                                              0x16c9
1357  #define mmDCDEBUG_OUT_CNTL                                                      0x16ca
1358  #define mmDCDEBUG_OUT_DATA                                                      0x16cb
1359  #define mmDMIF_CONTROL                                                          0x2f6
1360  #define mmDMIF_STATUS                                                           0x2f7
1361  #define mmDMIFV_STATUS                                                          0x2f5
1362  #define mmDMIF_HW_DEBUG                                                         0x2f8
1363  #define mmDMIF_ARBITRATION_CONTROL                                              0x2f9
1364  #define mmPIPE0_ARBITRATION_CONTROL3                                            0x2fa
1365  #define mmPIPE1_ARBITRATION_CONTROL3                                            0x2fb
1366  #define mmPIPE2_ARBITRATION_CONTROL3                                            0x2fc
1367  #define mmPIPE3_ARBITRATION_CONTROL3                                            0x2fd
1368  #define mmPIPE4_ARBITRATION_CONTROL3                                            0x2fe
1369  #define mmPIPE5_ARBITRATION_CONTROL3                                            0x2ff
1370  #define mmPIPE6_ARBITRATION_CONTROL3                                            0x32a
1371  #define mmPIPE7_ARBITRATION_CONTROL3                                            0x32b
1372  #define mmDMIF_P_VMID                                                           0x300
1373  #define mmDMIF_URG_OVERRIDE                                                     0x329
1374  #define mmDMIF_TEST_DEBUG_INDEX                                                 0x301
1375  #define mmDMIF_TEST_DEBUG_DATA                                                  0x302
1376  #define ixDMIF_DEBUG02_CORE0                                                    0x2
1377  #define ixDMIF_DEBUG02_CORE1                                                    0xa
1378  #define mmDMIF_ADDR_CALC                                                        0x303
1379  #define mmDMIF_STATUS2                                                          0x304
1380  #define mmPIPE0_MAX_REQUESTS                                                    0x305
1381  #define mmPIPE1_MAX_REQUESTS                                                    0x306
1382  #define mmPIPE2_MAX_REQUESTS                                                    0x307
1383  #define mmPIPE3_MAX_REQUESTS                                                    0x308
1384  #define mmPIPE4_MAX_REQUESTS                                                    0x309
1385  #define mmPIPE5_MAX_REQUESTS                                                    0x30a
1386  #define mmPIPE6_MAX_REQUESTS                                                    0x32c
1387  #define mmPIPE7_MAX_REQUESTS                                                    0x32d
1388  #define mmDVMM_REG_RD_STATUS                                                    0x32e
1389  #define mmDVMM_REG_RD_DATA                                                      0x32f
1390  #define mmDVMM_PTE_REQ                                                          0x330
1391  #define mmDVMM_CNTL                                                             0x331
1392  #define mmDVMM_FAULT_STATUS                                                     0x332
1393  #define mmDVMM_FAULT_ADDR                                                       0x333
1394  #define mmLOW_POWER_TILING_CONTROL                                              0x30b
1395  #define mmMCIF_CONTROL                                                          0x30c
1396  #define mmMCIF_WRITE_COMBINE_CONTROL                                            0x30d
1397  #define mmMCIF_TEST_DEBUG_INDEX                                                 0x30e
1398  #define mmMCIF_TEST_DEBUG_DATA                                                  0x30f
1399  #define ixIDDCCIF02_DBG_DCCIF_C                                                 0x9
1400  #define ixIDDCCIF04_DBG_DCCIF_E                                                 0xb
1401  #define ixIDDCCIF05_DBG_DCCIF_F                                                 0xc
1402  #define mmMCIF_VMID                                                             0x310
1403  #define mmMCIF_MEM_CONTROL                                                      0x311
1404  #define mmCC_DC_PIPE_DIS                                                        0x312
1405  #define mmMC_DC_INTERFACE_NACK_STATUS                                           0x313
1406  #define mmRBBMIF_TIMEOUT                                                        0x314
1407  #define mmRBBMIF_STATUS                                                         0x315
1408  #define mmRBBMIF_TIMEOUT_DIS                                                    0x316
1409  #define mmRBBMIF_STATUS_FLAG                                                    0x327
1410  #define mmDCI_MEM_PWR_STATUS                                                    0x317
1411  #define mmDCI_MEM_PWR_STATUS2                                                   0x318
1412  #define mmDCI_MEM_PWR_STATUS3                                                   0x33d
1413  #define mmDCI_CLK_CNTL                                                          0x319
1414  #define mmDCI_CLK_RAMP_CNTL                                                     0x31a
1415  #define mmDCI_MEM_PWR_CNTL                                                      0x31b
1416  #define mmDCI_MEM_PWR_CNTL2                                                     0x31c
1417  #define mmDCI_MEM_PWR_CNTL3                                                     0x31d
1418  #define mmDCI_MEM_PWR_CNTL4                                                     0x33b
1419  #define mmDVMM_PTE_PGMEM_CONTROL                                                0x335
1420  #define mmDVMM_PTE_PGMEM_STATE                                                  0x336
1421  #define mmDCI_SOFT_RESET                                                        0x328
1422  #define mmDCI_MISC                                                              0x33c
1423  #define mmDCI_TEST_DEBUG_INDEX                                                  0x31e
1424  #define mmDCI_TEST_DEBUG_DATA                                                   0x31f
1425  #define mmDCI_DEBUG_CONFIG                                                      0x320
1426  #define mmPIPE0_DMIF_BUFFER_CONTROL                                             0x321
1427  #define mmPIPE1_DMIF_BUFFER_CONTROL                                             0x322
1428  #define mmPIPE2_DMIF_BUFFER_CONTROL                                             0x323
1429  #define mmPIPE3_DMIF_BUFFER_CONTROL                                             0x324
1430  #define mmPIPE4_DMIF_BUFFER_CONTROL                                             0x325
1431  #define mmPIPE5_DMIF_BUFFER_CONTROL                                             0x326
1432  #define mmDC_GENERICA                                                           0x4800
1433  #define mmDC_GENERICB                                                           0x4801
1434  #define mmDC_PAD_EXTERN_SIG                                                     0x4802
1435  #define mmDC_REF_CLK_CNTL                                                       0x4803
1436  #define mmDC_GPIO_DEBUG                                                         0x4804
1437  #define mmUNIPHYA_LINK_CNTL                                                     0x4805
1438  #define mmUNIPHYB_LINK_CNTL                                                     0x4807
1439  #define mmUNIPHYC_LINK_CNTL                                                     0x4809
1440  #define mmUNIPHYD_LINK_CNTL                                                     0x480b
1441  #define mmUNIPHYE_LINK_CNTL                                                     0x480d
1442  #define mmUNIPHYF_LINK_CNTL                                                     0x480f
1443  #define mmUNIPHYG_LINK_CNTL                                                     0x4811
1444  #define mmUNIPHYA_CHANNEL_XBAR_CNTL                                             0x4806
1445  #define mmUNIPHYB_CHANNEL_XBAR_CNTL                                             0x4808
1446  #define mmUNIPHYC_CHANNEL_XBAR_CNTL                                             0x480a
1447  #define mmUNIPHYD_CHANNEL_XBAR_CNTL                                             0x480c
1448  #define mmUNIPHYE_CHANNEL_XBAR_CNTL                                             0x480e
1449  #define mmUNIPHYF_CHANNEL_XBAR_CNTL                                             0x4810
1450  #define mmUNIPHYG_CHANNEL_XBAR_CNTL                                             0x4812
1451  #define mmUNIPHYLPA_LINK_CNTL                                                   0x4847
1452  #define mmUNIPHYLPB_LINK_CNTL                                                   0x4848
1453  #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL                                           0x4849
1454  #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL                                           0x484a
1455  #define mmUNIPHY_IMPCAL_LINKA                                                   0x4838
1456  #define mmUNIPHY_IMPCAL_LINKB                                                   0x4839
1457  #define mmUNIPHY_IMPCAL_LINKC                                                   0x483f
1458  #define mmUNIPHY_IMPCAL_LINKD                                                   0x4840
1459  #define mmUNIPHY_IMPCAL_LINKE                                                   0x4843
1460  #define mmUNIPHY_IMPCAL_LINKF                                                   0x4844
1461  #define mmUNIPHY_IMPCAL_PERIOD                                                  0x483a
1462  #define mmAUXP_IMPCAL                                                           0x483b
1463  #define mmAUXN_IMPCAL                                                           0x483c
1464  #define mmDCIO_IMPCAL_CNTL                                                      0x483d
1465  #define mmUNIPHY_IMPCAL_PSW_AB                                                  0x483e
1466  #define mmDCIO_IMPCAL_CNTL_CD                                                   0x4841
1467  #define mmUNIPHY_IMPCAL_PSW_CD                                                  0x4842
1468  #define mmDCIO_IMPCAL_CNTL_EF                                                   0x4845
1469  #define mmUNIPHY_IMPCAL_PSW_EF                                                  0x4846
1470  #define mmDCIO_WRCMD_DELAY                                                      0x4816
1471  #define mmDC_PINSTRAPS                                                          0x4818
1472  #define mmDC_DVODATA_CONFIG                                                     0x481a
1473  #define mmLVTMA_PWRSEQ_CNTL                                                     0x481b
1474  #define mmLVTMA_PWRSEQ_STATE                                                    0x481c
1475  #define mmLVTMA_PWRSEQ_REF_DIV                                                  0x481d
1476  #define mmLVTMA_PWRSEQ_DELAY1                                                   0x481e
1477  #define mmLVTMA_PWRSEQ_DELAY2                                                   0x481f
1478  #define mmBL_PWM_CNTL                                                           0x4820
1479  #define mmBL_PWM_CNTL2                                                          0x4821
1480  #define mmBL_PWM_PERIOD_CNTL                                                    0x4822
1481  #define mmBL_PWM_GRP1_REG_LOCK                                                  0x4823
1482  #define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
1483  #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                            0x4825
1484  #define mmDCIO_GSL0_CNTL                                                        0x4826
1485  #define mmDCIO_GSL1_CNTL                                                        0x4827
1486  #define mmDCIO_GSL2_CNTL                                                        0x4828
1487  #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                  0x4829
1488  #define mmDC_GPU_TIMER_START_POSITION_P_FLIP                                    0x482a
1489  #define mmDC_GPU_TIMER_READ                                                     0x482b
1490  #define mmDC_GPU_TIMER_READ_CNTL                                                0x482c
1491  #define mmDCIO_CLOCK_CNTL                                                       0x482d
1492  #define mmDCIO_DEBUG                                                            0x482f
1493  #define mmDCO_DCFE_EXT_VSYNC_CNTL                                               0x4830
1494  #define mmDBG_OUT_CNTL                                                          0x4834
1495  #define mmDCIO_DEBUG_CONFIG                                                     0x4835
1496  #define mmDCIO_SOFT_RESET                                                       0x4836
1497  #define mmDCIO_DPHY_SEL                                                         0x4837
1498  #define mmDCIO_DPCS_TX_INTERRUPT                                                0x484b
1499  #define mmDCIO_DPCS_RX_INTERRUPT                                                0x484c
1500  #define mmDCIO_SEMAPHORE0                                                       0x484d
1501  #define mmDCIO_SEMAPHORE1                                                       0x484e
1502  #define mmDCIO_SEMAPHORE2                                                       0x484f
1503  #define mmDCIO_SEMAPHORE3                                                       0x4850
1504  #define mmDCIO_SEMAPHORE4                                                       0x4851
1505  #define mmDCIO_SEMAPHORE5                                                       0x4852
1506  #define mmDCIO_SEMAPHORE6                                                       0x4853
1507  #define mmDCIO_SEMAPHORE7                                                       0x4854
1508  #define mmDCIO_TEST_DEBUG_INDEX                                                 0x4831
1509  #define mmDCIO_TEST_DEBUG_DATA                                                  0x4832
1510  #define ixDCIO_DEBUG1                                                           0x1
1511  #define ixDCIO_DEBUG2                                                           0x2
1512  #define ixDCIO_DEBUG3                                                           0x3
1513  #define ixDCIO_DEBUG4                                                           0x4
1514  #define ixDCIO_DEBUG5                                                           0x5
1515  #define ixDCIO_DEBUG6                                                           0x6
1516  #define ixDCIO_DEBUG7                                                           0x7
1517  #define ixDCIO_DEBUG8                                                           0x8
1518  #define ixDCIO_DEBUG9                                                           0x9
1519  #define ixDCIO_DEBUGA                                                           0xa
1520  #define ixDCIO_DEBUGB                                                           0xb
1521  #define ixDCIO_DEBUGC                                                           0xc
1522  #define ixDCIO_DEBUGD                                                           0xd
1523  #define ixDCIO_DEBUGE                                                           0xe
1524  #define ixDCIO_DEBUGF                                                           0xf
1525  #define ixDCIO_DEBUG10                                                          0x10
1526  #define ixDCIO_DEBUG11                                                          0x11
1527  #define ixDCIO_DEBUG12                                                          0x12
1528  #define ixDCIO_DEBUG13                                                          0x13
1529  #define ixDCIO_DEBUG14                                                          0x14
1530  #define ixDCIO_DEBUG15                                                          0x15
1531  #define ixDCIO_DEBUG16                                                          0x16
1532  #define ixDCIO_DEBUG17                                                          0x17
1533  #define ixDCIO_DEBUG18                                                          0x18
1534  #define ixDCIO_DEBUG19                                                          0x19
1535  #define ixDCIO_DEBUG1A                                                          0x1a
1536  #define ixDCIO_DEBUG1B                                                          0x1b
1537  #define ixDCIO_DEBUG1C                                                          0x1c
1538  #define ixDCIO_DEBUG1D                                                          0x1d
1539  #define ixDCIO_DEBUG1E                                                          0x1e
1540  #define ixDCIO_DEBUG1F                                                          0x1f
1541  #define ixDCIO_DEBUG20                                                          0x20
1542  #define ixDCIO_DEBUG21                                                          0x21
1543  #define ixDCIO_DEBUG22                                                          0x22
1544  #define ixDCIO_DEBUG23                                                          0x23
1545  #define ixDCIO_DEBUG24                                                          0x24
1546  #define ixDCIO_DEBUG25                                                          0x25
1547  #define ixDCIO_DEBUG26                                                          0x26
1548  #define ixDCIO_DEBUG27                                                          0x27
1549  #define ixDCIO_DEBUG28                                                          0x28
1550  #define ixDCIO_DEBUG_ID                                                         0x0
1551  #define mmDC_GPIO_GENERIC_MASK                                                  0x4860
1552  #define mmDC_GPIO_GENERIC_A                                                     0x4861
1553  #define mmDC_GPIO_GENERIC_EN                                                    0x4862
1554  #define mmDC_GPIO_GENERIC_Y                                                     0x4863
1555  #define mmDC_GPIO_DDC1_MASK                                                     0x4868
1556  #define mmDC_GPIO_DDC1_A                                                        0x4869
1557  #define mmDC_GPIO_DDC1_EN                                                       0x486a
1558  #define mmDC_GPIO_DDC1_Y                                                        0x486b
1559  #define mmDC_GPIO_DDC2_MASK                                                     0x486c
1560  #define mmDC_GPIO_DDC2_A                                                        0x486d
1561  #define mmDC_GPIO_DDC2_EN                                                       0x486e
1562  #define mmDC_GPIO_DDC2_Y                                                        0x486f
1563  #define mmDC_GPIO_DDC3_MASK                                                     0x4870
1564  #define mmDC_GPIO_DDC3_A                                                        0x4871
1565  #define mmDC_GPIO_DDC3_EN                                                       0x4872
1566  #define mmDC_GPIO_DDC3_Y                                                        0x4873
1567  #define mmDC_GPIO_DDC4_MASK                                                     0x4874
1568  #define mmDC_GPIO_DDC4_A                                                        0x4875
1569  #define mmDC_GPIO_DDC4_EN                                                       0x4876
1570  #define mmDC_GPIO_DDC4_Y                                                        0x4877
1571  #define mmDC_GPIO_DDC5_MASK                                                     0x4878
1572  #define mmDC_GPIO_DDC5_A                                                        0x4879
1573  #define mmDC_GPIO_DDC5_EN                                                       0x487a
1574  #define mmDC_GPIO_DDC5_Y                                                        0x487b
1575  #define mmDC_GPIO_DDC6_MASK                                                     0x487c
1576  #define mmDC_GPIO_DDC6_A                                                        0x487d
1577  #define mmDC_GPIO_DDC6_EN                                                       0x487e
1578  #define mmDC_GPIO_DDC6_Y                                                        0x487f
1579  #define mmDC_GPIO_DDCVGA_MASK                                                   0x4880
1580  #define mmDC_GPIO_DDCVGA_A                                                      0x4881
1581  #define mmDC_GPIO_DDCVGA_EN                                                     0x4882
1582  #define mmDC_GPIO_DDCVGA_Y                                                      0x4883
1583  #define mmDC_GPIO_SYNCA_MASK                                                    0x4884
1584  #define mmDC_GPIO_SYNCA_A                                                       0x4885
1585  #define mmDC_GPIO_SYNCA_EN                                                      0x4886
1586  #define mmDC_GPIO_SYNCA_Y                                                       0x4887
1587  #define mmDC_GPIO_GENLK_MASK                                                    0x4888
1588  #define mmDC_GPIO_GENLK_A                                                       0x4889
1589  #define mmDC_GPIO_GENLK_EN                                                      0x488a
1590  #define mmDC_GPIO_GENLK_Y                                                       0x488b
1591  #define mmDC_GPIO_HPD_MASK                                                      0x488c
1592  #define mmDC_GPIO_HPD_A                                                         0x488d
1593  #define mmDC_GPIO_HPD_EN                                                        0x488e
1594  #define mmDC_GPIO_HPD_Y                                                         0x488f
1595  #define mmDC_GPIO_PWRSEQ_MASK                                                   0x4890
1596  #define mmDC_GPIO_PWRSEQ_A                                                      0x4891
1597  #define mmDC_GPIO_PWRSEQ_EN                                                     0x4892
1598  #define mmDC_GPIO_PWRSEQ_Y                                                      0x4893
1599  #define mmDC_GPIO_PAD_STRENGTH_1                                                0x4894
1600  #define mmDC_GPIO_PAD_STRENGTH_2                                                0x4895
1601  #define mmPHY_AUX_CNTL                                                          0x4897
1602  #define mmDC_GPIO_I2CPAD_A                                                      0x4899
1603  #define mmDC_GPIO_I2CPAD_EN                                                     0x489a
1604  #define mmDC_GPIO_I2CPAD_Y                                                      0x489b
1605  #define mmDC_GPIO_I2CPAD_STRENGTH                                               0x489c
1606  #define mmDVO_VREF_CONTROL                                                      0x489e
1607  #define mmDVO_SKEW_ADJUST                                                       0x489f
1608  #define mmDC_GPIO_RECEIVER_EN0                                                  0x48a0
1609  #define mmDC_GPIO_RECEIVER_EN1                                                  0x48a1
1610  #define mmDC_GPIO_I2S_SPDIF_MASK                                                0x48a8
1611  #define mmDC_GPIO_I2S_SPDIF_A                                                   0x48a9
1612  #define mmDC_GPIO_I2S_SPDIF_EN                                                  0x48aa
1613  #define mmDC_GPIO_I2S_SPDIF_Y                                                   0x48ab
1614  #define mmDC_GPIO_I2S_SPDIF_STRENGTH                                            0x48ac
1615  #define mmDC_GPIO_TX12_EN                                                       0x48ad
1616  #define mmDC_GPIO_AUX_CTRL_0                                                    0x48ae
1617  #define mmDC_GPIO_AUX_CTRL_1                                                    0x48af
1618  #define mmDC_GPIO_AUX_CTRL_2                                                    0x48b0
1619  #define mmDC_GPIO_HPD_CTRL_0                                                    0x48b1
1620  #define mmDC_GPIO_HPD_CTRL_1                                                    0x48b2
1621  #define mmDAC_MACRO_CNTL_RESERVED0                                              0x48b8
1622  #define mmDAC_MACRO_CNTL_RESERVED1                                              0x48b9
1623  #define mmDAC_MACRO_CNTL_RESERVED2                                              0x48ba
1624  #define mmDAC_MACRO_CNTL_RESERVED3                                              0x48bb
1625  #define mmUNIPHY_MACRO_CNTL_RESERVED0                                           0x48c0
1626  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                              0x48c0
1627  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                              0x4960
1628  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                              0x9a00
1629  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                              0x9aa0
1630  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                              0x9b40
1631  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0                              0x9be0
1632  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0                              0x9c80
1633  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0                              0x9d20
1634  #define mmUNIPHY_MACRO_CNTL_RESERVED1                                           0x48c1
1635  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                              0x48c1
1636  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                              0x4961
1637  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                              0x9a01
1638  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                              0x9aa1
1639  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                              0x9b41
1640  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1                              0x9be1
1641  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1                              0x9c81
1642  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1                              0x9d21
1643  #define mmUNIPHY_MACRO_CNTL_RESERVED2                                           0x48c2
1644  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                              0x48c2
1645  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                              0x4962
1646  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                              0x9a02
1647  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                              0x9aa2
1648  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                              0x9b42
1649  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2                              0x9be2
1650  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2                              0x9c82
1651  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2                              0x9d22
1652  #define mmUNIPHY_MACRO_CNTL_RESERVED3                                           0x48c3
1653  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                              0x48c3
1654  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                              0x4963
1655  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                              0x9a03
1656  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                              0x9aa3
1657  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                              0x9b43
1658  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3                              0x9be3
1659  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3                              0x9c83
1660  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3                              0x9d23
1661  #define mmUNIPHY_MACRO_CNTL_RESERVED4                                           0x48c4
1662  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                              0x48c4
1663  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                              0x4964
1664  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                              0x9a04
1665  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                              0x9aa4
1666  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                              0x9b44
1667  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4                              0x9be4
1668  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4                              0x9c84
1669  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4                              0x9d24
1670  #define mmUNIPHY_MACRO_CNTL_RESERVED5                                           0x48c5
1671  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                              0x48c5
1672  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                              0x4965
1673  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                              0x9a05
1674  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                              0x9aa5
1675  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                              0x9b45
1676  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5                              0x9be5
1677  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5                              0x9c85
1678  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5                              0x9d25
1679  #define mmUNIPHY_MACRO_CNTL_RESERVED6                                           0x48c6
1680  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                              0x48c6
1681  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                              0x4966
1682  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                              0x9a06
1683  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                              0x9aa6
1684  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                              0x9b46
1685  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6                              0x9be6
1686  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6                              0x9c86
1687  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6                              0x9d26
1688  #define mmUNIPHY_MACRO_CNTL_RESERVED7                                           0x48c7
1689  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                              0x48c7
1690  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                              0x4967
1691  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                              0x9a07
1692  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                              0x9aa7
1693  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                              0x9b47
1694  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7                              0x9be7
1695  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7                              0x9c87
1696  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7                              0x9d27
1697  #define mmUNIPHY_MACRO_CNTL_RESERVED8                                           0x48c8
1698  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                              0x48c8
1699  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                              0x4968
1700  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                              0x9a08
1701  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                              0x9aa8
1702  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                              0x9b48
1703  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8                              0x9be8
1704  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8                              0x9c88
1705  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8                              0x9d28
1706  #define mmUNIPHY_MACRO_CNTL_RESERVED9                                           0x48c9
1707  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                              0x48c9
1708  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                              0x4969
1709  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                              0x9a09
1710  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                              0x9aa9
1711  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                              0x9b49
1712  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9                              0x9be9
1713  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9                              0x9c89
1714  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9                              0x9d29
1715  #define mmUNIPHY_MACRO_CNTL_RESERVED10                                          0x48ca
1716  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                             0x48ca
1717  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                             0x496a
1718  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                             0x9a0a
1719  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                             0x9aaa
1720  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                             0x9b4a
1721  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10                             0x9bea
1722  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10                             0x9c8a
1723  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10                             0x9d2a
1724  #define mmUNIPHY_MACRO_CNTL_RESERVED11                                          0x48cb
1725  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                             0x48cb
1726  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                             0x496b
1727  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                             0x9a0b
1728  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                             0x9aab
1729  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                             0x9b4b
1730  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11                             0x9beb
1731  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11                             0x9c8b
1732  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11                             0x9d2b
1733  #define mmUNIPHY_MACRO_CNTL_RESERVED12                                          0x48cc
1734  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                             0x48cc
1735  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                             0x496c
1736  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                             0x9a0c
1737  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                             0x9aac
1738  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                             0x9b4c
1739  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12                             0x9bec
1740  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12                             0x9c8c
1741  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12                             0x9d2c
1742  #define mmUNIPHY_MACRO_CNTL_RESERVED13                                          0x48cd
1743  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                             0x48cd
1744  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                             0x496d
1745  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                             0x9a0d
1746  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                             0x9aad
1747  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                             0x9b4d
1748  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13                             0x9bed
1749  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13                             0x9c8d
1750  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13                             0x9d2d
1751  #define mmUNIPHY_MACRO_CNTL_RESERVED14                                          0x48ce
1752  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                             0x48ce
1753  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                             0x496e
1754  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                             0x9a0e
1755  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                             0x9aae
1756  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                             0x9b4e
1757  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14                             0x9bee
1758  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14                             0x9c8e
1759  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14                             0x9d2e
1760  #define mmUNIPHY_MACRO_CNTL_RESERVED15                                          0x48cf
1761  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                             0x48cf
1762  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                             0x496f
1763  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                             0x9a0f
1764  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                             0x9aaf
1765  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                             0x9b4f
1766  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15                             0x9bef
1767  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15                             0x9c8f
1768  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15                             0x9d2f
1769  #define mmUNIPHY_MACRO_CNTL_RESERVED16                                          0x48d0
1770  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                             0x48d0
1771  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                             0x4970
1772  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                             0x9a10
1773  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                             0x9ab0
1774  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                             0x9b50
1775  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16                             0x9bf0
1776  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16                             0x9c90
1777  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16                             0x9d30
1778  #define mmUNIPHY_MACRO_CNTL_RESERVED17                                          0x48d1
1779  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                             0x48d1
1780  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                             0x4971
1781  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                             0x9a11
1782  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                             0x9ab1
1783  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                             0x9b51
1784  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17                             0x9bf1
1785  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17                             0x9c91
1786  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17                             0x9d31
1787  #define mmUNIPHY_MACRO_CNTL_RESERVED18                                          0x48d2
1788  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                             0x48d2
1789  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                             0x4972
1790  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                             0x9a12
1791  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                             0x9ab2
1792  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                             0x9b52
1793  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18                             0x9bf2
1794  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18                             0x9c92
1795  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18                             0x9d32
1796  #define mmUNIPHY_MACRO_CNTL_RESERVED19                                          0x48d3
1797  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                             0x48d3
1798  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                             0x4973
1799  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                             0x9a13
1800  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                             0x9ab3
1801  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                             0x9b53
1802  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19                             0x9bf3
1803  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19                             0x9c93
1804  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19                             0x9d33
1805  #define mmUNIPHY_MACRO_CNTL_RESERVED20                                          0x48d4
1806  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                             0x48d4
1807  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                             0x4974
1808  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                             0x9a14
1809  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                             0x9ab4
1810  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                             0x9b54
1811  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20                             0x9bf4
1812  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20                             0x9c94
1813  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20                             0x9d34
1814  #define mmUNIPHY_MACRO_CNTL_RESERVED21                                          0x48d5
1815  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                             0x48d5
1816  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                             0x4975
1817  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                             0x9a15
1818  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                             0x9ab5
1819  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                             0x9b55
1820  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21                             0x9bf5
1821  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21                             0x9c95
1822  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21                             0x9d35
1823  #define mmUNIPHY_MACRO_CNTL_RESERVED22                                          0x48d6
1824  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                             0x48d6
1825  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                             0x4976
1826  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                             0x9a16
1827  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                             0x9ab6
1828  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                             0x9b56
1829  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22                             0x9bf6
1830  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22                             0x9c96
1831  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22                             0x9d36
1832  #define mmUNIPHY_MACRO_CNTL_RESERVED23                                          0x48d7
1833  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                             0x48d7
1834  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                             0x4977
1835  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                             0x9a17
1836  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                             0x9ab7
1837  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                             0x9b57
1838  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23                             0x9bf7
1839  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23                             0x9c97
1840  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23                             0x9d37
1841  #define mmUNIPHY_MACRO_CNTL_RESERVED24                                          0x48d8
1842  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                             0x48d8
1843  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                             0x4978
1844  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                             0x9a18
1845  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                             0x9ab8
1846  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                             0x9b58
1847  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24                             0x9bf8
1848  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24                             0x9c98
1849  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24                             0x9d38
1850  #define mmUNIPHY_MACRO_CNTL_RESERVED25                                          0x48d9
1851  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                             0x48d9
1852  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                             0x4979
1853  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                             0x9a19
1854  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                             0x9ab9
1855  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                             0x9b59
1856  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25                             0x9bf9
1857  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25                             0x9c99
1858  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25                             0x9d39
1859  #define mmUNIPHY_MACRO_CNTL_RESERVED26                                          0x48da
1860  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                             0x48da
1861  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                             0x497a
1862  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                             0x9a1a
1863  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                             0x9aba
1864  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                             0x9b5a
1865  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26                             0x9bfa
1866  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26                             0x9c9a
1867  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26                             0x9d3a
1868  #define mmUNIPHY_MACRO_CNTL_RESERVED27                                          0x48db
1869  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                             0x48db
1870  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                             0x497b
1871  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                             0x9a1b
1872  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                             0x9abb
1873  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                             0x9b5b
1874  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27                             0x9bfb
1875  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27                             0x9c9b
1876  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27                             0x9d3b
1877  #define mmUNIPHY_MACRO_CNTL_RESERVED28                                          0x48dc
1878  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                             0x48dc
1879  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                             0x497c
1880  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                             0x9a1c
1881  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                             0x9abc
1882  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                             0x9b5c
1883  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28                             0x9bfc
1884  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28                             0x9c9c
1885  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28                             0x9d3c
1886  #define mmUNIPHY_MACRO_CNTL_RESERVED29                                          0x48dd
1887  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                             0x48dd
1888  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                             0x497d
1889  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                             0x9a1d
1890  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                             0x9abd
1891  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                             0x9b5d
1892  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29                             0x9bfd
1893  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29                             0x9c9d
1894  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29                             0x9d3d
1895  #define mmUNIPHY_MACRO_CNTL_RESERVED30                                          0x48de
1896  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                             0x48de
1897  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                             0x497e
1898  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                             0x9a1e
1899  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                             0x9abe
1900  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                             0x9b5e
1901  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30                             0x9bfe
1902  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30                             0x9c9e
1903  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30                             0x9d3e
1904  #define mmUNIPHY_MACRO_CNTL_RESERVED31                                          0x48df
1905  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                             0x48df
1906  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                             0x497f
1907  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                             0x9a1f
1908  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                             0x9abf
1909  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                             0x9b5f
1910  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31                             0x9bff
1911  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31                             0x9c9f
1912  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31                             0x9d3f
1913  #define mmUNIPHY_MACRO_CNTL_RESERVED32                                          0x48e0
1914  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                             0x48e0
1915  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                             0x4980
1916  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                             0x9a20
1917  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                             0x9ac0
1918  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                             0x9b60
1919  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32                             0x9c00
1920  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32                             0x9ca0
1921  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED32                             0x9d40
1922  #define mmUNIPHY_MACRO_CNTL_RESERVED33                                          0x48e1
1923  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                             0x48e1
1924  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                             0x4981
1925  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                             0x9a21
1926  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                             0x9ac1
1927  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                             0x9b61
1928  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33                             0x9c01
1929  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33                             0x9ca1
1930  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED33                             0x9d41
1931  #define mmUNIPHY_MACRO_CNTL_RESERVED34                                          0x48e2
1932  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                             0x48e2
1933  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                             0x4982
1934  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                             0x9a22
1935  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                             0x9ac2
1936  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                             0x9b62
1937  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34                             0x9c02
1938  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34                             0x9ca2
1939  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED34                             0x9d42
1940  #define mmUNIPHY_MACRO_CNTL_RESERVED35                                          0x48e3
1941  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                             0x48e3
1942  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                             0x4983
1943  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                             0x9a23
1944  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                             0x9ac3
1945  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                             0x9b63
1946  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35                             0x9c03
1947  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35                             0x9ca3
1948  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED35                             0x9d43
1949  #define mmUNIPHY_MACRO_CNTL_RESERVED36                                          0x48e4
1950  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                             0x48e4
1951  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                             0x4984
1952  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                             0x9a24
1953  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                             0x9ac4
1954  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                             0x9b64
1955  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36                             0x9c04
1956  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36                             0x9ca4
1957  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED36                             0x9d44
1958  #define mmUNIPHY_MACRO_CNTL_RESERVED37                                          0x48e5
1959  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                             0x48e5
1960  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                             0x4985
1961  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                             0x9a25
1962  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                             0x9ac5
1963  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                             0x9b65
1964  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37                             0x9c05
1965  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37                             0x9ca5
1966  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED37                             0x9d45
1967  #define mmUNIPHY_MACRO_CNTL_RESERVED38                                          0x48e6
1968  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                             0x48e6
1969  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                             0x4986
1970  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                             0x9a26
1971  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                             0x9ac6
1972  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                             0x9b66
1973  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38                             0x9c06
1974  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38                             0x9ca6
1975  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED38                             0x9d46
1976  #define mmUNIPHY_MACRO_CNTL_RESERVED39                                          0x48e7
1977  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                             0x48e7
1978  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                             0x4987
1979  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                             0x9a27
1980  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                             0x9ac7
1981  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                             0x9b67
1982  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39                             0x9c07
1983  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39                             0x9ca7
1984  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED39                             0x9d47
1985  #define mmUNIPHY_MACRO_CNTL_RESERVED40                                          0x48e8
1986  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                             0x48e8
1987  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                             0x4988
1988  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                             0x9a28
1989  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                             0x9ac8
1990  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                             0x9b68
1991  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40                             0x9c08
1992  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40                             0x9ca8
1993  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED40                             0x9d48
1994  #define mmUNIPHY_MACRO_CNTL_RESERVED41                                          0x48e9
1995  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                             0x48e9
1996  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                             0x4989
1997  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                             0x9a29
1998  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                             0x9ac9
1999  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                             0x9b69
2000  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41                             0x9c09
2001  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41                             0x9ca9
2002  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED41                             0x9d49
2003  #define mmUNIPHY_MACRO_CNTL_RESERVED42                                          0x48ea
2004  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                             0x48ea
2005  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                             0x498a
2006  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                             0x9a2a
2007  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                             0x9aca
2008  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                             0x9b6a
2009  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42                             0x9c0a
2010  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42                             0x9caa
2011  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED42                             0x9d4a
2012  #define mmUNIPHY_MACRO_CNTL_RESERVED43                                          0x48eb
2013  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                             0x48eb
2014  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                             0x498b
2015  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                             0x9a2b
2016  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                             0x9acb
2017  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                             0x9b6b
2018  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43                             0x9c0b
2019  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43                             0x9cab
2020  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED43                             0x9d4b
2021  #define mmUNIPHY_MACRO_CNTL_RESERVED44                                          0x48ec
2022  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                             0x48ec
2023  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                             0x498c
2024  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                             0x9a2c
2025  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                             0x9acc
2026  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                             0x9b6c
2027  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44                             0x9c0c
2028  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44                             0x9cac
2029  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED44                             0x9d4c
2030  #define mmUNIPHY_MACRO_CNTL_RESERVED45                                          0x48ed
2031  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                             0x48ed
2032  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                             0x498d
2033  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                             0x9a2d
2034  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                             0x9acd
2035  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                             0x9b6d
2036  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45                             0x9c0d
2037  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45                             0x9cad
2038  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED45                             0x9d4d
2039  #define mmUNIPHY_MACRO_CNTL_RESERVED46                                          0x48ee
2040  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                             0x48ee
2041  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                             0x498e
2042  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                             0x9a2e
2043  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                             0x9ace
2044  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                             0x9b6e
2045  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46                             0x9c0e
2046  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46                             0x9cae
2047  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED46                             0x9d4e
2048  #define mmUNIPHY_MACRO_CNTL_RESERVED47                                          0x48ef
2049  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                             0x48ef
2050  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                             0x498f
2051  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                             0x9a2f
2052  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                             0x9acf
2053  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                             0x9b6f
2054  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47                             0x9c0f
2055  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47                             0x9caf
2056  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED47                             0x9d4f
2057  #define mmUNIPHY_MACRO_CNTL_RESERVED48                                          0x48f0
2058  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                             0x48f0
2059  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                             0x4990
2060  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                             0x9a30
2061  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                             0x9ad0
2062  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                             0x9b70
2063  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48                             0x9c10
2064  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48                             0x9cb0
2065  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED48                             0x9d50
2066  #define mmUNIPHY_MACRO_CNTL_RESERVED49                                          0x48f1
2067  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                             0x48f1
2068  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                             0x4991
2069  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                             0x9a31
2070  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                             0x9ad1
2071  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                             0x9b71
2072  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49                             0x9c11
2073  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49                             0x9cb1
2074  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED49                             0x9d51
2075  #define mmUNIPHY_MACRO_CNTL_RESERVED50                                          0x48f2
2076  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                             0x48f2
2077  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                             0x4992
2078  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                             0x9a32
2079  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                             0x9ad2
2080  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                             0x9b72
2081  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50                             0x9c12
2082  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50                             0x9cb2
2083  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED50                             0x9d52
2084  #define mmUNIPHY_MACRO_CNTL_RESERVED51                                          0x48f3
2085  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                             0x48f3
2086  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                             0x4993
2087  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                             0x9a33
2088  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                             0x9ad3
2089  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                             0x9b73
2090  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51                             0x9c13
2091  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51                             0x9cb3
2092  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED51                             0x9d53
2093  #define mmUNIPHY_MACRO_CNTL_RESERVED52                                          0x48f4
2094  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                             0x48f4
2095  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                             0x4994
2096  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                             0x9a34
2097  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                             0x9ad4
2098  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                             0x9b74
2099  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52                             0x9c14
2100  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52                             0x9cb4
2101  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED52                             0x9d54
2102  #define mmUNIPHY_MACRO_CNTL_RESERVED53                                          0x48f5
2103  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                             0x48f5
2104  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                             0x4995
2105  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                             0x9a35
2106  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                             0x9ad5
2107  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                             0x9b75
2108  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53                             0x9c15
2109  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53                             0x9cb5
2110  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED53                             0x9d55
2111  #define mmUNIPHY_MACRO_CNTL_RESERVED54                                          0x48f6
2112  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                             0x48f6
2113  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                             0x4996
2114  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                             0x9a36
2115  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                             0x9ad6
2116  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                             0x9b76
2117  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54                             0x9c16
2118  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54                             0x9cb6
2119  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED54                             0x9d56
2120  #define mmUNIPHY_MACRO_CNTL_RESERVED55                                          0x48f7
2121  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                             0x48f7
2122  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                             0x4997
2123  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                             0x9a37
2124  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                             0x9ad7
2125  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                             0x9b77
2126  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55                             0x9c17
2127  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55                             0x9cb7
2128  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED55                             0x9d57
2129  #define mmUNIPHY_MACRO_CNTL_RESERVED56                                          0x48f8
2130  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                             0x48f8
2131  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                             0x4998
2132  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                             0x9a38
2133  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                             0x9ad8
2134  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                             0x9b78
2135  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56                             0x9c18
2136  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56                             0x9cb8
2137  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED56                             0x9d58
2138  #define mmUNIPHY_MACRO_CNTL_RESERVED57                                          0x48f9
2139  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                             0x48f9
2140  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                             0x4999
2141  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                             0x9a39
2142  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                             0x9ad9
2143  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                             0x9b79
2144  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57                             0x9c19
2145  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57                             0x9cb9
2146  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED57                             0x9d59
2147  #define mmUNIPHY_MACRO_CNTL_RESERVED58                                          0x48fa
2148  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58                             0x48fa
2149  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58                             0x499a
2150  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58                             0x9a3a
2151  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58                             0x9ada
2152  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58                             0x9b7a
2153  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58                             0x9c1a
2154  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58                             0x9cba
2155  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED58                             0x9d5a
2156  #define mmUNIPHY_MACRO_CNTL_RESERVED59                                          0x48fb
2157  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59                             0x48fb
2158  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59                             0x499b
2159  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59                             0x9a3b
2160  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59                             0x9adb
2161  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59                             0x9b7b
2162  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59                             0x9c1b
2163  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59                             0x9cbb
2164  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED59                             0x9d5b
2165  #define mmUNIPHY_MACRO_CNTL_RESERVED60                                          0x48fc
2166  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60                             0x48fc
2167  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60                             0x499c
2168  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60                             0x9a3c
2169  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60                             0x9adc
2170  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60                             0x9b7c
2171  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60                             0x9c1c
2172  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60                             0x9cbc
2173  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED60                             0x9d5c
2174  #define mmUNIPHY_MACRO_CNTL_RESERVED61                                          0x48fd
2175  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61                             0x48fd
2176  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61                             0x499d
2177  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61                             0x9a3d
2178  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61                             0x9add
2179  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61                             0x9b7d
2180  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61                             0x9c1d
2181  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61                             0x9cbd
2182  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED61                             0x9d5d
2183  #define mmUNIPHY_MACRO_CNTL_RESERVED62                                          0x48fe
2184  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62                             0x48fe
2185  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62                             0x499e
2186  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62                             0x9a3e
2187  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62                             0x9ade
2188  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62                             0x9b7e
2189  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62                             0x9c1e
2190  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62                             0x9cbe
2191  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED62                             0x9d5e
2192  #define mmUNIPHY_MACRO_CNTL_RESERVED63                                          0x48ff
2193  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63                             0x48ff
2194  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63                             0x499f
2195  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63                             0x9a3f
2196  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63                             0x9adf
2197  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63                             0x9b7f
2198  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63                             0x9c1f
2199  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63                             0x9cbf
2200  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED63                             0x9d5f
2201  #define mmUNIPHY_MACRO_CNTL_RESERVED64                                          0x4900
2202  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64                             0x4900
2203  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64                             0x49a0
2204  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64                             0x9a40
2205  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64                             0x9ae0
2206  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64                             0x9b80
2207  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64                             0x9c20
2208  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64                             0x9cc0
2209  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED64                             0x9d60
2210  #define mmUNIPHY_MACRO_CNTL_RESERVED65                                          0x4901
2211  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65                             0x4901
2212  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65                             0x49a1
2213  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65                             0x9a41
2214  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65                             0x9ae1
2215  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65                             0x9b81
2216  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65                             0x9c21
2217  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65                             0x9cc1
2218  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED65                             0x9d61
2219  #define mmUNIPHY_MACRO_CNTL_RESERVED66                                          0x4902
2220  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66                             0x4902
2221  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66                             0x49a2
2222  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66                             0x9a42
2223  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66                             0x9ae2
2224  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66                             0x9b82
2225  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66                             0x9c22
2226  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66                             0x9cc2
2227  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED66                             0x9d62
2228  #define mmUNIPHY_MACRO_CNTL_RESERVED67                                          0x4903
2229  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67                             0x4903
2230  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67                             0x49a3
2231  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67                             0x9a43
2232  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67                             0x9ae3
2233  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67                             0x9b83
2234  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67                             0x9c23
2235  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67                             0x9cc3
2236  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED67                             0x9d63
2237  #define mmUNIPHY_MACRO_CNTL_RESERVED68                                          0x4904
2238  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68                             0x4904
2239  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68                             0x49a4
2240  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68                             0x9a44
2241  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68                             0x9ae4
2242  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68                             0x9b84
2243  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68                             0x9c24
2244  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68                             0x9cc4
2245  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED68                             0x9d64
2246  #define mmUNIPHY_MACRO_CNTL_RESERVED69                                          0x4905
2247  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69                             0x4905
2248  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69                             0x49a5
2249  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69                             0x9a45
2250  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69                             0x9ae5
2251  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69                             0x9b85
2252  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69                             0x9c25
2253  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69                             0x9cc5
2254  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED69                             0x9d65
2255  #define mmUNIPHY_MACRO_CNTL_RESERVED70                                          0x4906
2256  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70                             0x4906
2257  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70                             0x49a6
2258  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70                             0x9a46
2259  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70                             0x9ae6
2260  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70                             0x9b86
2261  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70                             0x9c26
2262  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70                             0x9cc6
2263  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED70                             0x9d66
2264  #define mmUNIPHY_MACRO_CNTL_RESERVED71                                          0x4907
2265  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71                             0x4907
2266  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71                             0x49a7
2267  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71                             0x9a47
2268  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71                             0x9ae7
2269  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71                             0x9b87
2270  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71                             0x9c27
2271  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71                             0x9cc7
2272  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED71                             0x9d67
2273  #define mmUNIPHY_MACRO_CNTL_RESERVED72                                          0x4908
2274  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72                             0x4908
2275  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72                             0x49a8
2276  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72                             0x9a48
2277  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72                             0x9ae8
2278  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72                             0x9b88
2279  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72                             0x9c28
2280  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72                             0x9cc8
2281  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED72                             0x9d68
2282  #define mmUNIPHY_MACRO_CNTL_RESERVED73                                          0x4909
2283  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73                             0x4909
2284  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73                             0x49a9
2285  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73                             0x9a49
2286  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73                             0x9ae9
2287  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73                             0x9b89
2288  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73                             0x9c29
2289  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73                             0x9cc9
2290  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED73                             0x9d69
2291  #define mmUNIPHY_MACRO_CNTL_RESERVED74                                          0x490a
2292  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74                             0x490a
2293  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74                             0x49aa
2294  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74                             0x9a4a
2295  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74                             0x9aea
2296  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74                             0x9b8a
2297  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74                             0x9c2a
2298  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74                             0x9cca
2299  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED74                             0x9d6a
2300  #define mmUNIPHY_MACRO_CNTL_RESERVED75                                          0x490b
2301  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75                             0x490b
2302  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75                             0x49ab
2303  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75                             0x9a4b
2304  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75                             0x9aeb
2305  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75                             0x9b8b
2306  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75                             0x9c2b
2307  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75                             0x9ccb
2308  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED75                             0x9d6b
2309  #define mmUNIPHY_MACRO_CNTL_RESERVED76                                          0x490c
2310  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76                             0x490c
2311  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76                             0x49ac
2312  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76                             0x9a4c
2313  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76                             0x9aec
2314  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76                             0x9b8c
2315  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76                             0x9c2c
2316  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76                             0x9ccc
2317  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED76                             0x9d6c
2318  #define mmUNIPHY_MACRO_CNTL_RESERVED77                                          0x490d
2319  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77                             0x490d
2320  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77                             0x49ad
2321  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77                             0x9a4d
2322  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77                             0x9aed
2323  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77                             0x9b8d
2324  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77                             0x9c2d
2325  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77                             0x9ccd
2326  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED77                             0x9d6d
2327  #define mmUNIPHY_MACRO_CNTL_RESERVED78                                          0x490e
2328  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78                             0x490e
2329  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78                             0x49ae
2330  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78                             0x9a4e
2331  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78                             0x9aee
2332  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78                             0x9b8e
2333  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78                             0x9c2e
2334  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78                             0x9cce
2335  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED78                             0x9d6e
2336  #define mmUNIPHY_MACRO_CNTL_RESERVED79                                          0x490f
2337  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79                             0x490f
2338  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79                             0x49af
2339  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79                             0x9a4f
2340  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79                             0x9aef
2341  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79                             0x9b8f
2342  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79                             0x9c2f
2343  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79                             0x9ccf
2344  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED79                             0x9d6f
2345  #define mmUNIPHY_MACRO_CNTL_RESERVED80                                          0x4910
2346  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80                             0x4910
2347  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80                             0x49b0
2348  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80                             0x9a50
2349  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80                             0x9af0
2350  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80                             0x9b90
2351  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80                             0x9c30
2352  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80                             0x9cd0
2353  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED80                             0x9d70
2354  #define mmUNIPHY_MACRO_CNTL_RESERVED81                                          0x4911
2355  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81                             0x4911
2356  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81                             0x49b1
2357  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81                             0x9a51
2358  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81                             0x9af1
2359  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81                             0x9b91
2360  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81                             0x9c31
2361  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81                             0x9cd1
2362  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED81                             0x9d71
2363  #define mmUNIPHY_MACRO_CNTL_RESERVED82                                          0x4912
2364  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82                             0x4912
2365  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82                             0x49b2
2366  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82                             0x9a52
2367  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82                             0x9af2
2368  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82                             0x9b92
2369  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82                             0x9c32
2370  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82                             0x9cd2
2371  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED82                             0x9d72
2372  #define mmUNIPHY_MACRO_CNTL_RESERVED83                                          0x4913
2373  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83                             0x4913
2374  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83                             0x49b3
2375  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83                             0x9a53
2376  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83                             0x9af3
2377  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83                             0x9b93
2378  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83                             0x9c33
2379  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83                             0x9cd3
2380  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED83                             0x9d73
2381  #define mmUNIPHY_MACRO_CNTL_RESERVED84                                          0x4914
2382  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84                             0x4914
2383  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84                             0x49b4
2384  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84                             0x9a54
2385  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84                             0x9af4
2386  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84                             0x9b94
2387  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84                             0x9c34
2388  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84                             0x9cd4
2389  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED84                             0x9d74
2390  #define mmUNIPHY_MACRO_CNTL_RESERVED85                                          0x4915
2391  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85                             0x4915
2392  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85                             0x49b5
2393  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85                             0x9a55
2394  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85                             0x9af5
2395  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85                             0x9b95
2396  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85                             0x9c35
2397  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85                             0x9cd5
2398  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED85                             0x9d75
2399  #define mmUNIPHY_MACRO_CNTL_RESERVED86                                          0x4916
2400  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86                             0x4916
2401  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86                             0x49b6
2402  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86                             0x9a56
2403  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86                             0x9af6
2404  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86                             0x9b96
2405  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86                             0x9c36
2406  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86                             0x9cd6
2407  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED86                             0x9d76
2408  #define mmUNIPHY_MACRO_CNTL_RESERVED87                                          0x4917
2409  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87                             0x4917
2410  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87                             0x49b7
2411  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87                             0x9a57
2412  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87                             0x9af7
2413  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87                             0x9b97
2414  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87                             0x9c37
2415  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87                             0x9cd7
2416  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED87                             0x9d77
2417  #define mmUNIPHY_MACRO_CNTL_RESERVED88                                          0x4918
2418  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88                             0x4918
2419  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88                             0x49b8
2420  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88                             0x9a58
2421  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88                             0x9af8
2422  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88                             0x9b98
2423  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88                             0x9c38
2424  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88                             0x9cd8
2425  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED88                             0x9d78
2426  #define mmUNIPHY_MACRO_CNTL_RESERVED89                                          0x4919
2427  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89                             0x4919
2428  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89                             0x49b9
2429  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89                             0x9a59
2430  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89                             0x9af9
2431  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89                             0x9b99
2432  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89                             0x9c39
2433  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89                             0x9cd9
2434  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED89                             0x9d79
2435  #define mmUNIPHY_MACRO_CNTL_RESERVED90                                          0x491a
2436  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90                             0x491a
2437  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90                             0x49ba
2438  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90                             0x9a5a
2439  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90                             0x9afa
2440  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90                             0x9b9a
2441  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90                             0x9c3a
2442  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90                             0x9cda
2443  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED90                             0x9d7a
2444  #define mmUNIPHY_MACRO_CNTL_RESERVED91                                          0x491b
2445  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91                             0x491b
2446  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91                             0x49bb
2447  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91                             0x9a5b
2448  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91                             0x9afb
2449  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91                             0x9b9b
2450  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91                             0x9c3b
2451  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91                             0x9cdb
2452  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED91                             0x9d7b
2453  #define mmUNIPHY_MACRO_CNTL_RESERVED92                                          0x491c
2454  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92                             0x491c
2455  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92                             0x49bc
2456  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92                             0x9a5c
2457  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92                             0x9afc
2458  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92                             0x9b9c
2459  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92                             0x9c3c
2460  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92                             0x9cdc
2461  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED92                             0x9d7c
2462  #define mmUNIPHY_MACRO_CNTL_RESERVED93                                          0x491d
2463  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93                             0x491d
2464  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93                             0x49bd
2465  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93                             0x9a5d
2466  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93                             0x9afd
2467  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93                             0x9b9d
2468  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93                             0x9c3d
2469  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93                             0x9cdd
2470  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED93                             0x9d7d
2471  #define mmUNIPHY_MACRO_CNTL_RESERVED94                                          0x491e
2472  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94                             0x491e
2473  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94                             0x49be
2474  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94                             0x9a5e
2475  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94                             0x9afe
2476  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94                             0x9b9e
2477  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94                             0x9c3e
2478  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94                             0x9cde
2479  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED94                             0x9d7e
2480  #define mmUNIPHY_MACRO_CNTL_RESERVED95                                          0x491f
2481  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95                             0x491f
2482  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95                             0x49bf
2483  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95                             0x9a5f
2484  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95                             0x9aff
2485  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95                             0x9b9f
2486  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95                             0x9c3f
2487  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95                             0x9cdf
2488  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED95                             0x9d7f
2489  #define mmUNIPHY_MACRO_CNTL_RESERVED96                                          0x4920
2490  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96                             0x4920
2491  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96                             0x49c0
2492  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96                             0x9a60
2493  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96                             0x9b00
2494  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96                             0x9ba0
2495  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96                             0x9c40
2496  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96                             0x9ce0
2497  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED96                             0x9d80
2498  #define mmUNIPHY_MACRO_CNTL_RESERVED97                                          0x4921
2499  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97                             0x4921
2500  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97                             0x49c1
2501  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97                             0x9a61
2502  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97                             0x9b01
2503  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97                             0x9ba1
2504  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97                             0x9c41
2505  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97                             0x9ce1
2506  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED97                             0x9d81
2507  #define mmUNIPHY_MACRO_CNTL_RESERVED98                                          0x4922
2508  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98                             0x4922
2509  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98                             0x49c2
2510  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98                             0x9a62
2511  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98                             0x9b02
2512  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98                             0x9ba2
2513  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98                             0x9c42
2514  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98                             0x9ce2
2515  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED98                             0x9d82
2516  #define mmUNIPHY_MACRO_CNTL_RESERVED99                                          0x4923
2517  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99                             0x4923
2518  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99                             0x49c3
2519  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99                             0x9a63
2520  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99                             0x9b03
2521  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99                             0x9ba3
2522  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99                             0x9c43
2523  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99                             0x9ce3
2524  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED99                             0x9d83
2525  #define mmUNIPHY_MACRO_CNTL_RESERVED100                                         0x4924
2526  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100                            0x4924
2527  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100                            0x49c4
2528  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100                            0x9a64
2529  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100                            0x9b04
2530  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100                            0x9ba4
2531  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100                            0x9c44
2532  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100                            0x9ce4
2533  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED100                            0x9d84
2534  #define mmUNIPHY_MACRO_CNTL_RESERVED101                                         0x4925
2535  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101                            0x4925
2536  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101                            0x49c5
2537  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101                            0x9a65
2538  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101                            0x9b05
2539  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101                            0x9ba5
2540  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101                            0x9c45
2541  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101                            0x9ce5
2542  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED101                            0x9d85
2543  #define mmUNIPHY_MACRO_CNTL_RESERVED102                                         0x4926
2544  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102                            0x4926
2545  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102                            0x49c6
2546  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102                            0x9a66
2547  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102                            0x9b06
2548  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102                            0x9ba6
2549  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102                            0x9c46
2550  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102                            0x9ce6
2551  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED102                            0x9d86
2552  #define mmUNIPHY_MACRO_CNTL_RESERVED103                                         0x4927
2553  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103                            0x4927
2554  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103                            0x49c7
2555  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103                            0x9a67
2556  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103                            0x9b07
2557  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103                            0x9ba7
2558  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103                            0x9c47
2559  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103                            0x9ce7
2560  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED103                            0x9d87
2561  #define mmUNIPHY_MACRO_CNTL_RESERVED104                                         0x4928
2562  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104                            0x4928
2563  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104                            0x49c8
2564  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104                            0x9a68
2565  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104                            0x9b08
2566  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104                            0x9ba8
2567  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104                            0x9c48
2568  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104                            0x9ce8
2569  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED104                            0x9d88
2570  #define mmUNIPHY_MACRO_CNTL_RESERVED105                                         0x4929
2571  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105                            0x4929
2572  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105                            0x49c9
2573  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105                            0x9a69
2574  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105                            0x9b09
2575  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105                            0x9ba9
2576  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105                            0x9c49
2577  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105                            0x9ce9
2578  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED105                            0x9d89
2579  #define mmUNIPHY_MACRO_CNTL_RESERVED106                                         0x492a
2580  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106                            0x492a
2581  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106                            0x49ca
2582  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106                            0x9a6a
2583  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106                            0x9b0a
2584  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106                            0x9baa
2585  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106                            0x9c4a
2586  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106                            0x9cea
2587  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED106                            0x9d8a
2588  #define mmUNIPHY_MACRO_CNTL_RESERVED107                                         0x492b
2589  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107                            0x492b
2590  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107                            0x49cb
2591  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107                            0x9a6b
2592  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107                            0x9b0b
2593  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107                            0x9bab
2594  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107                            0x9c4b
2595  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107                            0x9ceb
2596  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED107                            0x9d8b
2597  #define mmUNIPHY_MACRO_CNTL_RESERVED108                                         0x492c
2598  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108                            0x492c
2599  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108                            0x49cc
2600  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108                            0x9a6c
2601  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108                            0x9b0c
2602  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108                            0x9bac
2603  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108                            0x9c4c
2604  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108                            0x9cec
2605  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED108                            0x9d8c
2606  #define mmUNIPHY_MACRO_CNTL_RESERVED109                                         0x492d
2607  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109                            0x492d
2608  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109                            0x49cd
2609  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109                            0x9a6d
2610  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109                            0x9b0d
2611  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109                            0x9bad
2612  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109                            0x9c4d
2613  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109                            0x9ced
2614  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED109                            0x9d8d
2615  #define mmUNIPHY_MACRO_CNTL_RESERVED110                                         0x492e
2616  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110                            0x492e
2617  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110                            0x49ce
2618  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110                            0x9a6e
2619  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110                            0x9b0e
2620  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110                            0x9bae
2621  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110                            0x9c4e
2622  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110                            0x9cee
2623  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED110                            0x9d8e
2624  #define mmUNIPHY_MACRO_CNTL_RESERVED111                                         0x492f
2625  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111                            0x492f
2626  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111                            0x49cf
2627  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111                            0x9a6f
2628  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111                            0x9b0f
2629  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111                            0x9baf
2630  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111                            0x9c4f
2631  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111                            0x9cef
2632  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED111                            0x9d8f
2633  #define mmUNIPHY_MACRO_CNTL_RESERVED112                                         0x4930
2634  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112                            0x4930
2635  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112                            0x49d0
2636  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112                            0x9a70
2637  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112                            0x9b10
2638  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112                            0x9bb0
2639  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112                            0x9c50
2640  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112                            0x9cf0
2641  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED112                            0x9d90
2642  #define mmUNIPHY_MACRO_CNTL_RESERVED113                                         0x4931
2643  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113                            0x4931
2644  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113                            0x49d1
2645  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113                            0x9a71
2646  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113                            0x9b11
2647  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113                            0x9bb1
2648  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113                            0x9c51
2649  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113                            0x9cf1
2650  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED113                            0x9d91
2651  #define mmUNIPHY_MACRO_CNTL_RESERVED114                                         0x4932
2652  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114                            0x4932
2653  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114                            0x49d2
2654  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114                            0x9a72
2655  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114                            0x9b12
2656  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114                            0x9bb2
2657  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114                            0x9c52
2658  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114                            0x9cf2
2659  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED114                            0x9d92
2660  #define mmUNIPHY_MACRO_CNTL_RESERVED115                                         0x4933
2661  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115                            0x4933
2662  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115                            0x49d3
2663  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115                            0x9a73
2664  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115                            0x9b13
2665  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115                            0x9bb3
2666  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115                            0x9c53
2667  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115                            0x9cf3
2668  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED115                            0x9d93
2669  #define mmUNIPHY_MACRO_CNTL_RESERVED116                                         0x4934
2670  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116                            0x4934
2671  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116                            0x49d4
2672  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116                            0x9a74
2673  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116                            0x9b14
2674  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116                            0x9bb4
2675  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116                            0x9c54
2676  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116                            0x9cf4
2677  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED116                            0x9d94
2678  #define mmUNIPHY_MACRO_CNTL_RESERVED117                                         0x4935
2679  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117                            0x4935
2680  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117                            0x49d5
2681  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117                            0x9a75
2682  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117                            0x9b15
2683  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117                            0x9bb5
2684  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117                            0x9c55
2685  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117                            0x9cf5
2686  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED117                            0x9d95
2687  #define mmUNIPHY_MACRO_CNTL_RESERVED118                                         0x4936
2688  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118                            0x4936
2689  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118                            0x49d6
2690  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118                            0x9a76
2691  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118                            0x9b16
2692  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118                            0x9bb6
2693  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118                            0x9c56
2694  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118                            0x9cf6
2695  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED118                            0x9d96
2696  #define mmUNIPHY_MACRO_CNTL_RESERVED119                                         0x4937
2697  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119                            0x4937
2698  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119                            0x49d7
2699  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119                            0x9a77
2700  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119                            0x9b17
2701  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119                            0x9bb7
2702  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119                            0x9c57
2703  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119                            0x9cf7
2704  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED119                            0x9d97
2705  #define mmUNIPHY_MACRO_CNTL_RESERVED120                                         0x4938
2706  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120                            0x4938
2707  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120                            0x49d8
2708  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120                            0x9a78
2709  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120                            0x9b18
2710  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120                            0x9bb8
2711  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120                            0x9c58
2712  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120                            0x9cf8
2713  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED120                            0x9d98
2714  #define mmUNIPHY_MACRO_CNTL_RESERVED121                                         0x4939
2715  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121                            0x4939
2716  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121                            0x49d9
2717  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121                            0x9a79
2718  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121                            0x9b19
2719  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121                            0x9bb9
2720  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121                            0x9c59
2721  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121                            0x9cf9
2722  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED121                            0x9d99
2723  #define mmUNIPHY_MACRO_CNTL_RESERVED122                                         0x493a
2724  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122                            0x493a
2725  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122                            0x49da
2726  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122                            0x9a7a
2727  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122                            0x9b1a
2728  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122                            0x9bba
2729  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122                            0x9c5a
2730  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122                            0x9cfa
2731  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED122                            0x9d9a
2732  #define mmUNIPHY_MACRO_CNTL_RESERVED123                                         0x493b
2733  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123                            0x493b
2734  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123                            0x49db
2735  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123                            0x9a7b
2736  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123                            0x9b1b
2737  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123                            0x9bbb
2738  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123                            0x9c5b
2739  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123                            0x9cfb
2740  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED123                            0x9d9b
2741  #define mmUNIPHY_MACRO_CNTL_RESERVED124                                         0x493c
2742  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124                            0x493c
2743  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124                            0x49dc
2744  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124                            0x9a7c
2745  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124                            0x9b1c
2746  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124                            0x9bbc
2747  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124                            0x9c5c
2748  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124                            0x9cfc
2749  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED124                            0x9d9c
2750  #define mmUNIPHY_MACRO_CNTL_RESERVED125                                         0x493d
2751  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125                            0x493d
2752  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125                            0x49dd
2753  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125                            0x9a7d
2754  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125                            0x9b1d
2755  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125                            0x9bbd
2756  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125                            0x9c5d
2757  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125                            0x9cfd
2758  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED125                            0x9d9d
2759  #define mmUNIPHY_MACRO_CNTL_RESERVED126                                         0x493e
2760  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126                            0x493e
2761  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126                            0x49de
2762  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126                            0x9a7e
2763  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126                            0x9b1e
2764  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126                            0x9bbe
2765  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126                            0x9c5e
2766  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126                            0x9cfe
2767  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED126                            0x9d9e
2768  #define mmUNIPHY_MACRO_CNTL_RESERVED127                                         0x493f
2769  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127                            0x493f
2770  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127                            0x49df
2771  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127                            0x9a7f
2772  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127                            0x9b1f
2773  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127                            0x9bbf
2774  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127                            0x9c5f
2775  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127                            0x9cff
2776  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED127                            0x9d9f
2777  #define mmUNIPHY_MACRO_CNTL_RESERVED128                                         0x4940
2778  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128                            0x4940
2779  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128                            0x49e0
2780  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128                            0x9a80
2781  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128                            0x9b20
2782  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128                            0x9bc0
2783  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128                            0x9c60
2784  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128                            0x9d00
2785  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED128                            0x9da0
2786  #define mmUNIPHY_MACRO_CNTL_RESERVED129                                         0x4941
2787  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129                            0x4941
2788  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129                            0x49e1
2789  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129                            0x9a81
2790  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129                            0x9b21
2791  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129                            0x9bc1
2792  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129                            0x9c61
2793  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129                            0x9d01
2794  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED129                            0x9da1
2795  #define mmUNIPHY_MACRO_CNTL_RESERVED130                                         0x4942
2796  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130                            0x4942
2797  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130                            0x49e2
2798  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130                            0x9a82
2799  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130                            0x9b22
2800  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130                            0x9bc2
2801  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130                            0x9c62
2802  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130                            0x9d02
2803  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED130                            0x9da2
2804  #define mmUNIPHY_MACRO_CNTL_RESERVED131                                         0x4943
2805  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131                            0x4943
2806  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131                            0x49e3
2807  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131                            0x9a83
2808  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131                            0x9b23
2809  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131                            0x9bc3
2810  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131                            0x9c63
2811  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131                            0x9d03
2812  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED131                            0x9da3
2813  #define mmUNIPHY_MACRO_CNTL_RESERVED132                                         0x4944
2814  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132                            0x4944
2815  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132                            0x49e4
2816  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132                            0x9a84
2817  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132                            0x9b24
2818  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132                            0x9bc4
2819  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132                            0x9c64
2820  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132                            0x9d04
2821  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED132                            0x9da4
2822  #define mmUNIPHY_MACRO_CNTL_RESERVED133                                         0x4945
2823  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133                            0x4945
2824  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133                            0x49e5
2825  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133                            0x9a85
2826  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133                            0x9b25
2827  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133                            0x9bc5
2828  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133                            0x9c65
2829  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133                            0x9d05
2830  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED133                            0x9da5
2831  #define mmUNIPHY_MACRO_CNTL_RESERVED134                                         0x4946
2832  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134                            0x4946
2833  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134                            0x49e6
2834  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134                            0x9a86
2835  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134                            0x9b26
2836  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134                            0x9bc6
2837  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134                            0x9c66
2838  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134                            0x9d06
2839  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED134                            0x9da6
2840  #define mmUNIPHY_MACRO_CNTL_RESERVED135                                         0x4947
2841  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135                            0x4947
2842  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135                            0x49e7
2843  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135                            0x9a87
2844  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135                            0x9b27
2845  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135                            0x9bc7
2846  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135                            0x9c67
2847  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135                            0x9d07
2848  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED135                            0x9da7
2849  #define mmUNIPHY_MACRO_CNTL_RESERVED136                                         0x4948
2850  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136                            0x4948
2851  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136                            0x49e8
2852  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136                            0x9a88
2853  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136                            0x9b28
2854  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136                            0x9bc8
2855  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136                            0x9c68
2856  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136                            0x9d08
2857  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED136                            0x9da8
2858  #define mmUNIPHY_MACRO_CNTL_RESERVED137                                         0x4949
2859  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137                            0x4949
2860  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137                            0x49e9
2861  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137                            0x9a89
2862  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137                            0x9b29
2863  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137                            0x9bc9
2864  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137                            0x9c69
2865  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137                            0x9d09
2866  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED137                            0x9da9
2867  #define mmUNIPHY_MACRO_CNTL_RESERVED138                                         0x494a
2868  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138                            0x494a
2869  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138                            0x49ea
2870  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138                            0x9a8a
2871  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138                            0x9b2a
2872  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138                            0x9bca
2873  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138                            0x9c6a
2874  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138                            0x9d0a
2875  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED138                            0x9daa
2876  #define mmUNIPHY_MACRO_CNTL_RESERVED139                                         0x494b
2877  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139                            0x494b
2878  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139                            0x49eb
2879  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139                            0x9a8b
2880  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139                            0x9b2b
2881  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139                            0x9bcb
2882  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139                            0x9c6b
2883  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139                            0x9d0b
2884  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED139                            0x9dab
2885  #define mmUNIPHY_MACRO_CNTL_RESERVED140                                         0x494c
2886  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140                            0x494c
2887  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140                            0x49ec
2888  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140                            0x9a8c
2889  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140                            0x9b2c
2890  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140                            0x9bcc
2891  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140                            0x9c6c
2892  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140                            0x9d0c
2893  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED140                            0x9dac
2894  #define mmUNIPHY_MACRO_CNTL_RESERVED141                                         0x494d
2895  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141                            0x494d
2896  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141                            0x49ed
2897  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141                            0x9a8d
2898  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141                            0x9b2d
2899  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141                            0x9bcd
2900  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141                            0x9c6d
2901  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141                            0x9d0d
2902  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED141                            0x9dad
2903  #define mmUNIPHY_MACRO_CNTL_RESERVED142                                         0x494e
2904  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142                            0x494e
2905  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142                            0x49ee
2906  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142                            0x9a8e
2907  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142                            0x9b2e
2908  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142                            0x9bce
2909  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142                            0x9c6e
2910  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142                            0x9d0e
2911  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED142                            0x9dae
2912  #define mmUNIPHY_MACRO_CNTL_RESERVED143                                         0x494f
2913  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143                            0x494f
2914  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143                            0x49ef
2915  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143                            0x9a8f
2916  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143                            0x9b2f
2917  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143                            0x9bcf
2918  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143                            0x9c6f
2919  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143                            0x9d0f
2920  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED143                            0x9daf
2921  #define mmUNIPHY_MACRO_CNTL_RESERVED144                                         0x4950
2922  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144                            0x4950
2923  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144                            0x49f0
2924  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144                            0x9a90
2925  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144                            0x9b30
2926  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144                            0x9bd0
2927  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144                            0x9c70
2928  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144                            0x9d10
2929  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED144                            0x9db0
2930  #define mmUNIPHY_MACRO_CNTL_RESERVED145                                         0x4951
2931  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145                            0x4951
2932  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145                            0x49f1
2933  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145                            0x9a91
2934  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145                            0x9b31
2935  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145                            0x9bd1
2936  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145                            0x9c71
2937  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145                            0x9d11
2938  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED145                            0x9db1
2939  #define mmUNIPHY_MACRO_CNTL_RESERVED146                                         0x4952
2940  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146                            0x4952
2941  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146                            0x49f2
2942  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146                            0x9a92
2943  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146                            0x9b32
2944  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146                            0x9bd2
2945  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146                            0x9c72
2946  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146                            0x9d12
2947  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED146                            0x9db2
2948  #define mmUNIPHY_MACRO_CNTL_RESERVED147                                         0x4953
2949  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147                            0x4953
2950  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147                            0x49f3
2951  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147                            0x9a93
2952  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147                            0x9b33
2953  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147                            0x9bd3
2954  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147                            0x9c73
2955  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147                            0x9d13
2956  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED147                            0x9db3
2957  #define mmUNIPHY_MACRO_CNTL_RESERVED148                                         0x4954
2958  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148                            0x4954
2959  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148                            0x49f4
2960  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148                            0x9a94
2961  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148                            0x9b34
2962  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148                            0x9bd4
2963  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148                            0x9c74
2964  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148                            0x9d14
2965  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED148                            0x9db4
2966  #define mmUNIPHY_MACRO_CNTL_RESERVED149                                         0x4955
2967  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149                            0x4955
2968  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149                            0x49f5
2969  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149                            0x9a95
2970  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149                            0x9b35
2971  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149                            0x9bd5
2972  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149                            0x9c75
2973  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149                            0x9d15
2974  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED149                            0x9db5
2975  #define mmUNIPHY_MACRO_CNTL_RESERVED150                                         0x4956
2976  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150                            0x4956
2977  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150                            0x49f6
2978  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150                            0x9a96
2979  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150                            0x9b36
2980  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150                            0x9bd6
2981  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150                            0x9c76
2982  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150                            0x9d16
2983  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED150                            0x9db6
2984  #define mmUNIPHY_MACRO_CNTL_RESERVED151                                         0x4957
2985  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151                            0x4957
2986  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151                            0x49f7
2987  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151                            0x9a97
2988  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151                            0x9b37
2989  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151                            0x9bd7
2990  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151                            0x9c77
2991  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151                            0x9d17
2992  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED151                            0x9db7
2993  #define mmUNIPHY_MACRO_CNTL_RESERVED152                                         0x4958
2994  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152                            0x4958
2995  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152                            0x49f8
2996  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152                            0x9a98
2997  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152                            0x9b38
2998  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152                            0x9bd8
2999  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152                            0x9c78
3000  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152                            0x9d18
3001  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED152                            0x9db8
3002  #define mmUNIPHY_MACRO_CNTL_RESERVED153                                         0x4959
3003  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153                            0x4959
3004  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153                            0x49f9
3005  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153                            0x9a99
3006  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153                            0x9b39
3007  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153                            0x9bd9
3008  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153                            0x9c79
3009  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153                            0x9d19
3010  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED153                            0x9db9
3011  #define mmUNIPHY_MACRO_CNTL_RESERVED154                                         0x495a
3012  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154                            0x495a
3013  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154                            0x49fa
3014  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154                            0x9a9a
3015  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154                            0x9b3a
3016  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154                            0x9bda
3017  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154                            0x9c7a
3018  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154                            0x9d1a
3019  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED154                            0x9dba
3020  #define mmUNIPHY_MACRO_CNTL_RESERVED155                                         0x495b
3021  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155                            0x495b
3022  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155                            0x49fb
3023  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155                            0x9a9b
3024  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155                            0x9b3b
3025  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155                            0x9bdb
3026  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155                            0x9c7b
3027  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155                            0x9d1b
3028  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED155                            0x9dbb
3029  #define mmUNIPHY_MACRO_CNTL_RESERVED156                                         0x495c
3030  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156                            0x495c
3031  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156                            0x49fc
3032  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156                            0x9a9c
3033  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156                            0x9b3c
3034  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156                            0x9bdc
3035  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156                            0x9c7c
3036  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156                            0x9d1c
3037  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED156                            0x9dbc
3038  #define mmUNIPHY_MACRO_CNTL_RESERVED157                                         0x495d
3039  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157                            0x495d
3040  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157                            0x49fd
3041  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157                            0x9a9d
3042  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157                            0x9b3d
3043  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157                            0x9bdd
3044  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157                            0x9c7d
3045  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157                            0x9d1d
3046  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED157                            0x9dbd
3047  #define mmUNIPHY_MACRO_CNTL_RESERVED158                                         0x495e
3048  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158                            0x495e
3049  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158                            0x49fe
3050  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158                            0x9a9e
3051  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158                            0x9b3e
3052  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158                            0x9bde
3053  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158                            0x9c7e
3054  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158                            0x9d1e
3055  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED158                            0x9dbe
3056  #define mmUNIPHY_MACRO_CNTL_RESERVED159                                         0x495f
3057  #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159                            0x495f
3058  #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159                            0x49ff
3059  #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159                            0x9a9f
3060  #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159                            0x9b3f
3061  #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159                            0x9bdf
3062  #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159                            0x9c7f
3063  #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159                            0x9d1f
3064  #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED159                            0x9dbf
3065  #define mmDCRX_PHY_MACRO_CNTL_RESERVED0                                         0x5a84
3066  #define mmDCRX_PHY_MACRO_CNTL_RESERVED1                                         0x5a85
3067  #define mmDCRX_PHY_MACRO_CNTL_RESERVED2                                         0x5a86
3068  #define mmDCRX_PHY_MACRO_CNTL_RESERVED3                                         0x5a87
3069  #define mmDCRX_PHY_MACRO_CNTL_RESERVED4                                         0x5a88
3070  #define mmDCRX_PHY_MACRO_CNTL_RESERVED5                                         0x5a89
3071  #define mmDCRX_PHY_MACRO_CNTL_RESERVED6                                         0x5a8a
3072  #define mmDCRX_PHY_MACRO_CNTL_RESERVED7                                         0x5a8b
3073  #define mmDCRX_PHY_MACRO_CNTL_RESERVED8                                         0x5a8c
3074  #define mmDCRX_PHY_MACRO_CNTL_RESERVED9                                         0x5a8d
3075  #define mmDCRX_PHY_MACRO_CNTL_RESERVED10                                        0x5a8e
3076  #define mmDCRX_PHY_MACRO_CNTL_RESERVED11                                        0x5a8f
3077  #define mmDCRX_PHY_MACRO_CNTL_RESERVED12                                        0x5a90
3078  #define mmDCRX_PHY_MACRO_CNTL_RESERVED13                                        0x5a91
3079  #define mmDCRX_PHY_MACRO_CNTL_RESERVED14                                        0x5a92
3080  #define mmDCRX_PHY_MACRO_CNTL_RESERVED15                                        0x5a93
3081  #define mmDCRX_PHY_MACRO_CNTL_RESERVED16                                        0x5a94
3082  #define mmDCRX_PHY_MACRO_CNTL_RESERVED17                                        0x5a95
3083  #define mmDCRX_PHY_MACRO_CNTL_RESERVED18                                        0x5a96
3084  #define mmDCRX_PHY_MACRO_CNTL_RESERVED19                                        0x5a97
3085  #define mmDCRX_PHY_MACRO_CNTL_RESERVED20                                        0x5a98
3086  #define mmDCRX_PHY_MACRO_CNTL_RESERVED21                                        0x5a99
3087  #define mmDCRX_PHY_MACRO_CNTL_RESERVED22                                        0x5a9a
3088  #define mmDCRX_PHY_MACRO_CNTL_RESERVED23                                        0x5a9b
3089  #define mmDCRX_PHY_MACRO_CNTL_RESERVED24                                        0x5a9c
3090  #define mmDCRX_PHY_MACRO_CNTL_RESERVED25                                        0x5a9d
3091  #define mmDCRX_PHY_MACRO_CNTL_RESERVED26                                        0x5a9e
3092  #define mmDCRX_PHY_MACRO_CNTL_RESERVED27                                        0x5a9f
3093  #define mmDCRX_PHY_MACRO_CNTL_RESERVED28                                        0x5aa0
3094  #define mmDCRX_PHY_MACRO_CNTL_RESERVED29                                        0x5aa1
3095  #define mmDCRX_PHY_MACRO_CNTL_RESERVED30                                        0x5aa2
3096  #define mmDCRX_PHY_MACRO_CNTL_RESERVED31                                        0x5aa3
3097  #define mmDCRX_PHY_MACRO_CNTL_RESERVED32                                        0x5aa4
3098  #define mmDCRX_PHY_MACRO_CNTL_RESERVED33                                        0x5aa5
3099  #define mmDCRX_PHY_MACRO_CNTL_RESERVED34                                        0x5aa6
3100  #define mmDCRX_PHY_MACRO_CNTL_RESERVED35                                        0x5aa7
3101  #define mmDCRX_PHY_MACRO_CNTL_RESERVED36                                        0x5aa8
3102  #define mmDCRX_PHY_MACRO_CNTL_RESERVED37                                        0x5aa9
3103  #define mmDCRX_PHY_MACRO_CNTL_RESERVED38                                        0x5aaa
3104  #define mmDCRX_PHY_MACRO_CNTL_RESERVED39                                        0x5aab
3105  #define mmDCRX_PHY_MACRO_CNTL_RESERVED40                                        0x5aac
3106  #define mmDCRX_PHY_MACRO_CNTL_RESERVED41                                        0x5aad
3107  #define mmDCRX_PHY_MACRO_CNTL_RESERVED42                                        0x5aae
3108  #define mmDCRX_PHY_MACRO_CNTL_RESERVED43                                        0x5aaf
3109  #define mmDCRX_PHY_MACRO_CNTL_RESERVED44                                        0x5ab0
3110  #define mmDCRX_PHY_MACRO_CNTL_RESERVED45                                        0x5ab1
3111  #define mmDCRX_PHY_MACRO_CNTL_RESERVED46                                        0x5ab2
3112  #define mmDCRX_PHY_MACRO_CNTL_RESERVED47                                        0x5ab3
3113  #define mmDCRX_PHY_MACRO_CNTL_RESERVED48                                        0x5ab4
3114  #define mmDCRX_PHY_MACRO_CNTL_RESERVED49                                        0x5ab5
3115  #define mmDCRX_PHY_MACRO_CNTL_RESERVED50                                        0x5ab6
3116  #define mmDCRX_PHY_MACRO_CNTL_RESERVED51                                        0x5ab7
3117  #define mmDCRX_PHY_MACRO_CNTL_RESERVED52                                        0x5ab8
3118  #define mmDCRX_PHY_MACRO_CNTL_RESERVED53                                        0x5ab9
3119  #define mmDCRX_PHY_MACRO_CNTL_RESERVED54                                        0x5aba
3120  #define mmDCRX_PHY_MACRO_CNTL_RESERVED55                                        0x5abb
3121  #define mmDCRX_PHY_MACRO_CNTL_RESERVED56                                        0x5abc
3122  #define mmDCRX_PHY_MACRO_CNTL_RESERVED57                                        0x5abd
3123  #define mmDCRX_PHY_MACRO_CNTL_RESERVED58                                        0x5abe
3124  #define mmDCRX_PHY_MACRO_CNTL_RESERVED59                                        0x5abf
3125  #define mmDCRX_PHY_MACRO_CNTL_RESERVED60                                        0x5ac0
3126  #define mmDCRX_PHY_MACRO_CNTL_RESERVED61                                        0x5ac1
3127  #define mmDCRX_PHY_MACRO_CNTL_RESERVED62                                        0x5ac2
3128  #define mmDCRX_PHY_MACRO_CNTL_RESERVED63                                        0x5ac3
3129  #define mmDCRX_PHY_MACRO_CNTL_RESERVED64                                        0x5ac4
3130  #define mmDCRX_PHY_MACRO_CNTL_RESERVED65                                        0x5ac5
3131  #define mmDCRX_PHY_MACRO_CNTL_RESERVED66                                        0x5ac6
3132  #define mmDCRX_PHY_MACRO_CNTL_RESERVED67                                        0x5ac7
3133  #define mmDCRX_PHY_MACRO_CNTL_RESERVED68                                        0x5ac8
3134  #define mmDCRX_PHY_MACRO_CNTL_RESERVED69                                        0x5ac9
3135  #define mmDCRX_PHY_MACRO_CNTL_RESERVED70                                        0x5aca
3136  #define mmDCRX_PHY_MACRO_CNTL_RESERVED71                                        0x5acb
3137  #define mmDCRX_PHY_MACRO_CNTL_RESERVED72                                        0x5acc
3138  #define mmDCRX_PHY_MACRO_CNTL_RESERVED73                                        0x5acd
3139  #define mmDCRX_PHY_MACRO_CNTL_RESERVED74                                        0x5ace
3140  #define mmDCRX_PHY_MACRO_CNTL_RESERVED75                                        0x5acf
3141  #define mmDCRX_PHY_MACRO_CNTL_RESERVED76                                        0x5ad0
3142  #define mmDCRX_PHY_MACRO_CNTL_RESERVED77                                        0x5ad1
3143  #define mmDCRX_PHY_MACRO_CNTL_RESERVED78                                        0x5ad2
3144  #define mmDCRX_PHY_MACRO_CNTL_RESERVED79                                        0x5ad3
3145  #define mmDCRX_PHY_MACRO_CNTL_RESERVED80                                        0x5ad4
3146  #define mmDCRX_PHY_MACRO_CNTL_RESERVED81                                        0x5ad5
3147  #define mmDCRX_PHY_MACRO_CNTL_RESERVED82                                        0x5ad6
3148  #define mmDCRX_PHY_MACRO_CNTL_RESERVED83                                        0x5ad7
3149  #define mmDCRX_PHY_MACRO_CNTL_RESERVED84                                        0x5ad8
3150  #define mmDCRX_PHY_MACRO_CNTL_RESERVED85                                        0x5ad9
3151  #define mmDCRX_PHY_MACRO_CNTL_RESERVED86                                        0x5ada
3152  #define mmDCRX_PHY_MACRO_CNTL_RESERVED87                                        0x5adb
3153  #define mmDCRX_PHY_MACRO_CNTL_RESERVED88                                        0x5adc
3154  #define mmDCRX_PHY_MACRO_CNTL_RESERVED89                                        0x5add
3155  #define mmDCRX_PHY_MACRO_CNTL_RESERVED90                                        0x5ade
3156  #define mmDCRX_PHY_MACRO_CNTL_RESERVED91                                        0x5adf
3157  #define mmDCRX_PHY_MACRO_CNTL_RESERVED92                                        0x5ae0
3158  #define mmDCRX_PHY_MACRO_CNTL_RESERVED93                                        0x5ae1
3159  #define mmDCRX_PHY_MACRO_CNTL_RESERVED94                                        0x5ae2
3160  #define mmDCRX_PHY_MACRO_CNTL_RESERVED95                                        0x5ae3
3161  #define mmDCRX_PHY_MACRO_CNTL_RESERVED96                                        0x5ae4
3162  #define mmDCRX_PHY_MACRO_CNTL_RESERVED97                                        0x5ae5
3163  #define mmDCRX_PHY_MACRO_CNTL_RESERVED98                                        0x5ae6
3164  #define mmDCRX_PHY_MACRO_CNTL_RESERVED99                                        0x5ae7
3165  #define mmDCRX_PHY_MACRO_CNTL_RESERVED100                                       0x5ae8
3166  #define mmDCRX_PHY_MACRO_CNTL_RESERVED101                                       0x5ae9
3167  #define mmDCRX_PHY_MACRO_CNTL_RESERVED102                                       0x5aea
3168  #define mmDCRX_PHY_MACRO_CNTL_RESERVED103                                       0x5aeb
3169  #define mmDCRX_PHY_MACRO_CNTL_RESERVED104                                       0x5aec
3170  #define mmDCRX_PHY_MACRO_CNTL_RESERVED105                                       0x5aed
3171  #define mmDCRX_PHY_MACRO_CNTL_RESERVED106                                       0x5aee
3172  #define mmDCRX_PHY_MACRO_CNTL_RESERVED107                                       0x5aef
3173  #define mmDCRX_PHY_MACRO_CNTL_RESERVED108                                       0x5af0
3174  #define mmDCRX_PHY_MACRO_CNTL_RESERVED109                                       0x5af1
3175  #define mmDCRX_PHY_MACRO_CNTL_RESERVED110                                       0x5af2
3176  #define mmDCRX_PHY_MACRO_CNTL_RESERVED111                                       0x5af3
3177  #define mmDCRX_PHY_MACRO_CNTL_RESERVED112                                       0x5af4
3178  #define mmDCRX_PHY_MACRO_CNTL_RESERVED113                                       0x5af5
3179  #define mmDCRX_PHY_MACRO_CNTL_RESERVED114                                       0x5af6
3180  #define mmDCRX_PHY_MACRO_CNTL_RESERVED115                                       0x5af7
3181  #define mmDCRX_PHY_MACRO_CNTL_RESERVED116                                       0x5af8
3182  #define mmDCRX_PHY_MACRO_CNTL_RESERVED117                                       0x5af9
3183  #define mmDCRX_PHY_MACRO_CNTL_RESERVED118                                       0x5afa
3184  #define mmDCRX_PHY_MACRO_CNTL_RESERVED119                                       0x5afb
3185  #define mmDCRX_PHY_MACRO_CNTL_RESERVED120                                       0x5afc
3186  #define mmDCRX_PHY_MACRO_CNTL_RESERVED121                                       0x5afd
3187  #define mmDCRX_PHY_MACRO_CNTL_RESERVED122                                       0x5afe
3188  #define mmDCRX_PHY_MACRO_CNTL_RESERVED123                                       0x5aff
3189  #define mmDCRX_PHY_MACRO_CNTL_RESERVED124                                       0x5b00
3190  #define mmDCRX_PHY_MACRO_CNTL_RESERVED125                                       0x5b01
3191  #define mmDCRX_PHY_MACRO_CNTL_RESERVED126                                       0x5b02
3192  #define mmDCRX_PHY_MACRO_CNTL_RESERVED127                                       0x5b03
3193  #define mmDCRX_PHY_MACRO_CNTL_RESERVED128                                       0x5b04
3194  #define mmDCRX_PHY_MACRO_CNTL_RESERVED129                                       0x5b05
3195  #define mmDCRX_PHY_MACRO_CNTL_RESERVED130                                       0x5b06
3196  #define mmDCRX_PHY_MACRO_CNTL_RESERVED131                                       0x5b07
3197  #define mmDCRX_PHY_MACRO_CNTL_RESERVED132                                       0x5b08
3198  #define mmDCRX_PHY_MACRO_CNTL_RESERVED133                                       0x5b09
3199  #define mmDCRX_PHY_MACRO_CNTL_RESERVED134                                       0x5b0a
3200  #define mmDCRX_PHY_MACRO_CNTL_RESERVED135                                       0x5b0b
3201  #define mmDCRX_PHY_MACRO_CNTL_RESERVED136                                       0x5b0c
3202  #define mmDCRX_PHY_MACRO_CNTL_RESERVED137                                       0x5b0d
3203  #define mmDCRX_PHY_MACRO_CNTL_RESERVED138                                       0x5b0e
3204  #define mmDCRX_PHY_MACRO_CNTL_RESERVED139                                       0x5b0f
3205  #define mmDCRX_PHY_MACRO_CNTL_RESERVED140                                       0x5b10
3206  #define mmDCRX_PHY_MACRO_CNTL_RESERVED141                                       0x5b11
3207  #define mmDCRX_PHY_MACRO_CNTL_RESERVED142                                       0x5b12
3208  #define mmDCRX_PHY_MACRO_CNTL_RESERVED143                                       0x5b13
3209  #define mmDCRX_PHY_MACRO_CNTL_RESERVED144                                       0x5b14
3210  #define mmDCRX_PHY_MACRO_CNTL_RESERVED145                                       0x5b15
3211  #define mmDCRX_PHY_MACRO_CNTL_RESERVED146                                       0x5b16
3212  #define mmDCRX_PHY_MACRO_CNTL_RESERVED147                                       0x5b17
3213  #define mmDCRX_PHY_MACRO_CNTL_RESERVED148                                       0x5b18
3214  #define mmDCRX_PHY_MACRO_CNTL_RESERVED149                                       0x5b19
3215  #define mmDCRX_PHY_MACRO_CNTL_RESERVED150                                       0x5b1a
3216  #define mmDCRX_PHY_MACRO_CNTL_RESERVED151                                       0x5b1b
3217  #define mmDCRX_PHY_MACRO_CNTL_RESERVED152                                       0x5b1c
3218  #define mmDCRX_PHY_MACRO_CNTL_RESERVED153                                       0x5b1d
3219  #define mmDCRX_PHY_MACRO_CNTL_RESERVED154                                       0x5b1e
3220  #define mmDCRX_PHY_MACRO_CNTL_RESERVED155                                       0x5b1f
3221  #define mmDCRX_PHY_MACRO_CNTL_RESERVED156                                       0x5b20
3222  #define mmDCRX_PHY_MACRO_CNTL_RESERVED157                                       0x5b21
3223  #define mmDCRX_PHY_MACRO_CNTL_RESERVED158                                       0x5b22
3224  #define mmDCRX_PHY_MACRO_CNTL_RESERVED159                                       0x5b23
3225  #define mmDCRX_PHY_MACRO_CNTL_RESERVED160                                       0x5b24
3226  #define mmDCRX_PHY_MACRO_CNTL_RESERVED161                                       0x5b25
3227  #define mmDCRX_PHY_MACRO_CNTL_RESERVED162                                       0x5b26
3228  #define mmDCRX_PHY_MACRO_CNTL_RESERVED163                                       0x5b27
3229  #define mmDCRX_PHY_MACRO_CNTL_RESERVED164                                       0x5b28
3230  #define mmDCRX_PHY_MACRO_CNTL_RESERVED165                                       0x5b29
3231  #define mmDCRX_PHY_MACRO_CNTL_RESERVED166                                       0x5b2a
3232  #define mmDCRX_PHY_MACRO_CNTL_RESERVED167                                       0x5b2b
3233  #define mmDCRX_PHY_MACRO_CNTL_RESERVED168                                       0x5b2c
3234  #define mmDCRX_PHY_MACRO_CNTL_RESERVED169                                       0x5b2d
3235  #define mmDCRX_PHY_MACRO_CNTL_RESERVED170                                       0x5b2e
3236  #define mmDCRX_PHY_MACRO_CNTL_RESERVED171                                       0x5b2f
3237  #define mmDCRX_PHY_MACRO_CNTL_RESERVED172                                       0x5b30
3238  #define mmDCRX_PHY_MACRO_CNTL_RESERVED173                                       0x5b31
3239  #define mmDCRX_PHY_MACRO_CNTL_RESERVED174                                       0x5b32
3240  #define mmDCRX_PHY_MACRO_CNTL_RESERVED175                                       0x5b33
3241  #define mmDCRX_PHY_MACRO_CNTL_RESERVED176                                       0x5b34
3242  #define mmDCRX_PHY_MACRO_CNTL_RESERVED177                                       0x5b35
3243  #define mmDCRX_PHY_MACRO_CNTL_RESERVED178                                       0x5b36
3244  #define mmDCRX_PHY_MACRO_CNTL_RESERVED179                                       0x5b37
3245  #define mmDCRX_PHY_MACRO_CNTL_RESERVED180                                       0x5b38
3246  #define mmDCRX_PHY_MACRO_CNTL_RESERVED181                                       0x5b39
3247  #define mmDCRX_PHY_MACRO_CNTL_RESERVED182                                       0x5b3a
3248  #define mmDCRX_PHY_MACRO_CNTL_RESERVED183                                       0x5b3b
3249  #define mmDCRX_PHY_MACRO_CNTL_RESERVED184                                       0x5b3c
3250  #define mmDCRX_PHY_MACRO_CNTL_RESERVED185                                       0x5b3d
3251  #define mmDCRX_PHY_MACRO_CNTL_RESERVED186                                       0x5b3e
3252  #define mmDCRX_PHY_MACRO_CNTL_RESERVED187                                       0x5b3f
3253  #define mmDCRX_PHY_MACRO_CNTL_RESERVED188                                       0x5b40
3254  #define mmDCRX_PHY_MACRO_CNTL_RESERVED189                                       0x5b41
3255  #define mmDCRX_PHY_MACRO_CNTL_RESERVED190                                       0x5b42
3256  #define mmDCRX_PHY_MACRO_CNTL_RESERVED191                                       0x5b43
3257  #define mmDCRX_PHY_MACRO_CNTL_RESERVED192                                       0x5b44
3258  #define mmDCRX_PHY_MACRO_CNTL_RESERVED193                                       0x5b45
3259  #define mmDCRX_PHY_MACRO_CNTL_RESERVED194                                       0x5b46
3260  #define mmDCRX_PHY_MACRO_CNTL_RESERVED195                                       0x5b47
3261  #define mmDCRX_PHY_MACRO_CNTL_RESERVED196                                       0x5b48
3262  #define mmDCRX_PHY_MACRO_CNTL_RESERVED197                                       0x5b49
3263  #define mmDCRX_PHY_MACRO_CNTL_RESERVED198                                       0x5b4a
3264  #define mmDCRX_PHY_MACRO_CNTL_RESERVED199                                       0x5b4b
3265  #define mmDCRX_PHY_MACRO_CNTL_RESERVED200                                       0x5b4c
3266  #define mmDCRX_PHY_MACRO_CNTL_RESERVED201                                       0x5b4d
3267  #define mmDCRX_PHY_MACRO_CNTL_RESERVED202                                       0x5b4e
3268  #define mmDCRX_PHY_MACRO_CNTL_RESERVED203                                       0x5b4f
3269  #define mmDCRX_PHY_MACRO_CNTL_RESERVED204                                       0x5b50
3270  #define mmDCRX_PHY_MACRO_CNTL_RESERVED205                                       0x5b51
3271  #define mmDCRX_PHY_MACRO_CNTL_RESERVED206                                       0x5b52
3272  #define mmDCRX_PHY_MACRO_CNTL_RESERVED207                                       0x5b53
3273  #define mmDCRX_PHY_MACRO_CNTL_RESERVED208                                       0x5b54
3274  #define mmDCRX_PHY_MACRO_CNTL_RESERVED209                                       0x5b55
3275  #define mmDCRX_PHY_MACRO_CNTL_RESERVED210                                       0x5b56
3276  #define mmDCRX_PHY_MACRO_CNTL_RESERVED211                                       0x5b57
3277  #define mmDCRX_PHY_MACRO_CNTL_RESERVED212                                       0x5b58
3278  #define mmDCRX_PHY_MACRO_CNTL_RESERVED213                                       0x5b59
3279  #define mmDCRX_PHY_MACRO_CNTL_RESERVED214                                       0x5b5a
3280  #define mmDCRX_PHY_MACRO_CNTL_RESERVED215                                       0x5b5b
3281  #define mmDCRX_PHY_MACRO_CNTL_RESERVED216                                       0x5b5c
3282  #define mmDCRX_PHY_MACRO_CNTL_RESERVED217                                       0x5b5d
3283  #define mmDCRX_PHY_MACRO_CNTL_RESERVED218                                       0x5b5e
3284  #define mmDCRX_PHY_MACRO_CNTL_RESERVED219                                       0x5b5f
3285  #define mmDCRX_PHY_MACRO_CNTL_RESERVED220                                       0x5b60
3286  #define mmDCRX_PHY_MACRO_CNTL_RESERVED221                                       0x5b61
3287  #define mmDCRX_PHY_MACRO_CNTL_RESERVED222                                       0x5b62
3288  #define mmDCRX_PHY_MACRO_CNTL_RESERVED223                                       0x5b63
3289  #define mmDCRX_PHY_MACRO_CNTL_RESERVED224                                       0x5b64
3290  #define mmDCRX_PHY_MACRO_CNTL_RESERVED225                                       0x5b65
3291  #define mmDCRX_PHY_MACRO_CNTL_RESERVED226                                       0x5b66
3292  #define mmDCRX_PHY_MACRO_CNTL_RESERVED227                                       0x5b67
3293  #define mmDCRX_PHY_MACRO_CNTL_RESERVED228                                       0x5b68
3294  #define mmDCRX_PHY_MACRO_CNTL_RESERVED229                                       0x5b69
3295  #define mmDCRX_PHY_MACRO_CNTL_RESERVED230                                       0x5b6a
3296  #define mmDCRX_PHY_MACRO_CNTL_RESERVED231                                       0x5b6b
3297  #define mmDCRX_PHY_MACRO_CNTL_RESERVED232                                       0x5b6c
3298  #define mmDCRX_PHY_MACRO_CNTL_RESERVED233                                       0x5b6d
3299  #define mmDCRX_PHY_MACRO_CNTL_RESERVED234                                       0x5b6e
3300  #define mmDCRX_PHY_MACRO_CNTL_RESERVED235                                       0x5b6f
3301  #define mmDCRX_PHY_MACRO_CNTL_RESERVED236                                       0x5b70
3302  #define mmDCRX_PHY_MACRO_CNTL_RESERVED237                                       0x5b71
3303  #define mmDCRX_PHY_MACRO_CNTL_RESERVED238                                       0x5b72
3304  #define mmDCRX_PHY_MACRO_CNTL_RESERVED239                                       0x5b73
3305  #define mmDCRX_PHY_MACRO_CNTL_RESERVED240                                       0x5b74
3306  #define mmDCRX_PHY_MACRO_CNTL_RESERVED241                                       0x5b75
3307  #define mmDCRX_PHY_MACRO_CNTL_RESERVED242                                       0x5b76
3308  #define mmDCRX_PHY_MACRO_CNTL_RESERVED243                                       0x5b77
3309  #define mmDCRX_PHY_MACRO_CNTL_RESERVED244                                       0x5b78
3310  #define mmDCRX_PHY_MACRO_CNTL_RESERVED245                                       0x5b79
3311  #define mmDCRX_PHY_MACRO_CNTL_RESERVED246                                       0x5b7a
3312  #define mmDCRX_PHY_MACRO_CNTL_RESERVED247                                       0x5b7b
3313  #define mmDCRX_PHY_MACRO_CNTL_RESERVED248                                       0x5b7c
3314  #define mmDCRX_PHY_MACRO_CNTL_RESERVED249                                       0x5b7d
3315  #define mmDCRX_PHY_MACRO_CNTL_RESERVED250                                       0x5b7e
3316  #define mmDCRX_PHY_MACRO_CNTL_RESERVED251                                       0x5b7f
3317  #define mmDCRX_PHY_MACRO_CNTL_RESERVED252                                       0x5b80
3318  #define mmDCRX_PHY_MACRO_CNTL_RESERVED253                                       0x5b81
3319  #define mmDCRX_PHY_MACRO_CNTL_RESERVED254                                       0x5b82
3320  #define mmDCRX_PHY_MACRO_CNTL_RESERVED255                                       0x5b83
3321  #define mmDCRX_PHY_MACRO_CNTL_RESERVED256                                       0x5b84
3322  #define mmDCRX_PHY_MACRO_CNTL_RESERVED257                                       0x5b85
3323  #define mmDCRX_PHY_MACRO_CNTL_RESERVED258                                       0x5b86
3324  #define mmDCRX_PHY_MACRO_CNTL_RESERVED259                                       0x5b87
3325  #define mmDCRX_PHY_MACRO_CNTL_RESERVED260                                       0x5b88
3326  #define mmDCRX_PHY_MACRO_CNTL_RESERVED261                                       0x5b89
3327  #define mmDCRX_PHY_MACRO_CNTL_RESERVED262                                       0x5b8a
3328  #define mmDCRX_PHY_MACRO_CNTL_RESERVED263                                       0x5b8b
3329  #define mmDCRX_PHY_MACRO_CNTL_RESERVED264                                       0x5b8c
3330  #define mmDCRX_PHY_MACRO_CNTL_RESERVED265                                       0x5b8d
3331  #define mmDCRX_PHY_MACRO_CNTL_RESERVED266                                       0x5b8e
3332  #define mmDCRX_PHY_MACRO_CNTL_RESERVED267                                       0x5b8f
3333  #define mmDCRX_PHY_MACRO_CNTL_RESERVED268                                       0x5b90
3334  #define mmDCRX_PHY_MACRO_CNTL_RESERVED269                                       0x5b91
3335  #define mmDCRX_PHY_MACRO_CNTL_RESERVED270                                       0x5b92
3336  #define mmDCRX_PHY_MACRO_CNTL_RESERVED271                                       0x5b93
3337  #define mmDCRX_PHY_MACRO_CNTL_RESERVED272                                       0x5b94
3338  #define mmDCRX_PHY_MACRO_CNTL_RESERVED273                                       0x5b95
3339  #define mmDCRX_PHY_MACRO_CNTL_RESERVED274                                       0x5b96
3340  #define mmDCRX_PHY_MACRO_CNTL_RESERVED275                                       0x5b97
3341  #define mmDCRX_PHY_MACRO_CNTL_RESERVED276                                       0x5b98
3342  #define mmDCRX_PHY_MACRO_CNTL_RESERVED277                                       0x5b99
3343  #define mmDCRX_PHY_MACRO_CNTL_RESERVED278                                       0x5b9a
3344  #define mmDCRX_PHY_MACRO_CNTL_RESERVED279                                       0x5b9b
3345  #define mmDCRX_PHY_MACRO_CNTL_RESERVED280                                       0x5b9c
3346  #define mmDCRX_PHY_MACRO_CNTL_RESERVED281                                       0x5b9d
3347  #define mmDCRX_PHY_MACRO_CNTL_RESERVED282                                       0x5b9e
3348  #define mmDCRX_PHY_MACRO_CNTL_RESERVED283                                       0x5b9f
3349  #define mmDCRX_PHY_MACRO_CNTL_RESERVED284                                       0x5ba0
3350  #define mmDCRX_PHY_MACRO_CNTL_RESERVED285                                       0x5ba1
3351  #define mmDCRX_PHY_MACRO_CNTL_RESERVED286                                       0x5ba2
3352  #define mmDCRX_PHY_MACRO_CNTL_RESERVED287                                       0x5ba3
3353  #define mmDCRX_PHY_MACRO_CNTL_RESERVED288                                       0x5ba4
3354  #define mmDCRX_PHY_MACRO_CNTL_RESERVED289                                       0x5ba5
3355  #define mmDCRX_PHY_MACRO_CNTL_RESERVED290                                       0x5ba6
3356  #define mmDCRX_PHY_MACRO_CNTL_RESERVED291                                       0x5ba7
3357  #define mmDCRX_PHY_MACRO_CNTL_RESERVED292                                       0x5ba8
3358  #define mmDCRX_PHY_MACRO_CNTL_RESERVED293                                       0x5ba9
3359  #define mmDCRX_PHY_MACRO_CNTL_RESERVED294                                       0x5baa
3360  #define mmDCRX_PHY_MACRO_CNTL_RESERVED295                                       0x5bab
3361  #define mmDCRX_PHY_MACRO_CNTL_RESERVED296                                       0x5bac
3362  #define mmDCRX_PHY_MACRO_CNTL_RESERVED297                                       0x5bad
3363  #define mmDCRX_PHY_MACRO_CNTL_RESERVED298                                       0x5bae
3364  #define mmDCRX_PHY_MACRO_CNTL_RESERVED299                                       0x5baf
3365  #define mmDCRX_PHY_MACRO_CNTL_RESERVED300                                       0x5bb0
3366  #define mmDCRX_PHY_MACRO_CNTL_RESERVED301                                       0x5bb1
3367  #define mmDCRX_PHY_MACRO_CNTL_RESERVED302                                       0x5bb2
3368  #define mmDCRX_PHY_MACRO_CNTL_RESERVED303                                       0x5bb3
3369  #define mmDCRX_PHY_MACRO_CNTL_RESERVED304                                       0x5bb4
3370  #define mmDCRX_PHY_MACRO_CNTL_RESERVED305                                       0x5bb5
3371  #define mmDCRX_PHY_MACRO_CNTL_RESERVED306                                       0x5bb6
3372  #define mmDCRX_PHY_MACRO_CNTL_RESERVED307                                       0x5bb7
3373  #define mmDCRX_PHY_MACRO_CNTL_RESERVED308                                       0x5bb8
3374  #define mmDCRX_PHY_MACRO_CNTL_RESERVED309                                       0x5bb9
3375  #define mmDCRX_PHY_MACRO_CNTL_RESERVED310                                       0x5bba
3376  #define mmDCRX_PHY_MACRO_CNTL_RESERVED311                                       0x5bbb
3377  #define mmDCRX_PHY_MACRO_CNTL_RESERVED312                                       0x5bbc
3378  #define mmDCRX_PHY_MACRO_CNTL_RESERVED313                                       0x5bbd
3379  #define mmDCRX_PHY_MACRO_CNTL_RESERVED314                                       0x5bbe
3380  #define mmDCRX_PHY_MACRO_CNTL_RESERVED315                                       0x5bbf
3381  #define mmDCRX_PHY_MACRO_CNTL_RESERVED316                                       0x5bc0
3382  #define mmDCRX_PHY_MACRO_CNTL_RESERVED317                                       0x5bc1
3383  #define mmDCRX_PHY_MACRO_CNTL_RESERVED318                                       0x5bc2
3384  #define mmDCRX_PHY_MACRO_CNTL_RESERVED319                                       0x5bc3
3385  #define mmDCRX_PHY_MACRO_CNTL_RESERVED320                                       0x5bc4
3386  #define mmDCRX_PHY_MACRO_CNTL_RESERVED321                                       0x5bc5
3387  #define mmDCRX_PHY_MACRO_CNTL_RESERVED322                                       0x5bc6
3388  #define mmDCRX_PHY_MACRO_CNTL_RESERVED323                                       0x5bc7
3389  #define mmDCRX_PHY_MACRO_CNTL_RESERVED324                                       0x5bc8
3390  #define mmDCRX_PHY_MACRO_CNTL_RESERVED325                                       0x5bc9
3391  #define mmDCRX_PHY_MACRO_CNTL_RESERVED326                                       0x5bca
3392  #define mmDCRX_PHY_MACRO_CNTL_RESERVED327                                       0x5bcb
3393  #define mmDCRX_PHY_MACRO_CNTL_RESERVED328                                       0x5bcc
3394  #define mmDCRX_PHY_MACRO_CNTL_RESERVED329                                       0x5bcd
3395  #define mmDCRX_PHY_MACRO_CNTL_RESERVED330                                       0x5bce
3396  #define mmDCRX_PHY_MACRO_CNTL_RESERVED331                                       0x5bcf
3397  #define mmDCRX_PHY_MACRO_CNTL_RESERVED332                                       0x5bd0
3398  #define mmDCRX_PHY_MACRO_CNTL_RESERVED333                                       0x5bd1
3399  #define mmDCRX_PHY_MACRO_CNTL_RESERVED334                                       0x5bd2
3400  #define mmDCRX_PHY_MACRO_CNTL_RESERVED335                                       0x5bd3
3401  #define mmDCRX_PHY_MACRO_CNTL_RESERVED336                                       0x5bd4
3402  #define mmDCRX_PHY_MACRO_CNTL_RESERVED337                                       0x5bd5
3403  #define mmDCRX_PHY_MACRO_CNTL_RESERVED338                                       0x5bd6
3404  #define mmDCRX_PHY_MACRO_CNTL_RESERVED339                                       0x5bd7
3405  #define mmDCRX_PHY_MACRO_CNTL_RESERVED340                                       0x5bd8
3406  #define mmDCRX_PHY_MACRO_CNTL_RESERVED341                                       0x5bd9
3407  #define mmDCRX_PHY_MACRO_CNTL_RESERVED342                                       0x5bda
3408  #define mmDCRX_PHY_MACRO_CNTL_RESERVED343                                       0x5bdb
3409  #define mmDCRX_PHY_MACRO_CNTL_RESERVED344                                       0x5bdc
3410  #define mmDCRX_PHY_MACRO_CNTL_RESERVED345                                       0x5bdd
3411  #define mmDCRX_PHY_MACRO_CNTL_RESERVED346                                       0x5bde
3412  #define mmDCRX_PHY_MACRO_CNTL_RESERVED347                                       0x5bdf
3413  #define mmDCRX_PHY_MACRO_CNTL_RESERVED348                                       0x5be0
3414  #define mmDCRX_PHY_MACRO_CNTL_RESERVED349                                       0x5be1
3415  #define mmDCRX_PHY_MACRO_CNTL_RESERVED350                                       0x5be2
3416  #define mmDCRX_PHY_MACRO_CNTL_RESERVED351                                       0x5be3
3417  #define mmDCRX_PHY_MACRO_CNTL_RESERVED352                                       0x5be4
3418  #define mmDCRX_PHY_MACRO_CNTL_RESERVED353                                       0x5be5
3419  #define mmDCRX_PHY_MACRO_CNTL_RESERVED354                                       0x5be6
3420  #define mmDCRX_PHY_MACRO_CNTL_RESERVED355                                       0x5be7
3421  #define mmDCRX_PHY_MACRO_CNTL_RESERVED356                                       0x5be8
3422  #define mmDCRX_PHY_MACRO_CNTL_RESERVED357                                       0x5be9
3423  #define mmDCRX_PHY_MACRO_CNTL_RESERVED358                                       0x5bea
3424  #define mmDCRX_PHY_MACRO_CNTL_RESERVED359                                       0x5beb
3425  #define mmDCRX_PHY_MACRO_CNTL_RESERVED360                                       0x5bec
3426  #define mmDCRX_PHY_MACRO_CNTL_RESERVED361                                       0x5bed
3427  #define mmDCRX_PHY_MACRO_CNTL_RESERVED362                                       0x5bee
3428  #define mmDCRX_PHY_MACRO_CNTL_RESERVED363                                       0x5bef
3429  #define mmDCRX_PHY_MACRO_CNTL_RESERVED364                                       0x5bf0
3430  #define mmDCRX_PHY_MACRO_CNTL_RESERVED365                                       0x5bf1
3431  #define mmDCRX_PHY_MACRO_CNTL_RESERVED366                                       0x5bf2
3432  #define mmDCRX_PHY_MACRO_CNTL_RESERVED367                                       0x5bf3
3433  #define mmDCRX_PHY_MACRO_CNTL_RESERVED368                                       0x5bf4
3434  #define mmDCRX_PHY_MACRO_CNTL_RESERVED369                                       0x5bf5
3435  #define mmDCRX_PHY_MACRO_CNTL_RESERVED370                                       0x5bf6
3436  #define mmDCRX_PHY_MACRO_CNTL_RESERVED371                                       0x5bf7
3437  #define mmDCRX_PHY_MACRO_CNTL_RESERVED372                                       0x5bf8
3438  #define mmDCRX_PHY_MACRO_CNTL_RESERVED373                                       0x5bf9
3439  #define mmDCRX_PHY_MACRO_CNTL_RESERVED374                                       0x5bfa
3440  #define mmDCRX_PHY_MACRO_CNTL_RESERVED375                                       0x5bfb
3441  #define mmDCRX_PHY_MACRO_CNTL_RESERVED376                                       0x5bfc
3442  #define mmDCRX_PHY_MACRO_CNTL_RESERVED377                                       0x5bfd
3443  #define mmDCRX_PHY_MACRO_CNTL_RESERVED378                                       0x5bfe
3444  #define mmDCRX_PHY_MACRO_CNTL_RESERVED379                                       0x5bff
3445  #define mmDPHY_MACRO_CNTL_RESERVED0                                             0x5d98
3446  #define mmDPHY_MACRO_CNTL_RESERVED1                                             0x5d99
3447  #define mmDPHY_MACRO_CNTL_RESERVED2                                             0x5d9a
3448  #define mmDPHY_MACRO_CNTL_RESERVED3                                             0x5d9b
3449  #define mmDPHY_MACRO_CNTL_RESERVED4                                             0x5d9c
3450  #define mmDPHY_MACRO_CNTL_RESERVED5                                             0x5d9d
3451  #define mmDPHY_MACRO_CNTL_RESERVED6                                             0x5d9e
3452  #define mmDPHY_MACRO_CNTL_RESERVED7                                             0x5d9f
3453  #define mmDPHY_MACRO_CNTL_RESERVED8                                             0x5da0
3454  #define mmDPHY_MACRO_CNTL_RESERVED9                                             0x5da1
3455  #define mmDPHY_MACRO_CNTL_RESERVED10                                            0x5da2
3456  #define mmDPHY_MACRO_CNTL_RESERVED11                                            0x5da3
3457  #define mmDPHY_MACRO_CNTL_RESERVED12                                            0x5da4
3458  #define mmDPHY_MACRO_CNTL_RESERVED13                                            0x5da5
3459  #define mmDPHY_MACRO_CNTL_RESERVED14                                            0x5da6
3460  #define mmDPHY_MACRO_CNTL_RESERVED15                                            0x5da7
3461  #define mmDPHY_MACRO_CNTL_RESERVED16                                            0x5da8
3462  #define mmDPHY_MACRO_CNTL_RESERVED17                                            0x5da9
3463  #define mmDPHY_MACRO_CNTL_RESERVED18                                            0x5daa
3464  #define mmDPHY_MACRO_CNTL_RESERVED19                                            0x5dab
3465  #define mmDPHY_MACRO_CNTL_RESERVED20                                            0x5dac
3466  #define mmDPHY_MACRO_CNTL_RESERVED21                                            0x5dad
3467  #define mmDPHY_MACRO_CNTL_RESERVED22                                            0x5dae
3468  #define mmDPHY_MACRO_CNTL_RESERVED23                                            0x5daf
3469  #define mmDPHY_MACRO_CNTL_RESERVED24                                            0x5db0
3470  #define mmDPHY_MACRO_CNTL_RESERVED25                                            0x5db1
3471  #define mmDPHY_MACRO_CNTL_RESERVED26                                            0x5db2
3472  #define mmDPHY_MACRO_CNTL_RESERVED27                                            0x5db3
3473  #define mmDPHY_MACRO_CNTL_RESERVED28                                            0x5db4
3474  #define mmDPHY_MACRO_CNTL_RESERVED29                                            0x5db5
3475  #define mmDPHY_MACRO_CNTL_RESERVED30                                            0x5db6
3476  #define mmDPHY_MACRO_CNTL_RESERVED31                                            0x5db7
3477  #define mmDPHY_MACRO_CNTL_RESERVED32                                            0x5db8
3478  #define mmDPHY_MACRO_CNTL_RESERVED33                                            0x5db9
3479  #define mmDPHY_MACRO_CNTL_RESERVED34                                            0x5dba
3480  #define mmDPHY_MACRO_CNTL_RESERVED35                                            0x5dbb
3481  #define mmDPHY_MACRO_CNTL_RESERVED36                                            0x5dbc
3482  #define mmDPHY_MACRO_CNTL_RESERVED37                                            0x5dbd
3483  #define mmDPHY_MACRO_CNTL_RESERVED38                                            0x5dbe
3484  #define mmDPHY_MACRO_CNTL_RESERVED39                                            0x5dbf
3485  #define mmDPHY_MACRO_CNTL_RESERVED40                                            0x5dc0
3486  #define mmDPHY_MACRO_CNTL_RESERVED41                                            0x5dc1
3487  #define mmDPHY_MACRO_CNTL_RESERVED42                                            0x5dc2
3488  #define mmDPHY_MACRO_CNTL_RESERVED43                                            0x5dc3
3489  #define mmDPHY_MACRO_CNTL_RESERVED44                                            0x5dc4
3490  #define mmDPHY_MACRO_CNTL_RESERVED45                                            0x5dc5
3491  #define mmDPHY_MACRO_CNTL_RESERVED46                                            0x5dc6
3492  #define mmDPHY_MACRO_CNTL_RESERVED47                                            0x5dc7
3493  #define mmDPHY_MACRO_CNTL_RESERVED48                                            0x5dc8
3494  #define mmDPHY_MACRO_CNTL_RESERVED49                                            0x5dc9
3495  #define mmDPHY_MACRO_CNTL_RESERVED50                                            0x5dca
3496  #define mmDPHY_MACRO_CNTL_RESERVED51                                            0x5dcb
3497  #define mmDPHY_MACRO_CNTL_RESERVED52                                            0x5dcc
3498  #define mmDPHY_MACRO_CNTL_RESERVED53                                            0x5dcd
3499  #define mmDPHY_MACRO_CNTL_RESERVED54                                            0x5dce
3500  #define mmDPHY_MACRO_CNTL_RESERVED55                                            0x5dcf
3501  #define mmDPHY_MACRO_CNTL_RESERVED56                                            0x5dd0
3502  #define mmDPHY_MACRO_CNTL_RESERVED57                                            0x5dd1
3503  #define mmDPHY_MACRO_CNTL_RESERVED58                                            0x5dd2
3504  #define mmDPHY_MACRO_CNTL_RESERVED59                                            0x5dd3
3505  #define mmDPHY_MACRO_CNTL_RESERVED60                                            0x5dd4
3506  #define mmDPHY_MACRO_CNTL_RESERVED61                                            0x5dd5
3507  #define mmDPHY_MACRO_CNTL_RESERVED62                                            0x5dd6
3508  #define mmDPHY_MACRO_CNTL_RESERVED63                                            0x5dd7
3509  #define mmGRPH_ENABLE                                                           0x1a00
3510  #define mmDCP0_GRPH_ENABLE                                                      0x1a00
3511  #define mmDCP1_GRPH_ENABLE                                                      0x1c00
3512  #define mmDCP2_GRPH_ENABLE                                                      0x1e00
3513  #define mmDCP3_GRPH_ENABLE                                                      0x4000
3514  #define mmDCP4_GRPH_ENABLE                                                      0x4200
3515  #define mmDCP5_GRPH_ENABLE                                                      0x4400
3516  #define mmGRPH_CONTROL                                                          0x1a01
3517  #define mmDCP0_GRPH_CONTROL                                                     0x1a01
3518  #define mmDCP1_GRPH_CONTROL                                                     0x1c01
3519  #define mmDCP2_GRPH_CONTROL                                                     0x1e01
3520  #define mmDCP3_GRPH_CONTROL                                                     0x4001
3521  #define mmDCP4_GRPH_CONTROL                                                     0x4201
3522  #define mmDCP5_GRPH_CONTROL                                                     0x4401
3523  #define mmGRPH_LUT_10BIT_BYPASS                                                 0x1a02
3524  #define mmDCP0_GRPH_LUT_10BIT_BYPASS                                            0x1a02
3525  #define mmDCP1_GRPH_LUT_10BIT_BYPASS                                            0x1c02
3526  #define mmDCP2_GRPH_LUT_10BIT_BYPASS                                            0x1e02
3527  #define mmDCP3_GRPH_LUT_10BIT_BYPASS                                            0x4002
3528  #define mmDCP4_GRPH_LUT_10BIT_BYPASS                                            0x4202
3529  #define mmDCP5_GRPH_LUT_10BIT_BYPASS                                            0x4402
3530  #define mmGRPH_SWAP_CNTL                                                        0x1a03
3531  #define mmDCP0_GRPH_SWAP_CNTL                                                   0x1a03
3532  #define mmDCP1_GRPH_SWAP_CNTL                                                   0x1c03
3533  #define mmDCP2_GRPH_SWAP_CNTL                                                   0x1e03
3534  #define mmDCP3_GRPH_SWAP_CNTL                                                   0x4003
3535  #define mmDCP4_GRPH_SWAP_CNTL                                                   0x4203
3536  #define mmDCP5_GRPH_SWAP_CNTL                                                   0x4403
3537  #define mmGRPH_PRIMARY_SURFACE_ADDRESS                                          0x1a04
3538  #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1a04
3539  #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1c04
3540  #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x1e04
3541  #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4004
3542  #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4204
3543  #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                     0x4404
3544  #define mmGRPH_SECONDARY_SURFACE_ADDRESS                                        0x1a05
3545  #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1a05
3546  #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1c05
3547  #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x1e05
3548  #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4005
3549  #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4205
3550  #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                   0x4405
3551  #define mmGRPH_PITCH                                                            0x1a06
3552  #define mmDCP0_GRPH_PITCH                                                       0x1a06
3553  #define mmDCP1_GRPH_PITCH                                                       0x1c06
3554  #define mmDCP2_GRPH_PITCH                                                       0x1e06
3555  #define mmDCP3_GRPH_PITCH                                                       0x4006
3556  #define mmDCP4_GRPH_PITCH                                                       0x4206
3557  #define mmDCP5_GRPH_PITCH                                                       0x4406
3558  #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                     0x1a07
3559  #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1a07
3560  #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1c07
3561  #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x1e07
3562  #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4007
3563  #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4207
3564  #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                0x4407
3565  #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                   0x1a08
3566  #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1a08
3567  #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1c08
3568  #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x1e08
3569  #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4008
3570  #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4208
3571  #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                              0x4408
3572  #define mmGRPH_SURFACE_OFFSET_X                                                 0x1a09
3573  #define mmDCP0_GRPH_SURFACE_OFFSET_X                                            0x1a09
3574  #define mmDCP1_GRPH_SURFACE_OFFSET_X                                            0x1c09
3575  #define mmDCP2_GRPH_SURFACE_OFFSET_X                                            0x1e09
3576  #define mmDCP3_GRPH_SURFACE_OFFSET_X                                            0x4009
3577  #define mmDCP4_GRPH_SURFACE_OFFSET_X                                            0x4209
3578  #define mmDCP5_GRPH_SURFACE_OFFSET_X                                            0x4409
3579  #define mmGRPH_SURFACE_OFFSET_Y                                                 0x1a0a
3580  #define mmDCP0_GRPH_SURFACE_OFFSET_Y                                            0x1a0a
3581  #define mmDCP1_GRPH_SURFACE_OFFSET_Y                                            0x1c0a
3582  #define mmDCP2_GRPH_SURFACE_OFFSET_Y                                            0x1e0a
3583  #define mmDCP3_GRPH_SURFACE_OFFSET_Y                                            0x400a
3584  #define mmDCP4_GRPH_SURFACE_OFFSET_Y                                            0x420a
3585  #define mmDCP5_GRPH_SURFACE_OFFSET_Y                                            0x440a
3586  #define mmGRPH_X_START                                                          0x1a0b
3587  #define mmDCP0_GRPH_X_START                                                     0x1a0b
3588  #define mmDCP1_GRPH_X_START                                                     0x1c0b
3589  #define mmDCP2_GRPH_X_START                                                     0x1e0b
3590  #define mmDCP3_GRPH_X_START                                                     0x400b
3591  #define mmDCP4_GRPH_X_START                                                     0x420b
3592  #define mmDCP5_GRPH_X_START                                                     0x440b
3593  #define mmGRPH_Y_START                                                          0x1a0c
3594  #define mmDCP0_GRPH_Y_START                                                     0x1a0c
3595  #define mmDCP1_GRPH_Y_START                                                     0x1c0c
3596  #define mmDCP2_GRPH_Y_START                                                     0x1e0c
3597  #define mmDCP3_GRPH_Y_START                                                     0x400c
3598  #define mmDCP4_GRPH_Y_START                                                     0x420c
3599  #define mmDCP5_GRPH_Y_START                                                     0x440c
3600  #define mmGRPH_X_END                                                            0x1a0d
3601  #define mmDCP0_GRPH_X_END                                                       0x1a0d
3602  #define mmDCP1_GRPH_X_END                                                       0x1c0d
3603  #define mmDCP2_GRPH_X_END                                                       0x1e0d
3604  #define mmDCP3_GRPH_X_END                                                       0x400d
3605  #define mmDCP4_GRPH_X_END                                                       0x420d
3606  #define mmDCP5_GRPH_X_END                                                       0x440d
3607  #define mmGRPH_Y_END                                                            0x1a0e
3608  #define mmDCP0_GRPH_Y_END                                                       0x1a0e
3609  #define mmDCP1_GRPH_Y_END                                                       0x1c0e
3610  #define mmDCP2_GRPH_Y_END                                                       0x1e0e
3611  #define mmDCP3_GRPH_Y_END                                                       0x400e
3612  #define mmDCP4_GRPH_Y_END                                                       0x420e
3613  #define mmDCP5_GRPH_Y_END                                                       0x440e
3614  #define mmINPUT_GAMMA_CONTROL                                                   0x1a10
3615  #define mmDCP0_INPUT_GAMMA_CONTROL                                              0x1a10
3616  #define mmDCP1_INPUT_GAMMA_CONTROL                                              0x1c10
3617  #define mmDCP2_INPUT_GAMMA_CONTROL                                              0x1e10
3618  #define mmDCP3_INPUT_GAMMA_CONTROL                                              0x4010
3619  #define mmDCP4_INPUT_GAMMA_CONTROL                                              0x4210
3620  #define mmDCP5_INPUT_GAMMA_CONTROL                                              0x4410
3621  #define mmGRPH_UPDATE                                                           0x1a11
3622  #define mmDCP0_GRPH_UPDATE                                                      0x1a11
3623  #define mmDCP1_GRPH_UPDATE                                                      0x1c11
3624  #define mmDCP2_GRPH_UPDATE                                                      0x1e11
3625  #define mmDCP3_GRPH_UPDATE                                                      0x4011
3626  #define mmDCP4_GRPH_UPDATE                                                      0x4211
3627  #define mmDCP5_GRPH_UPDATE                                                      0x4411
3628  #define mmGRPH_FLIP_CONTROL                                                     0x1a12
3629  #define mmDCP0_GRPH_FLIP_CONTROL                                                0x1a12
3630  #define mmDCP1_GRPH_FLIP_CONTROL                                                0x1c12
3631  #define mmDCP2_GRPH_FLIP_CONTROL                                                0x1e12
3632  #define mmDCP3_GRPH_FLIP_CONTROL                                                0x4012
3633  #define mmDCP4_GRPH_FLIP_CONTROL                                                0x4212
3634  #define mmDCP5_GRPH_FLIP_CONTROL                                                0x4412
3635  #define mmGRPH_SURFACE_ADDRESS_INUSE                                            0x1a13
3636  #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                       0x1a13
3637  #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                       0x1c13
3638  #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                       0x1e13
3639  #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                       0x4013
3640  #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                       0x4213
3641  #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                       0x4413
3642  #define mmGRPH_DFQ_CONTROL                                                      0x1a14
3643  #define mmDCP0_GRPH_DFQ_CONTROL                                                 0x1a14
3644  #define mmDCP1_GRPH_DFQ_CONTROL                                                 0x1c14
3645  #define mmDCP2_GRPH_DFQ_CONTROL                                                 0x1e14
3646  #define mmDCP3_GRPH_DFQ_CONTROL                                                 0x4014
3647  #define mmDCP4_GRPH_DFQ_CONTROL                                                 0x4214
3648  #define mmDCP5_GRPH_DFQ_CONTROL                                                 0x4414
3649  #define mmGRPH_DFQ_STATUS                                                       0x1a15
3650  #define mmDCP0_GRPH_DFQ_STATUS                                                  0x1a15
3651  #define mmDCP1_GRPH_DFQ_STATUS                                                  0x1c15
3652  #define mmDCP2_GRPH_DFQ_STATUS                                                  0x1e15
3653  #define mmDCP3_GRPH_DFQ_STATUS                                                  0x4015
3654  #define mmDCP4_GRPH_DFQ_STATUS                                                  0x4215
3655  #define mmDCP5_GRPH_DFQ_STATUS                                                  0x4415
3656  #define mmGRPH_INTERRUPT_STATUS                                                 0x1a16
3657  #define mmDCP0_GRPH_INTERRUPT_STATUS                                            0x1a16
3658  #define mmDCP1_GRPH_INTERRUPT_STATUS                                            0x1c16
3659  #define mmDCP2_GRPH_INTERRUPT_STATUS                                            0x1e16
3660  #define mmDCP3_GRPH_INTERRUPT_STATUS                                            0x4016
3661  #define mmDCP4_GRPH_INTERRUPT_STATUS                                            0x4216
3662  #define mmDCP5_GRPH_INTERRUPT_STATUS                                            0x4416
3663  #define mmGRPH_INTERRUPT_CONTROL                                                0x1a17
3664  #define mmDCP0_GRPH_INTERRUPT_CONTROL                                           0x1a17
3665  #define mmDCP1_GRPH_INTERRUPT_CONTROL                                           0x1c17
3666  #define mmDCP2_GRPH_INTERRUPT_CONTROL                                           0x1e17
3667  #define mmDCP3_GRPH_INTERRUPT_CONTROL                                           0x4017
3668  #define mmDCP4_GRPH_INTERRUPT_CONTROL                                           0x4217
3669  #define mmDCP5_GRPH_INTERRUPT_CONTROL                                           0x4417
3670  #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE                                       0x1a18
3671  #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1a18
3672  #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1c18
3673  #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x1e18
3674  #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4018
3675  #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4218
3676  #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                  0x4418
3677  #define mmGRPH_COMPRESS_SURFACE_ADDRESS                                         0x1a19
3678  #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1a19
3679  #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1c19
3680  #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x1e19
3681  #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4019
3682  #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4219
3683  #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                    0x4419
3684  #define mmGRPH_COMPRESS_PITCH                                                   0x1a1a
3685  #define mmDCP0_GRPH_COMPRESS_PITCH                                              0x1a1a
3686  #define mmDCP1_GRPH_COMPRESS_PITCH                                              0x1c1a
3687  #define mmDCP2_GRPH_COMPRESS_PITCH                                              0x1e1a
3688  #define mmDCP3_GRPH_COMPRESS_PITCH                                              0x401a
3689  #define mmDCP4_GRPH_COMPRESS_PITCH                                              0x421a
3690  #define mmDCP5_GRPH_COMPRESS_PITCH                                              0x441a
3691  #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                    0x1a1b
3692  #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1a1b
3693  #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1c1b
3694  #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x1e1b
3695  #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x401b
3696  #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x421b
3697  #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                               0x441b
3698  #define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                   0x1a1c
3699  #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1a1c
3700  #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1c1c
3701  #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x1e1c
3702  #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x401c
3703  #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x421c
3704  #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                              0x441c
3705  #define mmPRESCALE_GRPH_CONTROL                                                 0x1a2d
3706  #define mmDCP0_PRESCALE_GRPH_CONTROL                                            0x1a2d
3707  #define mmDCP1_PRESCALE_GRPH_CONTROL                                            0x1c2d
3708  #define mmDCP2_PRESCALE_GRPH_CONTROL                                            0x1e2d
3709  #define mmDCP3_PRESCALE_GRPH_CONTROL                                            0x402d
3710  #define mmDCP4_PRESCALE_GRPH_CONTROL                                            0x422d
3711  #define mmDCP5_PRESCALE_GRPH_CONTROL                                            0x442d
3712  #define mmPRESCALE_VALUES_GRPH_R                                                0x1a2e
3713  #define mmDCP0_PRESCALE_VALUES_GRPH_R                                           0x1a2e
3714  #define mmDCP1_PRESCALE_VALUES_GRPH_R                                           0x1c2e
3715  #define mmDCP2_PRESCALE_VALUES_GRPH_R                                           0x1e2e
3716  #define mmDCP3_PRESCALE_VALUES_GRPH_R                                           0x402e
3717  #define mmDCP4_PRESCALE_VALUES_GRPH_R                                           0x422e
3718  #define mmDCP5_PRESCALE_VALUES_GRPH_R                                           0x442e
3719  #define mmPRESCALE_VALUES_GRPH_G                                                0x1a2f
3720  #define mmDCP0_PRESCALE_VALUES_GRPH_G                                           0x1a2f
3721  #define mmDCP1_PRESCALE_VALUES_GRPH_G                                           0x1c2f
3722  #define mmDCP2_PRESCALE_VALUES_GRPH_G                                           0x1e2f
3723  #define mmDCP3_PRESCALE_VALUES_GRPH_G                                           0x402f
3724  #define mmDCP4_PRESCALE_VALUES_GRPH_G                                           0x422f
3725  #define mmDCP5_PRESCALE_VALUES_GRPH_G                                           0x442f
3726  #define mmPRESCALE_VALUES_GRPH_B                                                0x1a30
3727  #define mmDCP0_PRESCALE_VALUES_GRPH_B                                           0x1a30
3728  #define mmDCP1_PRESCALE_VALUES_GRPH_B                                           0x1c30
3729  #define mmDCP2_PRESCALE_VALUES_GRPH_B                                           0x1e30
3730  #define mmDCP3_PRESCALE_VALUES_GRPH_B                                           0x4030
3731  #define mmDCP4_PRESCALE_VALUES_GRPH_B                                           0x4230
3732  #define mmDCP5_PRESCALE_VALUES_GRPH_B                                           0x4430
3733  #define mmINPUT_CSC_CONTROL                                                     0x1a35
3734  #define mmDCP0_INPUT_CSC_CONTROL                                                0x1a35
3735  #define mmDCP1_INPUT_CSC_CONTROL                                                0x1c35
3736  #define mmDCP2_INPUT_CSC_CONTROL                                                0x1e35
3737  #define mmDCP3_INPUT_CSC_CONTROL                                                0x4035
3738  #define mmDCP4_INPUT_CSC_CONTROL                                                0x4235
3739  #define mmDCP5_INPUT_CSC_CONTROL                                                0x4435
3740  #define mmINPUT_CSC_C11_C12                                                     0x1a36
3741  #define mmDCP0_INPUT_CSC_C11_C12                                                0x1a36
3742  #define mmDCP1_INPUT_CSC_C11_C12                                                0x1c36
3743  #define mmDCP2_INPUT_CSC_C11_C12                                                0x1e36
3744  #define mmDCP3_INPUT_CSC_C11_C12                                                0x4036
3745  #define mmDCP4_INPUT_CSC_C11_C12                                                0x4236
3746  #define mmDCP5_INPUT_CSC_C11_C12                                                0x4436
3747  #define mmINPUT_CSC_C13_C14                                                     0x1a37
3748  #define mmDCP0_INPUT_CSC_C13_C14                                                0x1a37
3749  #define mmDCP1_INPUT_CSC_C13_C14                                                0x1c37
3750  #define mmDCP2_INPUT_CSC_C13_C14                                                0x1e37
3751  #define mmDCP3_INPUT_CSC_C13_C14                                                0x4037
3752  #define mmDCP4_INPUT_CSC_C13_C14                                                0x4237
3753  #define mmDCP5_INPUT_CSC_C13_C14                                                0x4437
3754  #define mmINPUT_CSC_C21_C22                                                     0x1a38
3755  #define mmDCP0_INPUT_CSC_C21_C22                                                0x1a38
3756  #define mmDCP1_INPUT_CSC_C21_C22                                                0x1c38
3757  #define mmDCP2_INPUT_CSC_C21_C22                                                0x1e38
3758  #define mmDCP3_INPUT_CSC_C21_C22                                                0x4038
3759  #define mmDCP4_INPUT_CSC_C21_C22                                                0x4238
3760  #define mmDCP5_INPUT_CSC_C21_C22                                                0x4438
3761  #define mmINPUT_CSC_C23_C24                                                     0x1a39
3762  #define mmDCP0_INPUT_CSC_C23_C24                                                0x1a39
3763  #define mmDCP1_INPUT_CSC_C23_C24                                                0x1c39
3764  #define mmDCP2_INPUT_CSC_C23_C24                                                0x1e39
3765  #define mmDCP3_INPUT_CSC_C23_C24                                                0x4039
3766  #define mmDCP4_INPUT_CSC_C23_C24                                                0x4239
3767  #define mmDCP5_INPUT_CSC_C23_C24                                                0x4439
3768  #define mmINPUT_CSC_C31_C32                                                     0x1a3a
3769  #define mmDCP0_INPUT_CSC_C31_C32                                                0x1a3a
3770  #define mmDCP1_INPUT_CSC_C31_C32                                                0x1c3a
3771  #define mmDCP2_INPUT_CSC_C31_C32                                                0x1e3a
3772  #define mmDCP3_INPUT_CSC_C31_C32                                                0x403a
3773  #define mmDCP4_INPUT_CSC_C31_C32                                                0x423a
3774  #define mmDCP5_INPUT_CSC_C31_C32                                                0x443a
3775  #define mmINPUT_CSC_C33_C34                                                     0x1a3b
3776  #define mmDCP0_INPUT_CSC_C33_C34                                                0x1a3b
3777  #define mmDCP1_INPUT_CSC_C33_C34                                                0x1c3b
3778  #define mmDCP2_INPUT_CSC_C33_C34                                                0x1e3b
3779  #define mmDCP3_INPUT_CSC_C33_C34                                                0x403b
3780  #define mmDCP4_INPUT_CSC_C33_C34                                                0x423b
3781  #define mmDCP5_INPUT_CSC_C33_C34                                                0x443b
3782  #define mmOUTPUT_CSC_CONTROL                                                    0x1a3c
3783  #define mmDCP0_OUTPUT_CSC_CONTROL                                               0x1a3c
3784  #define mmDCP1_OUTPUT_CSC_CONTROL                                               0x1c3c
3785  #define mmDCP2_OUTPUT_CSC_CONTROL                                               0x1e3c
3786  #define mmDCP3_OUTPUT_CSC_CONTROL                                               0x403c
3787  #define mmDCP4_OUTPUT_CSC_CONTROL                                               0x423c
3788  #define mmDCP5_OUTPUT_CSC_CONTROL                                               0x443c
3789  #define mmOUTPUT_CSC_C11_C12                                                    0x1a3d
3790  #define mmDCP0_OUTPUT_CSC_C11_C12                                               0x1a3d
3791  #define mmDCP1_OUTPUT_CSC_C11_C12                                               0x1c3d
3792  #define mmDCP2_OUTPUT_CSC_C11_C12                                               0x1e3d
3793  #define mmDCP3_OUTPUT_CSC_C11_C12                                               0x403d
3794  #define mmDCP4_OUTPUT_CSC_C11_C12                                               0x423d
3795  #define mmDCP5_OUTPUT_CSC_C11_C12                                               0x443d
3796  #define mmOUTPUT_CSC_C13_C14                                                    0x1a3e
3797  #define mmDCP0_OUTPUT_CSC_C13_C14                                               0x1a3e
3798  #define mmDCP1_OUTPUT_CSC_C13_C14                                               0x1c3e
3799  #define mmDCP2_OUTPUT_CSC_C13_C14                                               0x1e3e
3800  #define mmDCP3_OUTPUT_CSC_C13_C14                                               0x403e
3801  #define mmDCP4_OUTPUT_CSC_C13_C14                                               0x423e
3802  #define mmDCP5_OUTPUT_CSC_C13_C14                                               0x443e
3803  #define mmOUTPUT_CSC_C21_C22                                                    0x1a3f
3804  #define mmDCP0_OUTPUT_CSC_C21_C22                                               0x1a3f
3805  #define mmDCP1_OUTPUT_CSC_C21_C22                                               0x1c3f
3806  #define mmDCP2_OUTPUT_CSC_C21_C22                                               0x1e3f
3807  #define mmDCP3_OUTPUT_CSC_C21_C22                                               0x403f
3808  #define mmDCP4_OUTPUT_CSC_C21_C22                                               0x423f
3809  #define mmDCP5_OUTPUT_CSC_C21_C22                                               0x443f
3810  #define mmOUTPUT_CSC_C23_C24                                                    0x1a40
3811  #define mmDCP0_OUTPUT_CSC_C23_C24                                               0x1a40
3812  #define mmDCP1_OUTPUT_CSC_C23_C24                                               0x1c40
3813  #define mmDCP2_OUTPUT_CSC_C23_C24                                               0x1e40
3814  #define mmDCP3_OUTPUT_CSC_C23_C24                                               0x4040
3815  #define mmDCP4_OUTPUT_CSC_C23_C24                                               0x4240
3816  #define mmDCP5_OUTPUT_CSC_C23_C24                                               0x4440
3817  #define mmOUTPUT_CSC_C31_C32                                                    0x1a41
3818  #define mmDCP0_OUTPUT_CSC_C31_C32                                               0x1a41
3819  #define mmDCP1_OUTPUT_CSC_C31_C32                                               0x1c41
3820  #define mmDCP2_OUTPUT_CSC_C31_C32                                               0x1e41
3821  #define mmDCP3_OUTPUT_CSC_C31_C32                                               0x4041
3822  #define mmDCP4_OUTPUT_CSC_C31_C32                                               0x4241
3823  #define mmDCP5_OUTPUT_CSC_C31_C32                                               0x4441
3824  #define mmOUTPUT_CSC_C33_C34                                                    0x1a42
3825  #define mmDCP0_OUTPUT_CSC_C33_C34                                               0x1a42
3826  #define mmDCP1_OUTPUT_CSC_C33_C34                                               0x1c42
3827  #define mmDCP2_OUTPUT_CSC_C33_C34                                               0x1e42
3828  #define mmDCP3_OUTPUT_CSC_C33_C34                                               0x4042
3829  #define mmDCP4_OUTPUT_CSC_C33_C34                                               0x4242
3830  #define mmDCP5_OUTPUT_CSC_C33_C34                                               0x4442
3831  #define mmCOMM_MATRIXA_TRANS_C11_C12                                            0x1a43
3832  #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                       0x1a43
3833  #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                       0x1c43
3834  #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                       0x1e43
3835  #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                       0x4043
3836  #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                       0x4243
3837  #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                       0x4443
3838  #define mmCOMM_MATRIXA_TRANS_C13_C14                                            0x1a44
3839  #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                       0x1a44
3840  #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                       0x1c44
3841  #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                       0x1e44
3842  #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                       0x4044
3843  #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                       0x4244
3844  #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                       0x4444
3845  #define mmCOMM_MATRIXA_TRANS_C21_C22                                            0x1a45
3846  #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                       0x1a45
3847  #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                       0x1c45
3848  #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                       0x1e45
3849  #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                       0x4045
3850  #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                       0x4245
3851  #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                       0x4445
3852  #define mmCOMM_MATRIXA_TRANS_C23_C24                                            0x1a46
3853  #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                       0x1a46
3854  #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                       0x1c46
3855  #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                       0x1e46
3856  #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                       0x4046
3857  #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                       0x4246
3858  #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                       0x4446
3859  #define mmCOMM_MATRIXA_TRANS_C31_C32                                            0x1a47
3860  #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                       0x1a47
3861  #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                       0x1c47
3862  #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                       0x1e47
3863  #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                       0x4047
3864  #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                       0x4247
3865  #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                       0x4447
3866  #define mmCOMM_MATRIXA_TRANS_C33_C34                                            0x1a48
3867  #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                       0x1a48
3868  #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                       0x1c48
3869  #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                       0x1e48
3870  #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                       0x4048
3871  #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                       0x4248
3872  #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                       0x4448
3873  #define mmCOMM_MATRIXB_TRANS_C11_C12                                            0x1a49
3874  #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                       0x1a49
3875  #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                       0x1c49
3876  #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                       0x1e49
3877  #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                       0x4049
3878  #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                       0x4249
3879  #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                       0x4449
3880  #define mmCOMM_MATRIXB_TRANS_C13_C14                                            0x1a4a
3881  #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                       0x1a4a
3882  #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                       0x1c4a
3883  #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                       0x1e4a
3884  #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                       0x404a
3885  #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                       0x424a
3886  #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                       0x444a
3887  #define mmCOMM_MATRIXB_TRANS_C21_C22                                            0x1a4b
3888  #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                       0x1a4b
3889  #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                       0x1c4b
3890  #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                       0x1e4b
3891  #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                       0x404b
3892  #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                       0x424b
3893  #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                       0x444b
3894  #define mmCOMM_MATRIXB_TRANS_C23_C24                                            0x1a4c
3895  #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                       0x1a4c
3896  #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                       0x1c4c
3897  #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                       0x1e4c
3898  #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                       0x404c
3899  #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                       0x424c
3900  #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                       0x444c
3901  #define mmCOMM_MATRIXB_TRANS_C31_C32                                            0x1a4d
3902  #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                       0x1a4d
3903  #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                       0x1c4d
3904  #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                       0x1e4d
3905  #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                       0x404d
3906  #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                       0x424d
3907  #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                       0x444d
3908  #define mmCOMM_MATRIXB_TRANS_C33_C34                                            0x1a4e
3909  #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                       0x1a4e
3910  #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                       0x1c4e
3911  #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                       0x1e4e
3912  #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                       0x404e
3913  #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                       0x424e
3914  #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                       0x444e
3915  #define mmDENORM_CONTROL                                                        0x1a50
3916  #define mmDCP0_DENORM_CONTROL                                                   0x1a50
3917  #define mmDCP1_DENORM_CONTROL                                                   0x1c50
3918  #define mmDCP2_DENORM_CONTROL                                                   0x1e50
3919  #define mmDCP3_DENORM_CONTROL                                                   0x4050
3920  #define mmDCP4_DENORM_CONTROL                                                   0x4250
3921  #define mmDCP5_DENORM_CONTROL                                                   0x4450
3922  #define mmOUT_ROUND_CONTROL                                                     0x1a51
3923  #define mmDCP0_OUT_ROUND_CONTROL                                                0x1a51
3924  #define mmDCP1_OUT_ROUND_CONTROL                                                0x1c51
3925  #define mmDCP2_OUT_ROUND_CONTROL                                                0x1e51
3926  #define mmDCP3_OUT_ROUND_CONTROL                                                0x4051
3927  #define mmDCP4_OUT_ROUND_CONTROL                                                0x4251
3928  #define mmDCP5_OUT_ROUND_CONTROL                                                0x4451
3929  #define mmOUT_CLAMP_CONTROL_R_CR                                                0x1a52
3930  #define mmDCP0_OUT_CLAMP_CONTROL_R_CR                                           0x1a52
3931  #define mmDCP1_OUT_CLAMP_CONTROL_R_CR                                           0x1c52
3932  #define mmDCP2_OUT_CLAMP_CONTROL_R_CR                                           0x1e52
3933  #define mmDCP3_OUT_CLAMP_CONTROL_R_CR                                           0x4052
3934  #define mmDCP4_OUT_CLAMP_CONTROL_R_CR                                           0x4252
3935  #define mmDCP5_OUT_CLAMP_CONTROL_R_CR                                           0x4452
3936  #define mmOUT_CLAMP_CONTROL_G_Y                                                 0x1a9c
3937  #define mmDCP0_OUT_CLAMP_CONTROL_G_Y                                            0x1a9c
3938  #define mmDCP1_OUT_CLAMP_CONTROL_G_Y                                            0x1c9c
3939  #define mmDCP2_OUT_CLAMP_CONTROL_G_Y                                            0x1e9c
3940  #define mmDCP3_OUT_CLAMP_CONTROL_G_Y                                            0x409c
3941  #define mmDCP4_OUT_CLAMP_CONTROL_G_Y                                            0x429c
3942  #define mmDCP5_OUT_CLAMP_CONTROL_G_Y                                            0x449c
3943  #define mmOUT_CLAMP_CONTROL_B_CB                                                0x1a9d
3944  #define mmDCP0_OUT_CLAMP_CONTROL_B_CB                                           0x1a9d
3945  #define mmDCP1_OUT_CLAMP_CONTROL_B_CB                                           0x1c9d
3946  #define mmDCP2_OUT_CLAMP_CONTROL_B_CB                                           0x1e9d
3947  #define mmDCP3_OUT_CLAMP_CONTROL_B_CB                                           0x409d
3948  #define mmDCP4_OUT_CLAMP_CONTROL_B_CB                                           0x429d
3949  #define mmDCP5_OUT_CLAMP_CONTROL_B_CB                                           0x449d
3950  #define mmKEY_CONTROL                                                           0x1a53
3951  #define mmDCP0_KEY_CONTROL                                                      0x1a53
3952  #define mmDCP1_KEY_CONTROL                                                      0x1c53
3953  #define mmDCP2_KEY_CONTROL                                                      0x1e53
3954  #define mmDCP3_KEY_CONTROL                                                      0x4053
3955  #define mmDCP4_KEY_CONTROL                                                      0x4253
3956  #define mmDCP5_KEY_CONTROL                                                      0x4453
3957  #define mmKEY_RANGE_ALPHA                                                       0x1a54
3958  #define mmDCP0_KEY_RANGE_ALPHA                                                  0x1a54
3959  #define mmDCP1_KEY_RANGE_ALPHA                                                  0x1c54
3960  #define mmDCP2_KEY_RANGE_ALPHA                                                  0x1e54
3961  #define mmDCP3_KEY_RANGE_ALPHA                                                  0x4054
3962  #define mmDCP4_KEY_RANGE_ALPHA                                                  0x4254
3963  #define mmDCP5_KEY_RANGE_ALPHA                                                  0x4454
3964  #define mmKEY_RANGE_RED                                                         0x1a55
3965  #define mmDCP0_KEY_RANGE_RED                                                    0x1a55
3966  #define mmDCP1_KEY_RANGE_RED                                                    0x1c55
3967  #define mmDCP2_KEY_RANGE_RED                                                    0x1e55
3968  #define mmDCP3_KEY_RANGE_RED                                                    0x4055
3969  #define mmDCP4_KEY_RANGE_RED                                                    0x4255
3970  #define mmDCP5_KEY_RANGE_RED                                                    0x4455
3971  #define mmKEY_RANGE_GREEN                                                       0x1a56
3972  #define mmDCP0_KEY_RANGE_GREEN                                                  0x1a56
3973  #define mmDCP1_KEY_RANGE_GREEN                                                  0x1c56
3974  #define mmDCP2_KEY_RANGE_GREEN                                                  0x1e56
3975  #define mmDCP3_KEY_RANGE_GREEN                                                  0x4056
3976  #define mmDCP4_KEY_RANGE_GREEN                                                  0x4256
3977  #define mmDCP5_KEY_RANGE_GREEN                                                  0x4456
3978  #define mmKEY_RANGE_BLUE                                                        0x1a57
3979  #define mmDCP0_KEY_RANGE_BLUE                                                   0x1a57
3980  #define mmDCP1_KEY_RANGE_BLUE                                                   0x1c57
3981  #define mmDCP2_KEY_RANGE_BLUE                                                   0x1e57
3982  #define mmDCP3_KEY_RANGE_BLUE                                                   0x4057
3983  #define mmDCP4_KEY_RANGE_BLUE                                                   0x4257
3984  #define mmDCP5_KEY_RANGE_BLUE                                                   0x4457
3985  #define mmDEGAMMA_CONTROL                                                       0x1a58
3986  #define mmDCP0_DEGAMMA_CONTROL                                                  0x1a58
3987  #define mmDCP1_DEGAMMA_CONTROL                                                  0x1c58
3988  #define mmDCP2_DEGAMMA_CONTROL                                                  0x1e58
3989  #define mmDCP3_DEGAMMA_CONTROL                                                  0x4058
3990  #define mmDCP4_DEGAMMA_CONTROL                                                  0x4258
3991  #define mmDCP5_DEGAMMA_CONTROL                                                  0x4458
3992  #define mmGAMUT_REMAP_CONTROL                                                   0x1a59
3993  #define mmDCP0_GAMUT_REMAP_CONTROL                                              0x1a59
3994  #define mmDCP1_GAMUT_REMAP_CONTROL                                              0x1c59
3995  #define mmDCP2_GAMUT_REMAP_CONTROL                                              0x1e59
3996  #define mmDCP3_GAMUT_REMAP_CONTROL                                              0x4059
3997  #define mmDCP4_GAMUT_REMAP_CONTROL                                              0x4259
3998  #define mmDCP5_GAMUT_REMAP_CONTROL                                              0x4459
3999  #define mmGAMUT_REMAP_C11_C12                                                   0x1a5a
4000  #define mmDCP0_GAMUT_REMAP_C11_C12                                              0x1a5a
4001  #define mmDCP1_GAMUT_REMAP_C11_C12                                              0x1c5a
4002  #define mmDCP2_GAMUT_REMAP_C11_C12                                              0x1e5a
4003  #define mmDCP3_GAMUT_REMAP_C11_C12                                              0x405a
4004  #define mmDCP4_GAMUT_REMAP_C11_C12                                              0x425a
4005  #define mmDCP5_GAMUT_REMAP_C11_C12                                              0x445a
4006  #define mmGAMUT_REMAP_C13_C14                                                   0x1a5b
4007  #define mmDCP0_GAMUT_REMAP_C13_C14                                              0x1a5b
4008  #define mmDCP1_GAMUT_REMAP_C13_C14                                              0x1c5b
4009  #define mmDCP2_GAMUT_REMAP_C13_C14                                              0x1e5b
4010  #define mmDCP3_GAMUT_REMAP_C13_C14                                              0x405b
4011  #define mmDCP4_GAMUT_REMAP_C13_C14                                              0x425b
4012  #define mmDCP5_GAMUT_REMAP_C13_C14                                              0x445b
4013  #define mmGAMUT_REMAP_C21_C22                                                   0x1a5c
4014  #define mmDCP0_GAMUT_REMAP_C21_C22                                              0x1a5c
4015  #define mmDCP1_GAMUT_REMAP_C21_C22                                              0x1c5c
4016  #define mmDCP2_GAMUT_REMAP_C21_C22                                              0x1e5c
4017  #define mmDCP3_GAMUT_REMAP_C21_C22                                              0x405c
4018  #define mmDCP4_GAMUT_REMAP_C21_C22                                              0x425c
4019  #define mmDCP5_GAMUT_REMAP_C21_C22                                              0x445c
4020  #define mmGAMUT_REMAP_C23_C24                                                   0x1a5d
4021  #define mmDCP0_GAMUT_REMAP_C23_C24                                              0x1a5d
4022  #define mmDCP1_GAMUT_REMAP_C23_C24                                              0x1c5d
4023  #define mmDCP2_GAMUT_REMAP_C23_C24                                              0x1e5d
4024  #define mmDCP3_GAMUT_REMAP_C23_C24                                              0x405d
4025  #define mmDCP4_GAMUT_REMAP_C23_C24                                              0x425d
4026  #define mmDCP5_GAMUT_REMAP_C23_C24                                              0x445d
4027  #define mmGAMUT_REMAP_C31_C32                                                   0x1a5e
4028  #define mmDCP0_GAMUT_REMAP_C31_C32                                              0x1a5e
4029  #define mmDCP1_GAMUT_REMAP_C31_C32                                              0x1c5e
4030  #define mmDCP2_GAMUT_REMAP_C31_C32                                              0x1e5e
4031  #define mmDCP3_GAMUT_REMAP_C31_C32                                              0x405e
4032  #define mmDCP4_GAMUT_REMAP_C31_C32                                              0x425e
4033  #define mmDCP5_GAMUT_REMAP_C31_C32                                              0x445e
4034  #define mmGAMUT_REMAP_C33_C34                                                   0x1a5f
4035  #define mmDCP0_GAMUT_REMAP_C33_C34                                              0x1a5f
4036  #define mmDCP1_GAMUT_REMAP_C33_C34                                              0x1c5f
4037  #define mmDCP2_GAMUT_REMAP_C33_C34                                              0x1e5f
4038  #define mmDCP3_GAMUT_REMAP_C33_C34                                              0x405f
4039  #define mmDCP4_GAMUT_REMAP_C33_C34                                              0x425f
4040  #define mmDCP5_GAMUT_REMAP_C33_C34                                              0x445f
4041  #define mmDCP_SPATIAL_DITHER_CNTL                                               0x1a60
4042  #define mmDCP0_DCP_SPATIAL_DITHER_CNTL                                          0x1a60
4043  #define mmDCP1_DCP_SPATIAL_DITHER_CNTL                                          0x1c60
4044  #define mmDCP2_DCP_SPATIAL_DITHER_CNTL                                          0x1e60
4045  #define mmDCP3_DCP_SPATIAL_DITHER_CNTL                                          0x4060
4046  #define mmDCP4_DCP_SPATIAL_DITHER_CNTL                                          0x4260
4047  #define mmDCP5_DCP_SPATIAL_DITHER_CNTL                                          0x4460
4048  #define mmDCP_RANDOM_SEEDS                                                      0x1a61
4049  #define mmDCP0_DCP_RANDOM_SEEDS                                                 0x1a61
4050  #define mmDCP1_DCP_RANDOM_SEEDS                                                 0x1c61
4051  #define mmDCP2_DCP_RANDOM_SEEDS                                                 0x1e61
4052  #define mmDCP3_DCP_RANDOM_SEEDS                                                 0x4061
4053  #define mmDCP4_DCP_RANDOM_SEEDS                                                 0x4261
4054  #define mmDCP5_DCP_RANDOM_SEEDS                                                 0x4461
4055  #define mmDCP_FP_CONVERTED_FIELD                                                0x1a65
4056  #define mmDCP0_DCP_FP_CONVERTED_FIELD                                           0x1a65
4057  #define mmDCP1_DCP_FP_CONVERTED_FIELD                                           0x1c65
4058  #define mmDCP2_DCP_FP_CONVERTED_FIELD                                           0x1e65
4059  #define mmDCP3_DCP_FP_CONVERTED_FIELD                                           0x4065
4060  #define mmDCP4_DCP_FP_CONVERTED_FIELD                                           0x4265
4061  #define mmDCP5_DCP_FP_CONVERTED_FIELD                                           0x4465
4062  #define mmCUR_CONTROL                                                           0x1a66
4063  #define mmDCP0_CUR_CONTROL                                                      0x1a66
4064  #define mmDCP1_CUR_CONTROL                                                      0x1c66
4065  #define mmDCP2_CUR_CONTROL                                                      0x1e66
4066  #define mmDCP3_CUR_CONTROL                                                      0x4066
4067  #define mmDCP4_CUR_CONTROL                                                      0x4266
4068  #define mmDCP5_CUR_CONTROL                                                      0x4466
4069  #define mmCUR_SURFACE_ADDRESS                                                   0x1a67
4070  #define mmDCP0_CUR_SURFACE_ADDRESS                                              0x1a67
4071  #define mmDCP1_CUR_SURFACE_ADDRESS                                              0x1c67
4072  #define mmDCP2_CUR_SURFACE_ADDRESS                                              0x1e67
4073  #define mmDCP3_CUR_SURFACE_ADDRESS                                              0x4067
4074  #define mmDCP4_CUR_SURFACE_ADDRESS                                              0x4267
4075  #define mmDCP5_CUR_SURFACE_ADDRESS                                              0x4467
4076  #define mmCUR_SIZE                                                              0x1a68
4077  #define mmDCP0_CUR_SIZE                                                         0x1a68
4078  #define mmDCP1_CUR_SIZE                                                         0x1c68
4079  #define mmDCP2_CUR_SIZE                                                         0x1e68
4080  #define mmDCP3_CUR_SIZE                                                         0x4068
4081  #define mmDCP4_CUR_SIZE                                                         0x4268
4082  #define mmDCP5_CUR_SIZE                                                         0x4468
4083  #define mmCUR_SURFACE_ADDRESS_HIGH                                              0x1a69
4084  #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                         0x1a69
4085  #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                         0x1c69
4086  #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                         0x1e69
4087  #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                         0x4069
4088  #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                         0x4269
4089  #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                         0x4469
4090  #define mmCUR_POSITION                                                          0x1a6a
4091  #define mmDCP0_CUR_POSITION                                                     0x1a6a
4092  #define mmDCP1_CUR_POSITION                                                     0x1c6a
4093  #define mmDCP2_CUR_POSITION                                                     0x1e6a
4094  #define mmDCP3_CUR_POSITION                                                     0x406a
4095  #define mmDCP4_CUR_POSITION                                                     0x426a
4096  #define mmDCP5_CUR_POSITION                                                     0x446a
4097  #define mmCUR_HOT_SPOT                                                          0x1a6b
4098  #define mmDCP0_CUR_HOT_SPOT                                                     0x1a6b
4099  #define mmDCP1_CUR_HOT_SPOT                                                     0x1c6b
4100  #define mmDCP2_CUR_HOT_SPOT                                                     0x1e6b
4101  #define mmDCP3_CUR_HOT_SPOT                                                     0x406b
4102  #define mmDCP4_CUR_HOT_SPOT                                                     0x426b
4103  #define mmDCP5_CUR_HOT_SPOT                                                     0x446b
4104  #define mmCUR_COLOR1                                                            0x1a6c
4105  #define mmDCP0_CUR_COLOR1                                                       0x1a6c
4106  #define mmDCP1_CUR_COLOR1                                                       0x1c6c
4107  #define mmDCP2_CUR_COLOR1                                                       0x1e6c
4108  #define mmDCP3_CUR_COLOR1                                                       0x406c
4109  #define mmDCP4_CUR_COLOR1                                                       0x426c
4110  #define mmDCP5_CUR_COLOR1                                                       0x446c
4111  #define mmCUR_COLOR2                                                            0x1a6d
4112  #define mmDCP0_CUR_COLOR2                                                       0x1a6d
4113  #define mmDCP1_CUR_COLOR2                                                       0x1c6d
4114  #define mmDCP2_CUR_COLOR2                                                       0x1e6d
4115  #define mmDCP3_CUR_COLOR2                                                       0x406d
4116  #define mmDCP4_CUR_COLOR2                                                       0x426d
4117  #define mmDCP5_CUR_COLOR2                                                       0x446d
4118  #define mmCUR_UPDATE                                                            0x1a6e
4119  #define mmDCP0_CUR_UPDATE                                                       0x1a6e
4120  #define mmDCP1_CUR_UPDATE                                                       0x1c6e
4121  #define mmDCP2_CUR_UPDATE                                                       0x1e6e
4122  #define mmDCP3_CUR_UPDATE                                                       0x406e
4123  #define mmDCP4_CUR_UPDATE                                                       0x426e
4124  #define mmDCP5_CUR_UPDATE                                                       0x446e
4125  #define mmCUR_REQUEST_FILTER_CNTL                                               0x1a99
4126  #define mmDCP0_CUR_REQUEST_FILTER_CNTL                                          0x1a99
4127  #define mmDCP1_CUR_REQUEST_FILTER_CNTL                                          0x1c99
4128  #define mmDCP2_CUR_REQUEST_FILTER_CNTL                                          0x1e99
4129  #define mmDCP3_CUR_REQUEST_FILTER_CNTL                                          0x4099
4130  #define mmDCP4_CUR_REQUEST_FILTER_CNTL                                          0x4299
4131  #define mmDCP5_CUR_REQUEST_FILTER_CNTL                                          0x4499
4132  #define mmCUR_STEREO_CONTROL                                                    0x1a9a
4133  #define mmDCP0_CUR_STEREO_CONTROL                                               0x1a9a
4134  #define mmDCP1_CUR_STEREO_CONTROL                                               0x1c9a
4135  #define mmDCP2_CUR_STEREO_CONTROL                                               0x1e9a
4136  #define mmDCP3_CUR_STEREO_CONTROL                                               0x409a
4137  #define mmDCP4_CUR_STEREO_CONTROL                                               0x429a
4138  #define mmDCP5_CUR_STEREO_CONTROL                                               0x449a
4139  #define mmDC_LUT_RW_MODE                                                        0x1a78
4140  #define mmDCP0_DC_LUT_RW_MODE                                                   0x1a78
4141  #define mmDCP1_DC_LUT_RW_MODE                                                   0x1c78
4142  #define mmDCP2_DC_LUT_RW_MODE                                                   0x1e78
4143  #define mmDCP3_DC_LUT_RW_MODE                                                   0x4078
4144  #define mmDCP4_DC_LUT_RW_MODE                                                   0x4278
4145  #define mmDCP5_DC_LUT_RW_MODE                                                   0x4478
4146  #define mmDC_LUT_RW_INDEX                                                       0x1a79
4147  #define mmDCP0_DC_LUT_RW_INDEX                                                  0x1a79
4148  #define mmDCP1_DC_LUT_RW_INDEX                                                  0x1c79
4149  #define mmDCP2_DC_LUT_RW_INDEX                                                  0x1e79
4150  #define mmDCP3_DC_LUT_RW_INDEX                                                  0x4079
4151  #define mmDCP4_DC_LUT_RW_INDEX                                                  0x4279
4152  #define mmDCP5_DC_LUT_RW_INDEX                                                  0x4479
4153  #define mmDC_LUT_SEQ_COLOR                                                      0x1a7a
4154  #define mmDCP0_DC_LUT_SEQ_COLOR                                                 0x1a7a
4155  #define mmDCP1_DC_LUT_SEQ_COLOR                                                 0x1c7a
4156  #define mmDCP2_DC_LUT_SEQ_COLOR                                                 0x1e7a
4157  #define mmDCP3_DC_LUT_SEQ_COLOR                                                 0x407a
4158  #define mmDCP4_DC_LUT_SEQ_COLOR                                                 0x427a
4159  #define mmDCP5_DC_LUT_SEQ_COLOR                                                 0x447a
4160  #define mmDC_LUT_PWL_DATA                                                       0x1a7b
4161  #define mmDCP0_DC_LUT_PWL_DATA                                                  0x1a7b
4162  #define mmDCP1_DC_LUT_PWL_DATA                                                  0x1c7b
4163  #define mmDCP2_DC_LUT_PWL_DATA                                                  0x1e7b
4164  #define mmDCP3_DC_LUT_PWL_DATA                                                  0x407b
4165  #define mmDCP4_DC_LUT_PWL_DATA                                                  0x427b
4166  #define mmDCP5_DC_LUT_PWL_DATA                                                  0x447b
4167  #define mmDC_LUT_30_COLOR                                                       0x1a7c
4168  #define mmDCP0_DC_LUT_30_COLOR                                                  0x1a7c
4169  #define mmDCP1_DC_LUT_30_COLOR                                                  0x1c7c
4170  #define mmDCP2_DC_LUT_30_COLOR                                                  0x1e7c
4171  #define mmDCP3_DC_LUT_30_COLOR                                                  0x407c
4172  #define mmDCP4_DC_LUT_30_COLOR                                                  0x427c
4173  #define mmDCP5_DC_LUT_30_COLOR                                                  0x447c
4174  #define mmDC_LUT_VGA_ACCESS_ENABLE                                              0x1a7d
4175  #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                         0x1a7d
4176  #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                         0x1c7d
4177  #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                         0x1e7d
4178  #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                         0x407d
4179  #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                         0x427d
4180  #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                         0x447d
4181  #define mmDC_LUT_WRITE_EN_MASK                                                  0x1a7e
4182  #define mmDCP0_DC_LUT_WRITE_EN_MASK                                             0x1a7e
4183  #define mmDCP1_DC_LUT_WRITE_EN_MASK                                             0x1c7e
4184  #define mmDCP2_DC_LUT_WRITE_EN_MASK                                             0x1e7e
4185  #define mmDCP3_DC_LUT_WRITE_EN_MASK                                             0x407e
4186  #define mmDCP4_DC_LUT_WRITE_EN_MASK                                             0x427e
4187  #define mmDCP5_DC_LUT_WRITE_EN_MASK                                             0x447e
4188  #define mmDC_LUT_AUTOFILL                                                       0x1a7f
4189  #define mmDCP0_DC_LUT_AUTOFILL                                                  0x1a7f
4190  #define mmDCP1_DC_LUT_AUTOFILL                                                  0x1c7f
4191  #define mmDCP2_DC_LUT_AUTOFILL                                                  0x1e7f
4192  #define mmDCP3_DC_LUT_AUTOFILL                                                  0x407f
4193  #define mmDCP4_DC_LUT_AUTOFILL                                                  0x427f
4194  #define mmDCP5_DC_LUT_AUTOFILL                                                  0x447f
4195  #define mmDC_LUT_CONTROL                                                        0x1a80
4196  #define mmDCP0_DC_LUT_CONTROL                                                   0x1a80
4197  #define mmDCP1_DC_LUT_CONTROL                                                   0x1c80
4198  #define mmDCP2_DC_LUT_CONTROL                                                   0x1e80
4199  #define mmDCP3_DC_LUT_CONTROL                                                   0x4080
4200  #define mmDCP4_DC_LUT_CONTROL                                                   0x4280
4201  #define mmDCP5_DC_LUT_CONTROL                                                   0x4480
4202  #define mmDC_LUT_BLACK_OFFSET_BLUE                                              0x1a81
4203  #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                         0x1a81
4204  #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                         0x1c81
4205  #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                         0x1e81
4206  #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                         0x4081
4207  #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                         0x4281
4208  #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                         0x4481
4209  #define mmDC_LUT_BLACK_OFFSET_GREEN                                             0x1a82
4210  #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                        0x1a82
4211  #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                        0x1c82
4212  #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                        0x1e82
4213  #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                        0x4082
4214  #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                        0x4282
4215  #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                        0x4482
4216  #define mmDC_LUT_BLACK_OFFSET_RED                                               0x1a83
4217  #define mmDCP0_DC_LUT_BLACK_OFFSET_RED                                          0x1a83
4218  #define mmDCP1_DC_LUT_BLACK_OFFSET_RED                                          0x1c83
4219  #define mmDCP2_DC_LUT_BLACK_OFFSET_RED                                          0x1e83
4220  #define mmDCP3_DC_LUT_BLACK_OFFSET_RED                                          0x4083
4221  #define mmDCP4_DC_LUT_BLACK_OFFSET_RED                                          0x4283
4222  #define mmDCP5_DC_LUT_BLACK_OFFSET_RED                                          0x4483
4223  #define mmDC_LUT_WHITE_OFFSET_BLUE                                              0x1a84
4224  #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                         0x1a84
4225  #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                         0x1c84
4226  #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                         0x1e84
4227  #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                         0x4084
4228  #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                         0x4284
4229  #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                         0x4484
4230  #define mmDC_LUT_WHITE_OFFSET_GREEN                                             0x1a85
4231  #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                        0x1a85
4232  #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                        0x1c85
4233  #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                        0x1e85
4234  #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                        0x4085
4235  #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                        0x4285
4236  #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                        0x4485
4237  #define mmDC_LUT_WHITE_OFFSET_RED                                               0x1a86
4238  #define mmDCP0_DC_LUT_WHITE_OFFSET_RED                                          0x1a86
4239  #define mmDCP1_DC_LUT_WHITE_OFFSET_RED                                          0x1c86
4240  #define mmDCP2_DC_LUT_WHITE_OFFSET_RED                                          0x1e86
4241  #define mmDCP3_DC_LUT_WHITE_OFFSET_RED                                          0x4086
4242  #define mmDCP4_DC_LUT_WHITE_OFFSET_RED                                          0x4286
4243  #define mmDCP5_DC_LUT_WHITE_OFFSET_RED                                          0x4486
4244  #define mmDCP_CRC_CONTROL                                                       0x1a87
4245  #define mmDCP0_DCP_CRC_CONTROL                                                  0x1a87
4246  #define mmDCP1_DCP_CRC_CONTROL                                                  0x1c87
4247  #define mmDCP2_DCP_CRC_CONTROL                                                  0x1e87
4248  #define mmDCP3_DCP_CRC_CONTROL                                                  0x4087
4249  #define mmDCP4_DCP_CRC_CONTROL                                                  0x4287
4250  #define mmDCP5_DCP_CRC_CONTROL                                                  0x4487
4251  #define mmDCP_CRC_MASK                                                          0x1a88
4252  #define mmDCP0_DCP_CRC_MASK                                                     0x1a88
4253  #define mmDCP1_DCP_CRC_MASK                                                     0x1c88
4254  #define mmDCP2_DCP_CRC_MASK                                                     0x1e88
4255  #define mmDCP3_DCP_CRC_MASK                                                     0x4088
4256  #define mmDCP4_DCP_CRC_MASK                                                     0x4288
4257  #define mmDCP5_DCP_CRC_MASK                                                     0x4488
4258  #define mmDCP_CRC_CURRENT                                                       0x1a89
4259  #define mmDCP0_DCP_CRC_CURRENT                                                  0x1a89
4260  #define mmDCP1_DCP_CRC_CURRENT                                                  0x1c89
4261  #define mmDCP2_DCP_CRC_CURRENT                                                  0x1e89
4262  #define mmDCP3_DCP_CRC_CURRENT                                                  0x4089
4263  #define mmDCP4_DCP_CRC_CURRENT                                                  0x4289
4264  #define mmDCP5_DCP_CRC_CURRENT                                                  0x4489
4265  #define mmDVMM_PTE_CONTROL                                                      0x1a8a
4266  #define mmDCP0_DVMM_PTE_CONTROL                                                 0x1a8a
4267  #define mmDCP1_DVMM_PTE_CONTROL                                                 0x1c8a
4268  #define mmDCP2_DVMM_PTE_CONTROL                                                 0x1e8a
4269  #define mmDCP3_DVMM_PTE_CONTROL                                                 0x408a
4270  #define mmDCP4_DVMM_PTE_CONTROL                                                 0x428a
4271  #define mmDCP5_DVMM_PTE_CONTROL                                                 0x448a
4272  #define mmDCP_CRC_LAST                                                          0x1a8b
4273  #define mmDCP0_DCP_CRC_LAST                                                     0x1a8b
4274  #define mmDCP1_DCP_CRC_LAST                                                     0x1c8b
4275  #define mmDCP2_DCP_CRC_LAST                                                     0x1e8b
4276  #define mmDCP3_DCP_CRC_LAST                                                     0x408b
4277  #define mmDCP4_DCP_CRC_LAST                                                     0x428b
4278  #define mmDCP5_DCP_CRC_LAST                                                     0x448b
4279  #define mmDCP_DEBUG                                                             0x1a8d
4280  #define mmDCP0_DCP_DEBUG                                                        0x1a8d
4281  #define mmDCP1_DCP_DEBUG                                                        0x1c8d
4282  #define mmDCP2_DCP_DEBUG                                                        0x1e8d
4283  #define mmDCP3_DCP_DEBUG                                                        0x408d
4284  #define mmDCP4_DCP_DEBUG                                                        0x428d
4285  #define mmDCP5_DCP_DEBUG                                                        0x448d
4286  #define mmGRPH_FLIP_RATE_CNTL                                                   0x1a8e
4287  #define mmDCP0_GRPH_FLIP_RATE_CNTL                                              0x1a8e
4288  #define mmDCP1_GRPH_FLIP_RATE_CNTL                                              0x1c8e
4289  #define mmDCP2_GRPH_FLIP_RATE_CNTL                                              0x1e8e
4290  #define mmDCP3_GRPH_FLIP_RATE_CNTL                                              0x408e
4291  #define mmDCP4_GRPH_FLIP_RATE_CNTL                                              0x428e
4292  #define mmDCP5_GRPH_FLIP_RATE_CNTL                                              0x448e
4293  #define mmDCP_GSL_CONTROL                                                       0x1a90
4294  #define mmDCP0_DCP_GSL_CONTROL                                                  0x1a90
4295  #define mmDCP1_DCP_GSL_CONTROL                                                  0x1c90
4296  #define mmDCP2_DCP_GSL_CONTROL                                                  0x1e90
4297  #define mmDCP3_DCP_GSL_CONTROL                                                  0x4090
4298  #define mmDCP4_DCP_GSL_CONTROL                                                  0x4290
4299  #define mmDCP5_DCP_GSL_CONTROL                                                  0x4490
4300  #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x1a91
4301  #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1a91
4302  #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1c91
4303  #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x1e91
4304  #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4091
4305  #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4291
4306  #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4491
4307  #define mmDCP_DEBUG_SG                                                          0x1a92
4308  #define mmDCP0_DCP_DEBUG_SG                                                     0x1a92
4309  #define mmDCP1_DCP_DEBUG_SG                                                     0x1c92
4310  #define mmDCP2_DCP_DEBUG_SG                                                     0x1e92
4311  #define mmDCP3_DCP_DEBUG_SG                                                     0x4092
4312  #define mmDCP4_DCP_DEBUG_SG                                                     0x4292
4313  #define mmDCP5_DCP_DEBUG_SG                                                     0x4492
4314  #define mmDCP_DEBUG_SG2                                                         0x1a94
4315  #define mmDCP0_DCP_DEBUG_SG2                                                    0x1a94
4316  #define mmDCP1_DCP_DEBUG_SG2                                                    0x1c94
4317  #define mmDCP2_DCP_DEBUG_SG2                                                    0x1e94
4318  #define mmDCP3_DCP_DEBUG_SG2                                                    0x4094
4319  #define mmDCP4_DCP_DEBUG_SG2                                                    0x4294
4320  #define mmDCP5_DCP_DEBUG_SG2                                                    0x4494
4321  #define mmDCP_DVMM_DEBUG                                                        0x1a93
4322  #define mmDCP0_DCP_DVMM_DEBUG                                                   0x1a93
4323  #define mmDCP1_DCP_DVMM_DEBUG                                                   0x1c93
4324  #define mmDCP2_DCP_DVMM_DEBUG                                                   0x1e93
4325  #define mmDCP3_DCP_DVMM_DEBUG                                                   0x4093
4326  #define mmDCP4_DCP_DVMM_DEBUG                                                   0x4293
4327  #define mmDCP5_DCP_DVMM_DEBUG                                                   0x4493
4328  #define mmDCP_TEST_DEBUG_INDEX                                                  0x1a95
4329  #define mmDCP0_DCP_TEST_DEBUG_INDEX                                             0x1a95
4330  #define mmDCP1_DCP_TEST_DEBUG_INDEX                                             0x1c95
4331  #define mmDCP2_DCP_TEST_DEBUG_INDEX                                             0x1e95
4332  #define mmDCP3_DCP_TEST_DEBUG_INDEX                                             0x4095
4333  #define mmDCP4_DCP_TEST_DEBUG_INDEX                                             0x4295
4334  #define mmDCP5_DCP_TEST_DEBUG_INDEX                                             0x4495
4335  #define mmDCP_TEST_DEBUG_DATA                                                   0x1a96
4336  #define mmDCP0_DCP_TEST_DEBUG_DATA                                              0x1a96
4337  #define mmDCP1_DCP_TEST_DEBUG_DATA                                              0x1c96
4338  #define mmDCP2_DCP_TEST_DEBUG_DATA                                              0x1e96
4339  #define mmDCP3_DCP_TEST_DEBUG_DATA                                              0x4096
4340  #define mmDCP4_DCP_TEST_DEBUG_DATA                                              0x4296
4341  #define mmDCP5_DCP_TEST_DEBUG_DATA                                              0x4496
4342  #define mmGRPH_STEREOSYNC_FLIP                                                  0x1a97
4343  #define mmDCP0_GRPH_STEREOSYNC_FLIP                                             0x1a97
4344  #define mmDCP1_GRPH_STEREOSYNC_FLIP                                             0x1c97
4345  #define mmDCP2_GRPH_STEREOSYNC_FLIP                                             0x1e97
4346  #define mmDCP3_GRPH_STEREOSYNC_FLIP                                             0x4097
4347  #define mmDCP4_GRPH_STEREOSYNC_FLIP                                             0x4297
4348  #define mmDCP5_GRPH_STEREOSYNC_FLIP                                             0x4497
4349  #define mmDCP_DEBUG2                                                            0x1a98
4350  #define mmDCP0_DCP_DEBUG2                                                       0x1a98
4351  #define mmDCP1_DCP_DEBUG2                                                       0x1c98
4352  #define mmDCP2_DCP_DEBUG2                                                       0x1e98
4353  #define mmDCP3_DCP_DEBUG2                                                       0x4098
4354  #define mmDCP4_DCP_DEBUG2                                                       0x4298
4355  #define mmDCP5_DCP_DEBUG2                                                       0x4498
4356  #define mmHW_ROTATION                                                           0x1a9e
4357  #define mmDCP0_HW_ROTATION                                                      0x1a9e
4358  #define mmDCP1_HW_ROTATION                                                      0x1c9e
4359  #define mmDCP2_HW_ROTATION                                                      0x1e9e
4360  #define mmDCP3_HW_ROTATION                                                      0x409e
4361  #define mmDCP4_HW_ROTATION                                                      0x429e
4362  #define mmDCP5_HW_ROTATION                                                      0x449e
4363  #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                    0x1a9f
4364  #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1a9f
4365  #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1c9f
4366  #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x1e9f
4367  #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x409f
4368  #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x429f
4369  #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                               0x449f
4370  #define mmREGAMMA_CONTROL                                                       0x1aa0
4371  #define mmDCP0_REGAMMA_CONTROL                                                  0x1aa0
4372  #define mmDCP1_REGAMMA_CONTROL                                                  0x1ca0
4373  #define mmDCP2_REGAMMA_CONTROL                                                  0x1ea0
4374  #define mmDCP3_REGAMMA_CONTROL                                                  0x40a0
4375  #define mmDCP4_REGAMMA_CONTROL                                                  0x42a0
4376  #define mmDCP5_REGAMMA_CONTROL                                                  0x44a0
4377  #define mmREGAMMA_LUT_INDEX                                                     0x1aa1
4378  #define mmDCP0_REGAMMA_LUT_INDEX                                                0x1aa1
4379  #define mmDCP1_REGAMMA_LUT_INDEX                                                0x1ca1
4380  #define mmDCP2_REGAMMA_LUT_INDEX                                                0x1ea1
4381  #define mmDCP3_REGAMMA_LUT_INDEX                                                0x40a1
4382  #define mmDCP4_REGAMMA_LUT_INDEX                                                0x42a1
4383  #define mmDCP5_REGAMMA_LUT_INDEX                                                0x44a1
4384  #define mmREGAMMA_LUT_DATA                                                      0x1aa2
4385  #define mmDCP0_REGAMMA_LUT_DATA                                                 0x1aa2
4386  #define mmDCP1_REGAMMA_LUT_DATA                                                 0x1ca2
4387  #define mmDCP2_REGAMMA_LUT_DATA                                                 0x1ea2
4388  #define mmDCP3_REGAMMA_LUT_DATA                                                 0x40a2
4389  #define mmDCP4_REGAMMA_LUT_DATA                                                 0x42a2
4390  #define mmDCP5_REGAMMA_LUT_DATA                                                 0x44a2
4391  #define mmREGAMMA_LUT_WRITE_EN_MASK                                             0x1aa3
4392  #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                        0x1aa3
4393  #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ca3
4394  #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                        0x1ea3
4395  #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                        0x40a3
4396  #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                        0x42a3
4397  #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                        0x44a3
4398  #define mmREGAMMA_CNTLA_START_CNTL                                              0x1aa4
4399  #define mmDCP0_REGAMMA_CNTLA_START_CNTL                                         0x1aa4
4400  #define mmDCP1_REGAMMA_CNTLA_START_CNTL                                         0x1ca4
4401  #define mmDCP2_REGAMMA_CNTLA_START_CNTL                                         0x1ea4
4402  #define mmDCP3_REGAMMA_CNTLA_START_CNTL                                         0x40a4
4403  #define mmDCP4_REGAMMA_CNTLA_START_CNTL                                         0x42a4
4404  #define mmDCP5_REGAMMA_CNTLA_START_CNTL                                         0x44a4
4405  #define mmREGAMMA_CNTLA_SLOPE_CNTL                                              0x1aa5
4406  #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1aa5
4407  #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ca5
4408  #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                         0x1ea5
4409  #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                         0x40a5
4410  #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                         0x42a5
4411  #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                         0x44a5
4412  #define mmREGAMMA_CNTLA_END_CNTL1                                               0x1aa6
4413  #define mmDCP0_REGAMMA_CNTLA_END_CNTL1                                          0x1aa6
4414  #define mmDCP1_REGAMMA_CNTLA_END_CNTL1                                          0x1ca6
4415  #define mmDCP2_REGAMMA_CNTLA_END_CNTL1                                          0x1ea6
4416  #define mmDCP3_REGAMMA_CNTLA_END_CNTL1                                          0x40a6
4417  #define mmDCP4_REGAMMA_CNTLA_END_CNTL1                                          0x42a6
4418  #define mmDCP5_REGAMMA_CNTLA_END_CNTL1                                          0x44a6
4419  #define mmREGAMMA_CNTLA_END_CNTL2                                               0x1aa7
4420  #define mmDCP0_REGAMMA_CNTLA_END_CNTL2                                          0x1aa7
4421  #define mmDCP1_REGAMMA_CNTLA_END_CNTL2                                          0x1ca7
4422  #define mmDCP2_REGAMMA_CNTLA_END_CNTL2                                          0x1ea7
4423  #define mmDCP3_REGAMMA_CNTLA_END_CNTL2                                          0x40a7
4424  #define mmDCP4_REGAMMA_CNTLA_END_CNTL2                                          0x42a7
4425  #define mmDCP5_REGAMMA_CNTLA_END_CNTL2                                          0x44a7
4426  #define mmREGAMMA_CNTLA_REGION_0_1                                              0x1aa8
4427  #define mmDCP0_REGAMMA_CNTLA_REGION_0_1                                         0x1aa8
4428  #define mmDCP1_REGAMMA_CNTLA_REGION_0_1                                         0x1ca8
4429  #define mmDCP2_REGAMMA_CNTLA_REGION_0_1                                         0x1ea8
4430  #define mmDCP3_REGAMMA_CNTLA_REGION_0_1                                         0x40a8
4431  #define mmDCP4_REGAMMA_CNTLA_REGION_0_1                                         0x42a8
4432  #define mmDCP5_REGAMMA_CNTLA_REGION_0_1                                         0x44a8
4433  #define mmREGAMMA_CNTLA_REGION_2_3                                              0x1aa9
4434  #define mmDCP0_REGAMMA_CNTLA_REGION_2_3                                         0x1aa9
4435  #define mmDCP1_REGAMMA_CNTLA_REGION_2_3                                         0x1ca9
4436  #define mmDCP2_REGAMMA_CNTLA_REGION_2_3                                         0x1ea9
4437  #define mmDCP3_REGAMMA_CNTLA_REGION_2_3                                         0x40a9
4438  #define mmDCP4_REGAMMA_CNTLA_REGION_2_3                                         0x42a9
4439  #define mmDCP5_REGAMMA_CNTLA_REGION_2_3                                         0x44a9
4440  #define mmREGAMMA_CNTLA_REGION_4_5                                              0x1aaa
4441  #define mmDCP0_REGAMMA_CNTLA_REGION_4_5                                         0x1aaa
4442  #define mmDCP1_REGAMMA_CNTLA_REGION_4_5                                         0x1caa
4443  #define mmDCP2_REGAMMA_CNTLA_REGION_4_5                                         0x1eaa
4444  #define mmDCP3_REGAMMA_CNTLA_REGION_4_5                                         0x40aa
4445  #define mmDCP4_REGAMMA_CNTLA_REGION_4_5                                         0x42aa
4446  #define mmDCP5_REGAMMA_CNTLA_REGION_4_5                                         0x44aa
4447  #define mmREGAMMA_CNTLA_REGION_6_7                                              0x1aab
4448  #define mmDCP0_REGAMMA_CNTLA_REGION_6_7                                         0x1aab
4449  #define mmDCP1_REGAMMA_CNTLA_REGION_6_7                                         0x1cab
4450  #define mmDCP2_REGAMMA_CNTLA_REGION_6_7                                         0x1eab
4451  #define mmDCP3_REGAMMA_CNTLA_REGION_6_7                                         0x40ab
4452  #define mmDCP4_REGAMMA_CNTLA_REGION_6_7                                         0x42ab
4453  #define mmDCP5_REGAMMA_CNTLA_REGION_6_7                                         0x44ab
4454  #define mmREGAMMA_CNTLA_REGION_8_9                                              0x1aac
4455  #define mmDCP0_REGAMMA_CNTLA_REGION_8_9                                         0x1aac
4456  #define mmDCP1_REGAMMA_CNTLA_REGION_8_9                                         0x1cac
4457  #define mmDCP2_REGAMMA_CNTLA_REGION_8_9                                         0x1eac
4458  #define mmDCP3_REGAMMA_CNTLA_REGION_8_9                                         0x40ac
4459  #define mmDCP4_REGAMMA_CNTLA_REGION_8_9                                         0x42ac
4460  #define mmDCP5_REGAMMA_CNTLA_REGION_8_9                                         0x44ac
4461  #define mmREGAMMA_CNTLA_REGION_10_11                                            0x1aad
4462  #define mmDCP0_REGAMMA_CNTLA_REGION_10_11                                       0x1aad
4463  #define mmDCP1_REGAMMA_CNTLA_REGION_10_11                                       0x1cad
4464  #define mmDCP2_REGAMMA_CNTLA_REGION_10_11                                       0x1ead
4465  #define mmDCP3_REGAMMA_CNTLA_REGION_10_11                                       0x40ad
4466  #define mmDCP4_REGAMMA_CNTLA_REGION_10_11                                       0x42ad
4467  #define mmDCP5_REGAMMA_CNTLA_REGION_10_11                                       0x44ad
4468  #define mmREGAMMA_CNTLA_REGION_12_13                                            0x1aae
4469  #define mmDCP0_REGAMMA_CNTLA_REGION_12_13                                       0x1aae
4470  #define mmDCP1_REGAMMA_CNTLA_REGION_12_13                                       0x1cae
4471  #define mmDCP2_REGAMMA_CNTLA_REGION_12_13                                       0x1eae
4472  #define mmDCP3_REGAMMA_CNTLA_REGION_12_13                                       0x40ae
4473  #define mmDCP4_REGAMMA_CNTLA_REGION_12_13                                       0x42ae
4474  #define mmDCP5_REGAMMA_CNTLA_REGION_12_13                                       0x44ae
4475  #define mmREGAMMA_CNTLA_REGION_14_15                                            0x1aaf
4476  #define mmDCP0_REGAMMA_CNTLA_REGION_14_15                                       0x1aaf
4477  #define mmDCP1_REGAMMA_CNTLA_REGION_14_15                                       0x1caf
4478  #define mmDCP2_REGAMMA_CNTLA_REGION_14_15                                       0x1eaf
4479  #define mmDCP3_REGAMMA_CNTLA_REGION_14_15                                       0x40af
4480  #define mmDCP4_REGAMMA_CNTLA_REGION_14_15                                       0x42af
4481  #define mmDCP5_REGAMMA_CNTLA_REGION_14_15                                       0x44af
4482  #define mmREGAMMA_CNTLB_START_CNTL                                              0x1ab0
4483  #define mmDCP0_REGAMMA_CNTLB_START_CNTL                                         0x1ab0
4484  #define mmDCP1_REGAMMA_CNTLB_START_CNTL                                         0x1cb0
4485  #define mmDCP2_REGAMMA_CNTLB_START_CNTL                                         0x1eb0
4486  #define mmDCP3_REGAMMA_CNTLB_START_CNTL                                         0x40b0
4487  #define mmDCP4_REGAMMA_CNTLB_START_CNTL                                         0x42b0
4488  #define mmDCP5_REGAMMA_CNTLB_START_CNTL                                         0x44b0
4489  #define mmREGAMMA_CNTLB_SLOPE_CNTL                                              0x1ab1
4490  #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1ab1
4491  #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1cb1
4492  #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                         0x1eb1
4493  #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                         0x40b1
4494  #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                         0x42b1
4495  #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                         0x44b1
4496  #define mmREGAMMA_CNTLB_END_CNTL1                                               0x1ab2
4497  #define mmDCP0_REGAMMA_CNTLB_END_CNTL1                                          0x1ab2
4498  #define mmDCP1_REGAMMA_CNTLB_END_CNTL1                                          0x1cb2
4499  #define mmDCP2_REGAMMA_CNTLB_END_CNTL1                                          0x1eb2
4500  #define mmDCP3_REGAMMA_CNTLB_END_CNTL1                                          0x40b2
4501  #define mmDCP4_REGAMMA_CNTLB_END_CNTL1                                          0x42b2
4502  #define mmDCP5_REGAMMA_CNTLB_END_CNTL1                                          0x44b2
4503  #define mmREGAMMA_CNTLB_END_CNTL2                                               0x1ab3
4504  #define mmDCP0_REGAMMA_CNTLB_END_CNTL2                                          0x1ab3
4505  #define mmDCP1_REGAMMA_CNTLB_END_CNTL2                                          0x1cb3
4506  #define mmDCP2_REGAMMA_CNTLB_END_CNTL2                                          0x1eb3
4507  #define mmDCP3_REGAMMA_CNTLB_END_CNTL2                                          0x40b3
4508  #define mmDCP4_REGAMMA_CNTLB_END_CNTL2                                          0x42b3
4509  #define mmDCP5_REGAMMA_CNTLB_END_CNTL2                                          0x44b3
4510  #define mmREGAMMA_CNTLB_REGION_0_1                                              0x1ab4
4511  #define mmDCP0_REGAMMA_CNTLB_REGION_0_1                                         0x1ab4
4512  #define mmDCP1_REGAMMA_CNTLB_REGION_0_1                                         0x1cb4
4513  #define mmDCP2_REGAMMA_CNTLB_REGION_0_1                                         0x1eb4
4514  #define mmDCP3_REGAMMA_CNTLB_REGION_0_1                                         0x40b4
4515  #define mmDCP4_REGAMMA_CNTLB_REGION_0_1                                         0x42b4
4516  #define mmDCP5_REGAMMA_CNTLB_REGION_0_1                                         0x44b4
4517  #define mmREGAMMA_CNTLB_REGION_2_3                                              0x1ab5
4518  #define mmDCP0_REGAMMA_CNTLB_REGION_2_3                                         0x1ab5
4519  #define mmDCP1_REGAMMA_CNTLB_REGION_2_3                                         0x1cb5
4520  #define mmDCP2_REGAMMA_CNTLB_REGION_2_3                                         0x1eb5
4521  #define mmDCP3_REGAMMA_CNTLB_REGION_2_3                                         0x40b5
4522  #define mmDCP4_REGAMMA_CNTLB_REGION_2_3                                         0x42b5
4523  #define mmDCP5_REGAMMA_CNTLB_REGION_2_3                                         0x44b5
4524  #define mmREGAMMA_CNTLB_REGION_4_5                                              0x1ab6
4525  #define mmDCP0_REGAMMA_CNTLB_REGION_4_5                                         0x1ab6
4526  #define mmDCP1_REGAMMA_CNTLB_REGION_4_5                                         0x1cb6
4527  #define mmDCP2_REGAMMA_CNTLB_REGION_4_5                                         0x1eb6
4528  #define mmDCP3_REGAMMA_CNTLB_REGION_4_5                                         0x40b6
4529  #define mmDCP4_REGAMMA_CNTLB_REGION_4_5                                         0x42b6
4530  #define mmDCP5_REGAMMA_CNTLB_REGION_4_5                                         0x44b6
4531  #define mmREGAMMA_CNTLB_REGION_6_7                                              0x1ab7
4532  #define mmDCP0_REGAMMA_CNTLB_REGION_6_7                                         0x1ab7
4533  #define mmDCP1_REGAMMA_CNTLB_REGION_6_7                                         0x1cb7
4534  #define mmDCP2_REGAMMA_CNTLB_REGION_6_7                                         0x1eb7
4535  #define mmDCP3_REGAMMA_CNTLB_REGION_6_7                                         0x40b7
4536  #define mmDCP4_REGAMMA_CNTLB_REGION_6_7                                         0x42b7
4537  #define mmDCP5_REGAMMA_CNTLB_REGION_6_7                                         0x44b7
4538  #define mmREGAMMA_CNTLB_REGION_8_9                                              0x1ab8
4539  #define mmDCP0_REGAMMA_CNTLB_REGION_8_9                                         0x1ab8
4540  #define mmDCP1_REGAMMA_CNTLB_REGION_8_9                                         0x1cb8
4541  #define mmDCP2_REGAMMA_CNTLB_REGION_8_9                                         0x1eb8
4542  #define mmDCP3_REGAMMA_CNTLB_REGION_8_9                                         0x40b8
4543  #define mmDCP4_REGAMMA_CNTLB_REGION_8_9                                         0x42b8
4544  #define mmDCP5_REGAMMA_CNTLB_REGION_8_9                                         0x44b8
4545  #define mmREGAMMA_CNTLB_REGION_10_11                                            0x1ab9
4546  #define mmDCP0_REGAMMA_CNTLB_REGION_10_11                                       0x1ab9
4547  #define mmDCP1_REGAMMA_CNTLB_REGION_10_11                                       0x1cb9
4548  #define mmDCP2_REGAMMA_CNTLB_REGION_10_11                                       0x1eb9
4549  #define mmDCP3_REGAMMA_CNTLB_REGION_10_11                                       0x40b9
4550  #define mmDCP4_REGAMMA_CNTLB_REGION_10_11                                       0x42b9
4551  #define mmDCP5_REGAMMA_CNTLB_REGION_10_11                                       0x44b9
4552  #define mmREGAMMA_CNTLB_REGION_12_13                                            0x1aba
4553  #define mmDCP0_REGAMMA_CNTLB_REGION_12_13                                       0x1aba
4554  #define mmDCP1_REGAMMA_CNTLB_REGION_12_13                                       0x1cba
4555  #define mmDCP2_REGAMMA_CNTLB_REGION_12_13                                       0x1eba
4556  #define mmDCP3_REGAMMA_CNTLB_REGION_12_13                                       0x40ba
4557  #define mmDCP4_REGAMMA_CNTLB_REGION_12_13                                       0x42ba
4558  #define mmDCP5_REGAMMA_CNTLB_REGION_12_13                                       0x44ba
4559  #define mmREGAMMA_CNTLB_REGION_14_15                                            0x1abb
4560  #define mmDCP0_REGAMMA_CNTLB_REGION_14_15                                       0x1abb
4561  #define mmDCP1_REGAMMA_CNTLB_REGION_14_15                                       0x1cbb
4562  #define mmDCP2_REGAMMA_CNTLB_REGION_14_15                                       0x1ebb
4563  #define mmDCP3_REGAMMA_CNTLB_REGION_14_15                                       0x40bb
4564  #define mmDCP4_REGAMMA_CNTLB_REGION_14_15                                       0x42bb
4565  #define mmDCP5_REGAMMA_CNTLB_REGION_14_15                                       0x44bb
4566  #define mmALPHA_CONTROL                                                         0x1abc
4567  #define mmDCP0_ALPHA_CONTROL                                                    0x1abc
4568  #define mmDCP1_ALPHA_CONTROL                                                    0x1cbc
4569  #define mmDCP2_ALPHA_CONTROL                                                    0x1ebc
4570  #define mmDCP3_ALPHA_CONTROL                                                    0x40bc
4571  #define mmDCP4_ALPHA_CONTROL                                                    0x42bc
4572  #define mmDCP5_ALPHA_CONTROL                                                    0x44bc
4573  #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                    0x1abd
4574  #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1abd
4575  #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1cbd
4576  #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x1ebd
4577  #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x40bd
4578  #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x42bd
4579  #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                               0x44bd
4580  #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                               0x1abe
4581  #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1abe
4582  #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1cbe
4583  #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x1ebe
4584  #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x40be
4585  #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x42be
4586  #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                          0x44be
4587  #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                  0x1abf
4588  #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1abf
4589  #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1cbf
4590  #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x1ebf
4591  #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x40bf
4592  #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x42bf
4593  #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                             0x44bf
4594  #define mmGRPH_SURFACE_COUNTER_CONTROL                                          0x1a0f
4595  #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL                                     0x1a0f
4596  #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL                                     0x1c0f
4597  #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL                                     0x1e0f
4598  #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL                                     0x400f
4599  #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL                                     0x420f
4600  #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL                                     0x440f
4601  #define mmGRPH_SURFACE_COUNTER_OUTPUT                                           0x1a1d
4602  #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1a1d
4603  #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1c1d
4604  #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT                                      0x1e1d
4605  #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT                                      0x401d
4606  #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT                                      0x421d
4607  #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT                                      0x441d
4608  #define mmDIG_FE_CNTL                                                           0x4a00
4609  #define mmDIG0_DIG_FE_CNTL                                                      0x4a00
4610  #define mmDIG1_DIG_FE_CNTL                                                      0x4b00
4611  #define mmDIG2_DIG_FE_CNTL                                                      0x4c00
4612  #define mmDIG3_DIG_FE_CNTL                                                      0x4d00
4613  #define mmDIG4_DIG_FE_CNTL                                                      0x4e00
4614  #define mmDIG5_DIG_FE_CNTL                                                      0x4f00
4615  #define mmDIG6_DIG_FE_CNTL                                                      0x5400
4616  #define mmDIG7_DIG_FE_CNTL                                                      0x5600
4617  #define mmDIG8_DIG_FE_CNTL                                                      0x5700
4618  #define mmDIG_OUTPUT_CRC_CNTL                                                   0x4a01
4619  #define mmDIG0_DIG_OUTPUT_CRC_CNTL                                              0x4a01
4620  #define mmDIG1_DIG_OUTPUT_CRC_CNTL                                              0x4b01
4621  #define mmDIG2_DIG_OUTPUT_CRC_CNTL                                              0x4c01
4622  #define mmDIG3_DIG_OUTPUT_CRC_CNTL                                              0x4d01
4623  #define mmDIG4_DIG_OUTPUT_CRC_CNTL                                              0x4e01
4624  #define mmDIG5_DIG_OUTPUT_CRC_CNTL                                              0x4f01
4625  #define mmDIG6_DIG_OUTPUT_CRC_CNTL                                              0x5401
4626  #define mmDIG7_DIG_OUTPUT_CRC_CNTL                                              0x5601
4627  #define mmDIG8_DIG_OUTPUT_CRC_CNTL                                              0x5701
4628  #define mmDIG_OUTPUT_CRC_RESULT                                                 0x4a02
4629  #define mmDIG0_DIG_OUTPUT_CRC_RESULT                                            0x4a02
4630  #define mmDIG1_DIG_OUTPUT_CRC_RESULT                                            0x4b02
4631  #define mmDIG2_DIG_OUTPUT_CRC_RESULT                                            0x4c02
4632  #define mmDIG3_DIG_OUTPUT_CRC_RESULT                                            0x4d02
4633  #define mmDIG4_DIG_OUTPUT_CRC_RESULT                                            0x4e02
4634  #define mmDIG5_DIG_OUTPUT_CRC_RESULT                                            0x4f02
4635  #define mmDIG6_DIG_OUTPUT_CRC_RESULT                                            0x5402
4636  #define mmDIG7_DIG_OUTPUT_CRC_RESULT                                            0x5602
4637  #define mmDIG8_DIG_OUTPUT_CRC_RESULT                                            0x5702
4638  #define mmDIG_CLOCK_PATTERN                                                     0x4a03
4639  #define mmDIG0_DIG_CLOCK_PATTERN                                                0x4a03
4640  #define mmDIG1_DIG_CLOCK_PATTERN                                                0x4b03
4641  #define mmDIG2_DIG_CLOCK_PATTERN                                                0x4c03
4642  #define mmDIG3_DIG_CLOCK_PATTERN                                                0x4d03
4643  #define mmDIG4_DIG_CLOCK_PATTERN                                                0x4e03
4644  #define mmDIG5_DIG_CLOCK_PATTERN                                                0x4f03
4645  #define mmDIG6_DIG_CLOCK_PATTERN                                                0x5403
4646  #define mmDIG7_DIG_CLOCK_PATTERN                                                0x5603
4647  #define mmDIG8_DIG_CLOCK_PATTERN                                                0x5703
4648  #define mmDIG_TEST_PATTERN                                                      0x4a04
4649  #define mmDIG0_DIG_TEST_PATTERN                                                 0x4a04
4650  #define mmDIG1_DIG_TEST_PATTERN                                                 0x4b04
4651  #define mmDIG2_DIG_TEST_PATTERN                                                 0x4c04
4652  #define mmDIG3_DIG_TEST_PATTERN                                                 0x4d04
4653  #define mmDIG4_DIG_TEST_PATTERN                                                 0x4e04
4654  #define mmDIG5_DIG_TEST_PATTERN                                                 0x4f04
4655  #define mmDIG6_DIG_TEST_PATTERN                                                 0x5404
4656  #define mmDIG7_DIG_TEST_PATTERN                                                 0x5604
4657  #define mmDIG8_DIG_TEST_PATTERN                                                 0x5704
4658  #define mmDIG_RANDOM_PATTERN_SEED                                               0x4a05
4659  #define mmDIG0_DIG_RANDOM_PATTERN_SEED                                          0x4a05
4660  #define mmDIG1_DIG_RANDOM_PATTERN_SEED                                          0x4b05
4661  #define mmDIG2_DIG_RANDOM_PATTERN_SEED                                          0x4c05
4662  #define mmDIG3_DIG_RANDOM_PATTERN_SEED                                          0x4d05
4663  #define mmDIG4_DIG_RANDOM_PATTERN_SEED                                          0x4e05
4664  #define mmDIG5_DIG_RANDOM_PATTERN_SEED                                          0x4f05
4665  #define mmDIG6_DIG_RANDOM_PATTERN_SEED                                          0x5405
4666  #define mmDIG7_DIG_RANDOM_PATTERN_SEED                                          0x5605
4667  #define mmDIG8_DIG_RANDOM_PATTERN_SEED                                          0x5705
4668  #define mmDIG_FIFO_STATUS                                                       0x4a06
4669  #define mmDIG0_DIG_FIFO_STATUS                                                  0x4a06
4670  #define mmDIG1_DIG_FIFO_STATUS                                                  0x4b06
4671  #define mmDIG2_DIG_FIFO_STATUS                                                  0x4c06
4672  #define mmDIG3_DIG_FIFO_STATUS                                                  0x4d06
4673  #define mmDIG4_DIG_FIFO_STATUS                                                  0x4e06
4674  #define mmDIG5_DIG_FIFO_STATUS                                                  0x4f06
4675  #define mmDIG6_DIG_FIFO_STATUS                                                  0x5406
4676  #define mmDIG7_DIG_FIFO_STATUS                                                  0x5606
4677  #define mmDIG8_DIG_FIFO_STATUS                                                  0x5706
4678  #define mmDIG_DISPCLK_SWITCH_CNTL                                               0x4a07
4679  #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL                                          0x4a07
4680  #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL                                          0x4b07
4681  #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL                                          0x4c07
4682  #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL                                          0x4d07
4683  #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL                                          0x4e07
4684  #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL                                          0x4f07
4685  #define mmDIG6_DIG_DISPCLK_SWITCH_CNTL                                          0x5407
4686  #define mmDIG7_DIG_DISPCLK_SWITCH_CNTL                                          0x5607
4687  #define mmDIG8_DIG_DISPCLK_SWITCH_CNTL                                          0x5707
4688  #define mmDIG_DISPCLK_SWITCH_STATUS                                             0x4a08
4689  #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS                                        0x4a08
4690  #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS                                        0x4b08
4691  #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS                                        0x4c08
4692  #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS                                        0x4d08
4693  #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS                                        0x4e08
4694  #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS                                        0x4f08
4695  #define mmDIG6_DIG_DISPCLK_SWITCH_STATUS                                        0x5408
4696  #define mmDIG7_DIG_DISPCLK_SWITCH_STATUS                                        0x5608
4697  #define mmDIG8_DIG_DISPCLK_SWITCH_STATUS                                        0x5708
4698  #define mmHDMI_CONTROL                                                          0x4a09
4699  #define mmDIG0_HDMI_CONTROL                                                     0x4a09
4700  #define mmDIG1_HDMI_CONTROL                                                     0x4b09
4701  #define mmDIG2_HDMI_CONTROL                                                     0x4c09
4702  #define mmDIG3_HDMI_CONTROL                                                     0x4d09
4703  #define mmDIG4_HDMI_CONTROL                                                     0x4e09
4704  #define mmDIG5_HDMI_CONTROL                                                     0x4f09
4705  #define mmDIG6_HDMI_CONTROL                                                     0x5409
4706  #define mmDIG7_HDMI_CONTROL                                                     0x5609
4707  #define mmDIG8_HDMI_CONTROL                                                     0x5709
4708  #define mmHDMI_STATUS                                                           0x4a0a
4709  #define mmDIG0_HDMI_STATUS                                                      0x4a0a
4710  #define mmDIG1_HDMI_STATUS                                                      0x4b0a
4711  #define mmDIG2_HDMI_STATUS                                                      0x4c0a
4712  #define mmDIG3_HDMI_STATUS                                                      0x4d0a
4713  #define mmDIG4_HDMI_STATUS                                                      0x4e0a
4714  #define mmDIG5_HDMI_STATUS                                                      0x4f0a
4715  #define mmDIG6_HDMI_STATUS                                                      0x540a
4716  #define mmDIG7_HDMI_STATUS                                                      0x560a
4717  #define mmDIG8_HDMI_STATUS                                                      0x570a
4718  #define mmHDMI_AUDIO_PACKET_CONTROL                                             0x4a0b
4719  #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                        0x4a0b
4720  #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                        0x4b0b
4721  #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                        0x4c0b
4722  #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                        0x4d0b
4723  #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                        0x4e0b
4724  #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                        0x4f0b
4725  #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                        0x540b
4726  #define mmDIG7_HDMI_AUDIO_PACKET_CONTROL                                        0x560b
4727  #define mmDIG8_HDMI_AUDIO_PACKET_CONTROL                                        0x570b
4728  #define mmHDMI_ACR_PACKET_CONTROL                                               0x4a0c
4729  #define mmDIG0_HDMI_ACR_PACKET_CONTROL                                          0x4a0c
4730  #define mmDIG1_HDMI_ACR_PACKET_CONTROL                                          0x4b0c
4731  #define mmDIG2_HDMI_ACR_PACKET_CONTROL                                          0x4c0c
4732  #define mmDIG3_HDMI_ACR_PACKET_CONTROL                                          0x4d0c
4733  #define mmDIG4_HDMI_ACR_PACKET_CONTROL                                          0x4e0c
4734  #define mmDIG5_HDMI_ACR_PACKET_CONTROL                                          0x4f0c
4735  #define mmDIG6_HDMI_ACR_PACKET_CONTROL                                          0x540c
4736  #define mmDIG7_HDMI_ACR_PACKET_CONTROL                                          0x560c
4737  #define mmDIG8_HDMI_ACR_PACKET_CONTROL                                          0x570c
4738  #define mmHDMI_VBI_PACKET_CONTROL                                               0x4a0d
4739  #define mmDIG0_HDMI_VBI_PACKET_CONTROL                                          0x4a0d
4740  #define mmDIG1_HDMI_VBI_PACKET_CONTROL                                          0x4b0d
4741  #define mmDIG2_HDMI_VBI_PACKET_CONTROL                                          0x4c0d
4742  #define mmDIG3_HDMI_VBI_PACKET_CONTROL                                          0x4d0d
4743  #define mmDIG4_HDMI_VBI_PACKET_CONTROL                                          0x4e0d
4744  #define mmDIG5_HDMI_VBI_PACKET_CONTROL                                          0x4f0d
4745  #define mmDIG6_HDMI_VBI_PACKET_CONTROL                                          0x540d
4746  #define mmDIG7_HDMI_VBI_PACKET_CONTROL                                          0x560d
4747  #define mmDIG8_HDMI_VBI_PACKET_CONTROL                                          0x570d
4748  #define mmHDMI_INFOFRAME_CONTROL0                                               0x4a0e
4749  #define mmDIG0_HDMI_INFOFRAME_CONTROL0                                          0x4a0e
4750  #define mmDIG1_HDMI_INFOFRAME_CONTROL0                                          0x4b0e
4751  #define mmDIG2_HDMI_INFOFRAME_CONTROL0                                          0x4c0e
4752  #define mmDIG3_HDMI_INFOFRAME_CONTROL0                                          0x4d0e
4753  #define mmDIG4_HDMI_INFOFRAME_CONTROL0                                          0x4e0e
4754  #define mmDIG5_HDMI_INFOFRAME_CONTROL0                                          0x4f0e
4755  #define mmDIG6_HDMI_INFOFRAME_CONTROL0                                          0x540e
4756  #define mmDIG7_HDMI_INFOFRAME_CONTROL0                                          0x560e
4757  #define mmDIG8_HDMI_INFOFRAME_CONTROL0                                          0x570e
4758  #define mmHDMI_INFOFRAME_CONTROL1                                               0x4a0f
4759  #define mmDIG0_HDMI_INFOFRAME_CONTROL1                                          0x4a0f
4760  #define mmDIG1_HDMI_INFOFRAME_CONTROL1                                          0x4b0f
4761  #define mmDIG2_HDMI_INFOFRAME_CONTROL1                                          0x4c0f
4762  #define mmDIG3_HDMI_INFOFRAME_CONTROL1                                          0x4d0f
4763  #define mmDIG4_HDMI_INFOFRAME_CONTROL1                                          0x4e0f
4764  #define mmDIG5_HDMI_INFOFRAME_CONTROL1                                          0x4f0f
4765  #define mmDIG6_HDMI_INFOFRAME_CONTROL1                                          0x540f
4766  #define mmDIG7_HDMI_INFOFRAME_CONTROL1                                          0x560f
4767  #define mmDIG8_HDMI_INFOFRAME_CONTROL1                                          0x570f
4768  #define mmHDMI_GENERIC_PACKET_CONTROL0                                          0x4a10
4769  #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                     0x4a10
4770  #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                     0x4b10
4771  #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                     0x4c10
4772  #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                     0x4d10
4773  #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                     0x4e10
4774  #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                     0x4f10
4775  #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                     0x5410
4776  #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0                                     0x5610
4777  #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0                                     0x5710
4778  #define mmAFMT_INTERRUPT_STATUS                                                 0x4a11
4779  #define mmDIG0_AFMT_INTERRUPT_STATUS                                            0x4a11
4780  #define mmDIG1_AFMT_INTERRUPT_STATUS                                            0x4b11
4781  #define mmDIG2_AFMT_INTERRUPT_STATUS                                            0x4c11
4782  #define mmDIG3_AFMT_INTERRUPT_STATUS                                            0x4d11
4783  #define mmDIG4_AFMT_INTERRUPT_STATUS                                            0x4e11
4784  #define mmDIG5_AFMT_INTERRUPT_STATUS                                            0x4f11
4785  #define mmDIG6_AFMT_INTERRUPT_STATUS                                            0x5411
4786  #define mmDIG7_AFMT_INTERRUPT_STATUS                                            0x5611
4787  #define mmDIG8_AFMT_INTERRUPT_STATUS                                            0x5711
4788  #define mmHDMI_GC                                                               0x4a13
4789  #define mmDIG0_HDMI_GC                                                          0x4a13
4790  #define mmDIG1_HDMI_GC                                                          0x4b13
4791  #define mmDIG2_HDMI_GC                                                          0x4c13
4792  #define mmDIG3_HDMI_GC                                                          0x4d13
4793  #define mmDIG4_HDMI_GC                                                          0x4e13
4794  #define mmDIG5_HDMI_GC                                                          0x4f13
4795  #define mmDIG6_HDMI_GC                                                          0x5413
4796  #define mmDIG7_HDMI_GC                                                          0x5613
4797  #define mmDIG8_HDMI_GC                                                          0x5713
4798  #define mmAFMT_AUDIO_PACKET_CONTROL2                                            0x4a14
4799  #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                       0x4a14
4800  #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                       0x4b14
4801  #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                       0x4c14
4802  #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                       0x4d14
4803  #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                       0x4e14
4804  #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                       0x4f14
4805  #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                       0x5414
4806  #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2                                       0x5614
4807  #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2                                       0x5714
4808  #define mmAFMT_ISRC1_0                                                          0x4a15
4809  #define mmDIG0_AFMT_ISRC1_0                                                     0x4a15
4810  #define mmDIG1_AFMT_ISRC1_0                                                     0x4b15
4811  #define mmDIG2_AFMT_ISRC1_0                                                     0x4c15
4812  #define mmDIG3_AFMT_ISRC1_0                                                     0x4d15
4813  #define mmDIG4_AFMT_ISRC1_0                                                     0x4e15
4814  #define mmDIG5_AFMT_ISRC1_0                                                     0x4f15
4815  #define mmDIG6_AFMT_ISRC1_0                                                     0x5415
4816  #define mmDIG7_AFMT_ISRC1_0                                                     0x5615
4817  #define mmDIG8_AFMT_ISRC1_0                                                     0x5715
4818  #define mmAFMT_ISRC1_1                                                          0x4a16
4819  #define mmDIG0_AFMT_ISRC1_1                                                     0x4a16
4820  #define mmDIG1_AFMT_ISRC1_1                                                     0x4b16
4821  #define mmDIG2_AFMT_ISRC1_1                                                     0x4c16
4822  #define mmDIG3_AFMT_ISRC1_1                                                     0x4d16
4823  #define mmDIG4_AFMT_ISRC1_1                                                     0x4e16
4824  #define mmDIG5_AFMT_ISRC1_1                                                     0x4f16
4825  #define mmDIG6_AFMT_ISRC1_1                                                     0x5416
4826  #define mmDIG7_AFMT_ISRC1_1                                                     0x5616
4827  #define mmDIG8_AFMT_ISRC1_1                                                     0x5716
4828  #define mmAFMT_ISRC1_2                                                          0x4a17
4829  #define mmDIG0_AFMT_ISRC1_2                                                     0x4a17
4830  #define mmDIG1_AFMT_ISRC1_2                                                     0x4b17
4831  #define mmDIG2_AFMT_ISRC1_2                                                     0x4c17
4832  #define mmDIG3_AFMT_ISRC1_2                                                     0x4d17
4833  #define mmDIG4_AFMT_ISRC1_2                                                     0x4e17
4834  #define mmDIG5_AFMT_ISRC1_2                                                     0x4f17
4835  #define mmDIG6_AFMT_ISRC1_2                                                     0x5417
4836  #define mmDIG7_AFMT_ISRC1_2                                                     0x5617
4837  #define mmDIG8_AFMT_ISRC1_2                                                     0x5717
4838  #define mmAFMT_ISRC1_3                                                          0x4a18
4839  #define mmDIG0_AFMT_ISRC1_3                                                     0x4a18
4840  #define mmDIG1_AFMT_ISRC1_3                                                     0x4b18
4841  #define mmDIG2_AFMT_ISRC1_3                                                     0x4c18
4842  #define mmDIG3_AFMT_ISRC1_3                                                     0x4d18
4843  #define mmDIG4_AFMT_ISRC1_3                                                     0x4e18
4844  #define mmDIG5_AFMT_ISRC1_3                                                     0x4f18
4845  #define mmDIG6_AFMT_ISRC1_3                                                     0x5418
4846  #define mmDIG7_AFMT_ISRC1_3                                                     0x5618
4847  #define mmDIG8_AFMT_ISRC1_3                                                     0x5718
4848  #define mmAFMT_ISRC1_4                                                          0x4a19
4849  #define mmDIG0_AFMT_ISRC1_4                                                     0x4a19
4850  #define mmDIG1_AFMT_ISRC1_4                                                     0x4b19
4851  #define mmDIG2_AFMT_ISRC1_4                                                     0x4c19
4852  #define mmDIG3_AFMT_ISRC1_4                                                     0x4d19
4853  #define mmDIG4_AFMT_ISRC1_4                                                     0x4e19
4854  #define mmDIG5_AFMT_ISRC1_4                                                     0x4f19
4855  #define mmDIG6_AFMT_ISRC1_4                                                     0x5419
4856  #define mmDIG7_AFMT_ISRC1_4                                                     0x5619
4857  #define mmDIG8_AFMT_ISRC1_4                                                     0x5719
4858  #define mmAFMT_ISRC2_0                                                          0x4a1a
4859  #define mmDIG0_AFMT_ISRC2_0                                                     0x4a1a
4860  #define mmDIG1_AFMT_ISRC2_0                                                     0x4b1a
4861  #define mmDIG2_AFMT_ISRC2_0                                                     0x4c1a
4862  #define mmDIG3_AFMT_ISRC2_0                                                     0x4d1a
4863  #define mmDIG4_AFMT_ISRC2_0                                                     0x4e1a
4864  #define mmDIG5_AFMT_ISRC2_0                                                     0x4f1a
4865  #define mmDIG6_AFMT_ISRC2_0                                                     0x541a
4866  #define mmDIG7_AFMT_ISRC2_0                                                     0x561a
4867  #define mmDIG8_AFMT_ISRC2_0                                                     0x571a
4868  #define mmAFMT_ISRC2_1                                                          0x4a1b
4869  #define mmDIG0_AFMT_ISRC2_1                                                     0x4a1b
4870  #define mmDIG1_AFMT_ISRC2_1                                                     0x4b1b
4871  #define mmDIG2_AFMT_ISRC2_1                                                     0x4c1b
4872  #define mmDIG3_AFMT_ISRC2_1                                                     0x4d1b
4873  #define mmDIG4_AFMT_ISRC2_1                                                     0x4e1b
4874  #define mmDIG5_AFMT_ISRC2_1                                                     0x4f1b
4875  #define mmDIG6_AFMT_ISRC2_1                                                     0x541b
4876  #define mmDIG7_AFMT_ISRC2_1                                                     0x561b
4877  #define mmDIG8_AFMT_ISRC2_1                                                     0x571b
4878  #define mmAFMT_ISRC2_2                                                          0x4a1c
4879  #define mmDIG0_AFMT_ISRC2_2                                                     0x4a1c
4880  #define mmDIG1_AFMT_ISRC2_2                                                     0x4b1c
4881  #define mmDIG2_AFMT_ISRC2_2                                                     0x4c1c
4882  #define mmDIG3_AFMT_ISRC2_2                                                     0x4d1c
4883  #define mmDIG4_AFMT_ISRC2_2                                                     0x4e1c
4884  #define mmDIG5_AFMT_ISRC2_2                                                     0x4f1c
4885  #define mmDIG6_AFMT_ISRC2_2                                                     0x541c
4886  #define mmDIG7_AFMT_ISRC2_2                                                     0x561c
4887  #define mmDIG8_AFMT_ISRC2_2                                                     0x571c
4888  #define mmAFMT_ISRC2_3                                                          0x4a1d
4889  #define mmDIG0_AFMT_ISRC2_3                                                     0x4a1d
4890  #define mmDIG1_AFMT_ISRC2_3                                                     0x4b1d
4891  #define mmDIG2_AFMT_ISRC2_3                                                     0x4c1d
4892  #define mmDIG3_AFMT_ISRC2_3                                                     0x4d1d
4893  #define mmDIG4_AFMT_ISRC2_3                                                     0x4e1d
4894  #define mmDIG5_AFMT_ISRC2_3                                                     0x4f1d
4895  #define mmDIG6_AFMT_ISRC2_3                                                     0x541d
4896  #define mmDIG7_AFMT_ISRC2_3                                                     0x561d
4897  #define mmDIG8_AFMT_ISRC2_3                                                     0x571d
4898  #define mmAFMT_AVI_INFO0                                                        0x4a1e
4899  #define mmDIG0_AFMT_AVI_INFO0                                                   0x4a1e
4900  #define mmDIG1_AFMT_AVI_INFO0                                                   0x4b1e
4901  #define mmDIG2_AFMT_AVI_INFO0                                                   0x4c1e
4902  #define mmDIG3_AFMT_AVI_INFO0                                                   0x4d1e
4903  #define mmDIG4_AFMT_AVI_INFO0                                                   0x4e1e
4904  #define mmDIG5_AFMT_AVI_INFO0                                                   0x4f1e
4905  #define mmDIG6_AFMT_AVI_INFO0                                                   0x541e
4906  #define mmDIG7_AFMT_AVI_INFO0                                                   0x561e
4907  #define mmDIG8_AFMT_AVI_INFO0                                                   0x571e
4908  #define mmAFMT_AVI_INFO1                                                        0x4a1f
4909  #define mmDIG0_AFMT_AVI_INFO1                                                   0x4a1f
4910  #define mmDIG1_AFMT_AVI_INFO1                                                   0x4b1f
4911  #define mmDIG2_AFMT_AVI_INFO1                                                   0x4c1f
4912  #define mmDIG3_AFMT_AVI_INFO1                                                   0x4d1f
4913  #define mmDIG4_AFMT_AVI_INFO1                                                   0x4e1f
4914  #define mmDIG5_AFMT_AVI_INFO1                                                   0x4f1f
4915  #define mmDIG6_AFMT_AVI_INFO1                                                   0x541f
4916  #define mmDIG7_AFMT_AVI_INFO1                                                   0x561f
4917  #define mmDIG8_AFMT_AVI_INFO1                                                   0x571f
4918  #define mmAFMT_AVI_INFO2                                                        0x4a20
4919  #define mmDIG0_AFMT_AVI_INFO2                                                   0x4a20
4920  #define mmDIG1_AFMT_AVI_INFO2                                                   0x4b20
4921  #define mmDIG2_AFMT_AVI_INFO2                                                   0x4c20
4922  #define mmDIG3_AFMT_AVI_INFO2                                                   0x4d20
4923  #define mmDIG4_AFMT_AVI_INFO2                                                   0x4e20
4924  #define mmDIG5_AFMT_AVI_INFO2                                                   0x4f20
4925  #define mmDIG6_AFMT_AVI_INFO2                                                   0x5420
4926  #define mmDIG7_AFMT_AVI_INFO2                                                   0x5620
4927  #define mmDIG8_AFMT_AVI_INFO2                                                   0x5720
4928  #define mmAFMT_AVI_INFO3                                                        0x4a21
4929  #define mmDIG0_AFMT_AVI_INFO3                                                   0x4a21
4930  #define mmDIG1_AFMT_AVI_INFO3                                                   0x4b21
4931  #define mmDIG2_AFMT_AVI_INFO3                                                   0x4c21
4932  #define mmDIG3_AFMT_AVI_INFO3                                                   0x4d21
4933  #define mmDIG4_AFMT_AVI_INFO3                                                   0x4e21
4934  #define mmDIG5_AFMT_AVI_INFO3                                                   0x4f21
4935  #define mmDIG6_AFMT_AVI_INFO3                                                   0x5421
4936  #define mmDIG7_AFMT_AVI_INFO3                                                   0x5621
4937  #define mmDIG8_AFMT_AVI_INFO3                                                   0x5721
4938  #define mmAFMT_MPEG_INFO0                                                       0x4a22
4939  #define mmDIG0_AFMT_MPEG_INFO0                                                  0x4a22
4940  #define mmDIG1_AFMT_MPEG_INFO0                                                  0x4b22
4941  #define mmDIG2_AFMT_MPEG_INFO0                                                  0x4c22
4942  #define mmDIG3_AFMT_MPEG_INFO0                                                  0x4d22
4943  #define mmDIG4_AFMT_MPEG_INFO0                                                  0x4e22
4944  #define mmDIG5_AFMT_MPEG_INFO0                                                  0x4f22
4945  #define mmDIG6_AFMT_MPEG_INFO0                                                  0x5422
4946  #define mmDIG7_AFMT_MPEG_INFO0                                                  0x5622
4947  #define mmDIG8_AFMT_MPEG_INFO0                                                  0x5722
4948  #define mmAFMT_MPEG_INFO1                                                       0x4a23
4949  #define mmDIG0_AFMT_MPEG_INFO1                                                  0x4a23
4950  #define mmDIG1_AFMT_MPEG_INFO1                                                  0x4b23
4951  #define mmDIG2_AFMT_MPEG_INFO1                                                  0x4c23
4952  #define mmDIG3_AFMT_MPEG_INFO1                                                  0x4d23
4953  #define mmDIG4_AFMT_MPEG_INFO1                                                  0x4e23
4954  #define mmDIG5_AFMT_MPEG_INFO1                                                  0x4f23
4955  #define mmDIG6_AFMT_MPEG_INFO1                                                  0x5423
4956  #define mmDIG7_AFMT_MPEG_INFO1                                                  0x5623
4957  #define mmDIG8_AFMT_MPEG_INFO1                                                  0x5723
4958  #define mmAFMT_GENERIC_HDR                                                      0x4a24
4959  #define mmDIG0_AFMT_GENERIC_HDR                                                 0x4a24
4960  #define mmDIG1_AFMT_GENERIC_HDR                                                 0x4b24
4961  #define mmDIG2_AFMT_GENERIC_HDR                                                 0x4c24
4962  #define mmDIG3_AFMT_GENERIC_HDR                                                 0x4d24
4963  #define mmDIG4_AFMT_GENERIC_HDR                                                 0x4e24
4964  #define mmDIG5_AFMT_GENERIC_HDR                                                 0x4f24
4965  #define mmDIG6_AFMT_GENERIC_HDR                                                 0x5424
4966  #define mmDIG7_AFMT_GENERIC_HDR                                                 0x5624
4967  #define mmDIG8_AFMT_GENERIC_HDR                                                 0x5724
4968  #define mmAFMT_GENERIC_0                                                        0x4a25
4969  #define mmDIG0_AFMT_GENERIC_0                                                   0x4a25
4970  #define mmDIG1_AFMT_GENERIC_0                                                   0x4b25
4971  #define mmDIG2_AFMT_GENERIC_0                                                   0x4c25
4972  #define mmDIG3_AFMT_GENERIC_0                                                   0x4d25
4973  #define mmDIG4_AFMT_GENERIC_0                                                   0x4e25
4974  #define mmDIG5_AFMT_GENERIC_0                                                   0x4f25
4975  #define mmDIG6_AFMT_GENERIC_0                                                   0x5425
4976  #define mmDIG7_AFMT_GENERIC_0                                                   0x5625
4977  #define mmDIG8_AFMT_GENERIC_0                                                   0x5725
4978  #define mmAFMT_GENERIC_1                                                        0x4a26
4979  #define mmDIG0_AFMT_GENERIC_1                                                   0x4a26
4980  #define mmDIG1_AFMT_GENERIC_1                                                   0x4b26
4981  #define mmDIG2_AFMT_GENERIC_1                                                   0x4c26
4982  #define mmDIG3_AFMT_GENERIC_1                                                   0x4d26
4983  #define mmDIG4_AFMT_GENERIC_1                                                   0x4e26
4984  #define mmDIG5_AFMT_GENERIC_1                                                   0x4f26
4985  #define mmDIG6_AFMT_GENERIC_1                                                   0x5426
4986  #define mmDIG7_AFMT_GENERIC_1                                                   0x5626
4987  #define mmDIG8_AFMT_GENERIC_1                                                   0x5726
4988  #define mmAFMT_GENERIC_2                                                        0x4a27
4989  #define mmDIG0_AFMT_GENERIC_2                                                   0x4a27
4990  #define mmDIG1_AFMT_GENERIC_2                                                   0x4b27
4991  #define mmDIG2_AFMT_GENERIC_2                                                   0x4c27
4992  #define mmDIG3_AFMT_GENERIC_2                                                   0x4d27
4993  #define mmDIG4_AFMT_GENERIC_2                                                   0x4e27
4994  #define mmDIG5_AFMT_GENERIC_2                                                   0x4f27
4995  #define mmDIG6_AFMT_GENERIC_2                                                   0x5427
4996  #define mmDIG7_AFMT_GENERIC_2                                                   0x5627
4997  #define mmDIG8_AFMT_GENERIC_2                                                   0x5727
4998  #define mmAFMT_GENERIC_3                                                        0x4a28
4999  #define mmDIG0_AFMT_GENERIC_3                                                   0x4a28
5000  #define mmDIG1_AFMT_GENERIC_3                                                   0x4b28
5001  #define mmDIG2_AFMT_GENERIC_3                                                   0x4c28
5002  #define mmDIG3_AFMT_GENERIC_3                                                   0x4d28
5003  #define mmDIG4_AFMT_GENERIC_3                                                   0x4e28
5004  #define mmDIG5_AFMT_GENERIC_3                                                   0x4f28
5005  #define mmDIG6_AFMT_GENERIC_3                                                   0x5428
5006  #define mmDIG7_AFMT_GENERIC_3                                                   0x5628
5007  #define mmDIG8_AFMT_GENERIC_3                                                   0x5728
5008  #define mmAFMT_GENERIC_4                                                        0x4a29
5009  #define mmDIG0_AFMT_GENERIC_4                                                   0x4a29
5010  #define mmDIG1_AFMT_GENERIC_4                                                   0x4b29
5011  #define mmDIG2_AFMT_GENERIC_4                                                   0x4c29
5012  #define mmDIG3_AFMT_GENERIC_4                                                   0x4d29
5013  #define mmDIG4_AFMT_GENERIC_4                                                   0x4e29
5014  #define mmDIG5_AFMT_GENERIC_4                                                   0x4f29
5015  #define mmDIG6_AFMT_GENERIC_4                                                   0x5429
5016  #define mmDIG7_AFMT_GENERIC_4                                                   0x5629
5017  #define mmDIG8_AFMT_GENERIC_4                                                   0x5729
5018  #define mmAFMT_GENERIC_5                                                        0x4a2a
5019  #define mmDIG0_AFMT_GENERIC_5                                                   0x4a2a
5020  #define mmDIG1_AFMT_GENERIC_5                                                   0x4b2a
5021  #define mmDIG2_AFMT_GENERIC_5                                                   0x4c2a
5022  #define mmDIG3_AFMT_GENERIC_5                                                   0x4d2a
5023  #define mmDIG4_AFMT_GENERIC_5                                                   0x4e2a
5024  #define mmDIG5_AFMT_GENERIC_5                                                   0x4f2a
5025  #define mmDIG6_AFMT_GENERIC_5                                                   0x542a
5026  #define mmDIG7_AFMT_GENERIC_5                                                   0x562a
5027  #define mmDIG8_AFMT_GENERIC_5                                                   0x572a
5028  #define mmAFMT_GENERIC_6                                                        0x4a2b
5029  #define mmDIG0_AFMT_GENERIC_6                                                   0x4a2b
5030  #define mmDIG1_AFMT_GENERIC_6                                                   0x4b2b
5031  #define mmDIG2_AFMT_GENERIC_6                                                   0x4c2b
5032  #define mmDIG3_AFMT_GENERIC_6                                                   0x4d2b
5033  #define mmDIG4_AFMT_GENERIC_6                                                   0x4e2b
5034  #define mmDIG5_AFMT_GENERIC_6                                                   0x4f2b
5035  #define mmDIG6_AFMT_GENERIC_6                                                   0x542b
5036  #define mmDIG7_AFMT_GENERIC_6                                                   0x562b
5037  #define mmDIG8_AFMT_GENERIC_6                                                   0x572b
5038  #define mmAFMT_GENERIC_7                                                        0x4a2c
5039  #define mmDIG0_AFMT_GENERIC_7                                                   0x4a2c
5040  #define mmDIG1_AFMT_GENERIC_7                                                   0x4b2c
5041  #define mmDIG2_AFMT_GENERIC_7                                                   0x4c2c
5042  #define mmDIG3_AFMT_GENERIC_7                                                   0x4d2c
5043  #define mmDIG4_AFMT_GENERIC_7                                                   0x4e2c
5044  #define mmDIG5_AFMT_GENERIC_7                                                   0x4f2c
5045  #define mmDIG6_AFMT_GENERIC_7                                                   0x542c
5046  #define mmDIG7_AFMT_GENERIC_7                                                   0x562c
5047  #define mmDIG8_AFMT_GENERIC_7                                                   0x572c
5048  #define mmHDMI_GENERIC_PACKET_CONTROL1                                          0x4a2d
5049  #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                     0x4a2d
5050  #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                     0x4b2d
5051  #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                     0x4c2d
5052  #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                     0x4d2d
5053  #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                     0x4e2d
5054  #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                     0x4f2d
5055  #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                     0x542d
5056  #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1                                     0x562d
5057  #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1                                     0x572d
5058  #define mmHDMI_ACR_32_0                                                         0x4a2e
5059  #define mmDIG0_HDMI_ACR_32_0                                                    0x4a2e
5060  #define mmDIG1_HDMI_ACR_32_0                                                    0x4b2e
5061  #define mmDIG2_HDMI_ACR_32_0                                                    0x4c2e
5062  #define mmDIG3_HDMI_ACR_32_0                                                    0x4d2e
5063  #define mmDIG4_HDMI_ACR_32_0                                                    0x4e2e
5064  #define mmDIG5_HDMI_ACR_32_0                                                    0x4f2e
5065  #define mmDIG6_HDMI_ACR_32_0                                                    0x542e
5066  #define mmDIG7_HDMI_ACR_32_0                                                    0x562e
5067  #define mmDIG8_HDMI_ACR_32_0                                                    0x572e
5068  #define mmHDMI_ACR_32_1                                                         0x4a2f
5069  #define mmDIG0_HDMI_ACR_32_1                                                    0x4a2f
5070  #define mmDIG1_HDMI_ACR_32_1                                                    0x4b2f
5071  #define mmDIG2_HDMI_ACR_32_1                                                    0x4c2f
5072  #define mmDIG3_HDMI_ACR_32_1                                                    0x4d2f
5073  #define mmDIG4_HDMI_ACR_32_1                                                    0x4e2f
5074  #define mmDIG5_HDMI_ACR_32_1                                                    0x4f2f
5075  #define mmDIG6_HDMI_ACR_32_1                                                    0x542f
5076  #define mmDIG7_HDMI_ACR_32_1                                                    0x562f
5077  #define mmDIG8_HDMI_ACR_32_1                                                    0x572f
5078  #define mmHDMI_ACR_44_0                                                         0x4a30
5079  #define mmDIG0_HDMI_ACR_44_0                                                    0x4a30
5080  #define mmDIG1_HDMI_ACR_44_0                                                    0x4b30
5081  #define mmDIG2_HDMI_ACR_44_0                                                    0x4c30
5082  #define mmDIG3_HDMI_ACR_44_0                                                    0x4d30
5083  #define mmDIG4_HDMI_ACR_44_0                                                    0x4e30
5084  #define mmDIG5_HDMI_ACR_44_0                                                    0x4f30
5085  #define mmDIG6_HDMI_ACR_44_0                                                    0x5430
5086  #define mmDIG7_HDMI_ACR_44_0                                                    0x5630
5087  #define mmDIG8_HDMI_ACR_44_0                                                    0x5730
5088  #define mmHDMI_ACR_44_1                                                         0x4a31
5089  #define mmDIG0_HDMI_ACR_44_1                                                    0x4a31
5090  #define mmDIG1_HDMI_ACR_44_1                                                    0x4b31
5091  #define mmDIG2_HDMI_ACR_44_1                                                    0x4c31
5092  #define mmDIG3_HDMI_ACR_44_1                                                    0x4d31
5093  #define mmDIG4_HDMI_ACR_44_1                                                    0x4e31
5094  #define mmDIG5_HDMI_ACR_44_1                                                    0x4f31
5095  #define mmDIG6_HDMI_ACR_44_1                                                    0x5431
5096  #define mmDIG7_HDMI_ACR_44_1                                                    0x5631
5097  #define mmDIG8_HDMI_ACR_44_1                                                    0x5731
5098  #define mmHDMI_ACR_48_0                                                         0x4a32
5099  #define mmDIG0_HDMI_ACR_48_0                                                    0x4a32
5100  #define mmDIG1_HDMI_ACR_48_0                                                    0x4b32
5101  #define mmDIG2_HDMI_ACR_48_0                                                    0x4c32
5102  #define mmDIG3_HDMI_ACR_48_0                                                    0x4d32
5103  #define mmDIG4_HDMI_ACR_48_0                                                    0x4e32
5104  #define mmDIG5_HDMI_ACR_48_0                                                    0x4f32
5105  #define mmDIG6_HDMI_ACR_48_0                                                    0x5432
5106  #define mmDIG7_HDMI_ACR_48_0                                                    0x5632
5107  #define mmDIG8_HDMI_ACR_48_0                                                    0x5732
5108  #define mmHDMI_ACR_48_1                                                         0x4a33
5109  #define mmDIG0_HDMI_ACR_48_1                                                    0x4a33
5110  #define mmDIG1_HDMI_ACR_48_1                                                    0x4b33
5111  #define mmDIG2_HDMI_ACR_48_1                                                    0x4c33
5112  #define mmDIG3_HDMI_ACR_48_1                                                    0x4d33
5113  #define mmDIG4_HDMI_ACR_48_1                                                    0x4e33
5114  #define mmDIG5_HDMI_ACR_48_1                                                    0x4f33
5115  #define mmDIG6_HDMI_ACR_48_1                                                    0x5433
5116  #define mmDIG7_HDMI_ACR_48_1                                                    0x5633
5117  #define mmDIG8_HDMI_ACR_48_1                                                    0x5733
5118  #define mmHDMI_ACR_STATUS_0                                                     0x4a34
5119  #define mmDIG0_HDMI_ACR_STATUS_0                                                0x4a34
5120  #define mmDIG1_HDMI_ACR_STATUS_0                                                0x4b34
5121  #define mmDIG2_HDMI_ACR_STATUS_0                                                0x4c34
5122  #define mmDIG3_HDMI_ACR_STATUS_0                                                0x4d34
5123  #define mmDIG4_HDMI_ACR_STATUS_0                                                0x4e34
5124  #define mmDIG5_HDMI_ACR_STATUS_0                                                0x4f34
5125  #define mmDIG6_HDMI_ACR_STATUS_0                                                0x5434
5126  #define mmDIG7_HDMI_ACR_STATUS_0                                                0x5634
5127  #define mmDIG8_HDMI_ACR_STATUS_0                                                0x5734
5128  #define mmHDMI_ACR_STATUS_1                                                     0x4a35
5129  #define mmDIG0_HDMI_ACR_STATUS_1                                                0x4a35
5130  #define mmDIG1_HDMI_ACR_STATUS_1                                                0x4b35
5131  #define mmDIG2_HDMI_ACR_STATUS_1                                                0x4c35
5132  #define mmDIG3_HDMI_ACR_STATUS_1                                                0x4d35
5133  #define mmDIG4_HDMI_ACR_STATUS_1                                                0x4e35
5134  #define mmDIG5_HDMI_ACR_STATUS_1                                                0x4f35
5135  #define mmDIG6_HDMI_ACR_STATUS_1                                                0x5435
5136  #define mmDIG7_HDMI_ACR_STATUS_1                                                0x5635
5137  #define mmDIG8_HDMI_ACR_STATUS_1                                                0x5735
5138  #define mmAFMT_AUDIO_INFO0                                                      0x4a36
5139  #define mmDIG0_AFMT_AUDIO_INFO0                                                 0x4a36
5140  #define mmDIG1_AFMT_AUDIO_INFO0                                                 0x4b36
5141  #define mmDIG2_AFMT_AUDIO_INFO0                                                 0x4c36
5142  #define mmDIG3_AFMT_AUDIO_INFO0                                                 0x4d36
5143  #define mmDIG4_AFMT_AUDIO_INFO0                                                 0x4e36
5144  #define mmDIG5_AFMT_AUDIO_INFO0                                                 0x4f36
5145  #define mmDIG6_AFMT_AUDIO_INFO0                                                 0x5436
5146  #define mmDIG7_AFMT_AUDIO_INFO0                                                 0x5636
5147  #define mmDIG8_AFMT_AUDIO_INFO0                                                 0x5736
5148  #define mmAFMT_AUDIO_INFO1                                                      0x4a37
5149  #define mmDIG0_AFMT_AUDIO_INFO1                                                 0x4a37
5150  #define mmDIG1_AFMT_AUDIO_INFO1                                                 0x4b37
5151  #define mmDIG2_AFMT_AUDIO_INFO1                                                 0x4c37
5152  #define mmDIG3_AFMT_AUDIO_INFO1                                                 0x4d37
5153  #define mmDIG4_AFMT_AUDIO_INFO1                                                 0x4e37
5154  #define mmDIG5_AFMT_AUDIO_INFO1                                                 0x4f37
5155  #define mmDIG6_AFMT_AUDIO_INFO1                                                 0x5437
5156  #define mmDIG7_AFMT_AUDIO_INFO1                                                 0x5637
5157  #define mmDIG8_AFMT_AUDIO_INFO1                                                 0x5737
5158  #define mmAFMT_60958_0                                                          0x4a38
5159  #define mmDIG0_AFMT_60958_0                                                     0x4a38
5160  #define mmDIG1_AFMT_60958_0                                                     0x4b38
5161  #define mmDIG2_AFMT_60958_0                                                     0x4c38
5162  #define mmDIG3_AFMT_60958_0                                                     0x4d38
5163  #define mmDIG4_AFMT_60958_0                                                     0x4e38
5164  #define mmDIG5_AFMT_60958_0                                                     0x4f38
5165  #define mmDIG6_AFMT_60958_0                                                     0x5438
5166  #define mmDIG7_AFMT_60958_0                                                     0x5638
5167  #define mmDIG8_AFMT_60958_0                                                     0x5738
5168  #define mmAFMT_60958_1                                                          0x4a39
5169  #define mmDIG0_AFMT_60958_1                                                     0x4a39
5170  #define mmDIG1_AFMT_60958_1                                                     0x4b39
5171  #define mmDIG2_AFMT_60958_1                                                     0x4c39
5172  #define mmDIG3_AFMT_60958_1                                                     0x4d39
5173  #define mmDIG4_AFMT_60958_1                                                     0x4e39
5174  #define mmDIG5_AFMT_60958_1                                                     0x4f39
5175  #define mmDIG6_AFMT_60958_1                                                     0x5439
5176  #define mmDIG7_AFMT_60958_1                                                     0x5639
5177  #define mmDIG8_AFMT_60958_1                                                     0x5739
5178  #define mmAFMT_AUDIO_CRC_CONTROL                                                0x4a3a
5179  #define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                           0x4a3a
5180  #define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                           0x4b3a
5181  #define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                           0x4c3a
5182  #define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                           0x4d3a
5183  #define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                           0x4e3a
5184  #define mmDIG5_AFMT_AUDIO_CRC_CONTROL                                           0x4f3a
5185  #define mmDIG6_AFMT_AUDIO_CRC_CONTROL                                           0x543a
5186  #define mmDIG7_AFMT_AUDIO_CRC_CONTROL                                           0x563a
5187  #define mmDIG8_AFMT_AUDIO_CRC_CONTROL                                           0x573a
5188  #define mmAFMT_RAMP_CONTROL0                                                    0x4a3b
5189  #define mmDIG0_AFMT_RAMP_CONTROL0                                               0x4a3b
5190  #define mmDIG1_AFMT_RAMP_CONTROL0                                               0x4b3b
5191  #define mmDIG2_AFMT_RAMP_CONTROL0                                               0x4c3b
5192  #define mmDIG3_AFMT_RAMP_CONTROL0                                               0x4d3b
5193  #define mmDIG4_AFMT_RAMP_CONTROL0                                               0x4e3b
5194  #define mmDIG5_AFMT_RAMP_CONTROL0                                               0x4f3b
5195  #define mmDIG6_AFMT_RAMP_CONTROL0                                               0x543b
5196  #define mmDIG7_AFMT_RAMP_CONTROL0                                               0x563b
5197  #define mmDIG8_AFMT_RAMP_CONTROL0                                               0x573b
5198  #define mmAFMT_RAMP_CONTROL1                                                    0x4a3c
5199  #define mmDIG0_AFMT_RAMP_CONTROL1                                               0x4a3c
5200  #define mmDIG1_AFMT_RAMP_CONTROL1                                               0x4b3c
5201  #define mmDIG2_AFMT_RAMP_CONTROL1                                               0x4c3c
5202  #define mmDIG3_AFMT_RAMP_CONTROL1                                               0x4d3c
5203  #define mmDIG4_AFMT_RAMP_CONTROL1                                               0x4e3c
5204  #define mmDIG5_AFMT_RAMP_CONTROL1                                               0x4f3c
5205  #define mmDIG6_AFMT_RAMP_CONTROL1                                               0x543c
5206  #define mmDIG7_AFMT_RAMP_CONTROL1                                               0x563c
5207  #define mmDIG8_AFMT_RAMP_CONTROL1                                               0x573c
5208  #define mmAFMT_RAMP_CONTROL2                                                    0x4a3d
5209  #define mmDIG0_AFMT_RAMP_CONTROL2                                               0x4a3d
5210  #define mmDIG1_AFMT_RAMP_CONTROL2                                               0x4b3d
5211  #define mmDIG2_AFMT_RAMP_CONTROL2                                               0x4c3d
5212  #define mmDIG3_AFMT_RAMP_CONTROL2                                               0x4d3d
5213  #define mmDIG4_AFMT_RAMP_CONTROL2                                               0x4e3d
5214  #define mmDIG5_AFMT_RAMP_CONTROL2                                               0x4f3d
5215  #define mmDIG6_AFMT_RAMP_CONTROL2                                               0x543d
5216  #define mmDIG7_AFMT_RAMP_CONTROL2                                               0x563d
5217  #define mmDIG8_AFMT_RAMP_CONTROL2                                               0x573d
5218  #define mmAFMT_RAMP_CONTROL3                                                    0x4a3e
5219  #define mmDIG0_AFMT_RAMP_CONTROL3                                               0x4a3e
5220  #define mmDIG1_AFMT_RAMP_CONTROL3                                               0x4b3e
5221  #define mmDIG2_AFMT_RAMP_CONTROL3                                               0x4c3e
5222  #define mmDIG3_AFMT_RAMP_CONTROL3                                               0x4d3e
5223  #define mmDIG4_AFMT_RAMP_CONTROL3                                               0x4e3e
5224  #define mmDIG5_AFMT_RAMP_CONTROL3                                               0x4f3e
5225  #define mmDIG6_AFMT_RAMP_CONTROL3                                               0x543e
5226  #define mmDIG7_AFMT_RAMP_CONTROL3                                               0x563e
5227  #define mmDIG8_AFMT_RAMP_CONTROL3                                               0x573e
5228  #define mmAFMT_60958_2                                                          0x4a3f
5229  #define mmDIG0_AFMT_60958_2                                                     0x4a3f
5230  #define mmDIG1_AFMT_60958_2                                                     0x4b3f
5231  #define mmDIG2_AFMT_60958_2                                                     0x4c3f
5232  #define mmDIG3_AFMT_60958_2                                                     0x4d3f
5233  #define mmDIG4_AFMT_60958_2                                                     0x4e3f
5234  #define mmDIG5_AFMT_60958_2                                                     0x4f3f
5235  #define mmDIG6_AFMT_60958_2                                                     0x543f
5236  #define mmDIG7_AFMT_60958_2                                                     0x563f
5237  #define mmDIG8_AFMT_60958_2                                                     0x573f
5238  #define mmAFMT_AUDIO_CRC_RESULT                                                 0x4a40
5239  #define mmDIG0_AFMT_AUDIO_CRC_RESULT                                            0x4a40
5240  #define mmDIG1_AFMT_AUDIO_CRC_RESULT                                            0x4b40
5241  #define mmDIG2_AFMT_AUDIO_CRC_RESULT                                            0x4c40
5242  #define mmDIG3_AFMT_AUDIO_CRC_RESULT                                            0x4d40
5243  #define mmDIG4_AFMT_AUDIO_CRC_RESULT                                            0x4e40
5244  #define mmDIG5_AFMT_AUDIO_CRC_RESULT                                            0x4f40
5245  #define mmDIG6_AFMT_AUDIO_CRC_RESULT                                            0x5440
5246  #define mmDIG7_AFMT_AUDIO_CRC_RESULT                                            0x5640
5247  #define mmDIG8_AFMT_AUDIO_CRC_RESULT                                            0x5740
5248  #define mmAFMT_STATUS                                                           0x4a41
5249  #define mmDIG0_AFMT_STATUS                                                      0x4a41
5250  #define mmDIG1_AFMT_STATUS                                                      0x4b41
5251  #define mmDIG2_AFMT_STATUS                                                      0x4c41
5252  #define mmDIG3_AFMT_STATUS                                                      0x4d41
5253  #define mmDIG4_AFMT_STATUS                                                      0x4e41
5254  #define mmDIG5_AFMT_STATUS                                                      0x4f41
5255  #define mmDIG6_AFMT_STATUS                                                      0x5441
5256  #define mmDIG7_AFMT_STATUS                                                      0x5641
5257  #define mmDIG8_AFMT_STATUS                                                      0x5741
5258  #define mmAFMT_AUDIO_PACKET_CONTROL                                             0x4a42
5259  #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                        0x4a42
5260  #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                        0x4b42
5261  #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                        0x4c42
5262  #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                        0x4d42
5263  #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                        0x4e42
5264  #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                        0x4f42
5265  #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                        0x5442
5266  #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL                                        0x5642
5267  #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL                                        0x5742
5268  #define mmAFMT_VBI_PACKET_CONTROL                                               0x4a43
5269  #define mmDIG0_AFMT_VBI_PACKET_CONTROL                                          0x4a43
5270  #define mmDIG1_AFMT_VBI_PACKET_CONTROL                                          0x4b43
5271  #define mmDIG2_AFMT_VBI_PACKET_CONTROL                                          0x4c43
5272  #define mmDIG3_AFMT_VBI_PACKET_CONTROL                                          0x4d43
5273  #define mmDIG4_AFMT_VBI_PACKET_CONTROL                                          0x4e43
5274  #define mmDIG5_AFMT_VBI_PACKET_CONTROL                                          0x4f43
5275  #define mmDIG6_AFMT_VBI_PACKET_CONTROL                                          0x5443
5276  #define mmDIG7_AFMT_VBI_PACKET_CONTROL                                          0x5643
5277  #define mmDIG8_AFMT_VBI_PACKET_CONTROL                                          0x5743
5278  #define mmAFMT_INFOFRAME_CONTROL0                                               0x4a44
5279  #define mmDIG0_AFMT_INFOFRAME_CONTROL0                                          0x4a44
5280  #define mmDIG1_AFMT_INFOFRAME_CONTROL0                                          0x4b44
5281  #define mmDIG2_AFMT_INFOFRAME_CONTROL0                                          0x4c44
5282  #define mmDIG3_AFMT_INFOFRAME_CONTROL0                                          0x4d44
5283  #define mmDIG4_AFMT_INFOFRAME_CONTROL0                                          0x4e44
5284  #define mmDIG5_AFMT_INFOFRAME_CONTROL0                                          0x4f44
5285  #define mmDIG6_AFMT_INFOFRAME_CONTROL0                                          0x5444
5286  #define mmDIG7_AFMT_INFOFRAME_CONTROL0                                          0x5644
5287  #define mmDIG8_AFMT_INFOFRAME_CONTROL0                                          0x5744
5288  #define mmAFMT_AUDIO_SRC_CONTROL                                                0x4a45
5289  #define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                           0x4a45
5290  #define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                           0x4b45
5291  #define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                           0x4c45
5292  #define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                           0x4d45
5293  #define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                           0x4e45
5294  #define mmDIG5_AFMT_AUDIO_SRC_CONTROL                                           0x4f45
5295  #define mmDIG6_AFMT_AUDIO_SRC_CONTROL                                           0x5445
5296  #define mmDIG7_AFMT_AUDIO_SRC_CONTROL                                           0x5645
5297  #define mmDIG8_AFMT_AUDIO_SRC_CONTROL                                           0x5745
5298  #define mmAFMT_AUDIO_DBG_DTO_CNTL                                               0x4a46
5299  #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4a46
5300  #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4b46
5301  #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4c46
5302  #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4d46
5303  #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4e46
5304  #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL                                          0x4f46
5305  #define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5446
5306  #define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5646
5307  #define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL                                          0x5746
5308  #define mmAFMT_CNTL                                                             0x4a7e
5309  #define mmDIG0_AFMT_CNTL                                                        0x4a7e
5310  #define mmDIG1_AFMT_CNTL                                                        0x4b7e
5311  #define mmDIG2_AFMT_CNTL                                                        0x4c7e
5312  #define mmDIG3_AFMT_CNTL                                                        0x4d7e
5313  #define mmDIG4_AFMT_CNTL                                                        0x4e7e
5314  #define mmDIG5_AFMT_CNTL                                                        0x4f7e
5315  #define mmDIG6_AFMT_CNTL                                                        0x547e
5316  #define mmDIG7_AFMT_CNTL                                                        0x567e
5317  #define mmDIG8_AFMT_CNTL                                                        0x577e
5318  #define mmDIG_BE_CNTL                                                           0x4a47
5319  #define mmDIG0_DIG_BE_CNTL                                                      0x4a47
5320  #define mmDIG1_DIG_BE_CNTL                                                      0x4b47
5321  #define mmDIG2_DIG_BE_CNTL                                                      0x4c47
5322  #define mmDIG3_DIG_BE_CNTL                                                      0x4d47
5323  #define mmDIG4_DIG_BE_CNTL                                                      0x4e47
5324  #define mmDIG5_DIG_BE_CNTL                                                      0x4f47
5325  #define mmDIG6_DIG_BE_CNTL                                                      0x5447
5326  #define mmDIG7_DIG_BE_CNTL                                                      0x5647
5327  #define mmDIG8_DIG_BE_CNTL                                                      0x5747
5328  #define mmDIG_BE_EN_CNTL                                                        0x4a48
5329  #define mmDIG0_DIG_BE_EN_CNTL                                                   0x4a48
5330  #define mmDIG1_DIG_BE_EN_CNTL                                                   0x4b48
5331  #define mmDIG2_DIG_BE_EN_CNTL                                                   0x4c48
5332  #define mmDIG3_DIG_BE_EN_CNTL                                                   0x4d48
5333  #define mmDIG4_DIG_BE_EN_CNTL                                                   0x4e48
5334  #define mmDIG5_DIG_BE_EN_CNTL                                                   0x4f48
5335  #define mmDIG6_DIG_BE_EN_CNTL                                                   0x5448
5336  #define mmDIG7_DIG_BE_EN_CNTL                                                   0x5648
5337  #define mmDIG8_DIG_BE_EN_CNTL                                                   0x5748
5338  #define mmTMDS_CNTL                                                             0x4a6b
5339  #define mmDIG0_TMDS_CNTL                                                        0x4a6b
5340  #define mmDIG1_TMDS_CNTL                                                        0x4b6b
5341  #define mmDIG2_TMDS_CNTL                                                        0x4c6b
5342  #define mmDIG3_TMDS_CNTL                                                        0x4d6b
5343  #define mmDIG4_TMDS_CNTL                                                        0x4e6b
5344  #define mmDIG5_TMDS_CNTL                                                        0x4f6b
5345  #define mmDIG6_TMDS_CNTL                                                        0x546b
5346  #define mmDIG7_TMDS_CNTL                                                        0x566b
5347  #define mmDIG8_TMDS_CNTL                                                        0x576b
5348  #define mmTMDS_CONTROL_CHAR                                                     0x4a6c
5349  #define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
5350  #define mmDIG1_TMDS_CONTROL_CHAR                                                0x4b6c
5351  #define mmDIG2_TMDS_CONTROL_CHAR                                                0x4c6c
5352  #define mmDIG3_TMDS_CONTROL_CHAR                                                0x4d6c
5353  #define mmDIG4_TMDS_CONTROL_CHAR                                                0x4e6c
5354  #define mmDIG5_TMDS_CONTROL_CHAR                                                0x4f6c
5355  #define mmDIG6_TMDS_CONTROL_CHAR                                                0x546c
5356  #define mmDIG7_TMDS_CONTROL_CHAR                                                0x566c
5357  #define mmDIG8_TMDS_CONTROL_CHAR                                                0x576c
5358  #define mmTMDS_CONTROL0_FEEDBACK                                                0x4a6d
5359  #define mmDIG0_TMDS_CONTROL0_FEEDBACK                                           0x4a6d
5360  #define mmDIG1_TMDS_CONTROL0_FEEDBACK                                           0x4b6d
5361  #define mmDIG2_TMDS_CONTROL0_FEEDBACK                                           0x4c6d
5362  #define mmDIG3_TMDS_CONTROL0_FEEDBACK                                           0x4d6d
5363  #define mmDIG4_TMDS_CONTROL0_FEEDBACK                                           0x4e6d
5364  #define mmDIG5_TMDS_CONTROL0_FEEDBACK                                           0x4f6d
5365  #define mmDIG6_TMDS_CONTROL0_FEEDBACK                                           0x546d
5366  #define mmDIG7_TMDS_CONTROL0_FEEDBACK                                           0x566d
5367  #define mmDIG8_TMDS_CONTROL0_FEEDBACK                                           0x576d
5368  #define mmTMDS_STEREOSYNC_CTL_SEL                                               0x4a6e
5369  #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                          0x4a6e
5370  #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                          0x4b6e
5371  #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                          0x4c6e
5372  #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                          0x4d6e
5373  #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                          0x4e6e
5374  #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                          0x4f6e
5375  #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                          0x546e
5376  #define mmDIG7_TMDS_STEREOSYNC_CTL_SEL                                          0x566e
5377  #define mmDIG8_TMDS_STEREOSYNC_CTL_SEL                                          0x576e
5378  #define mmTMDS_SYNC_CHAR_PATTERN_0_1                                            0x4a6f
5379  #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4a6f
5380  #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4b6f
5381  #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4c6f
5382  #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4d6f
5383  #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4e6f
5384  #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x4f6f
5385  #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x546f
5386  #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x566f
5387  #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1                                       0x576f
5388  #define mmTMDS_SYNC_CHAR_PATTERN_2_3                                            0x4a70
5389  #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4a70
5390  #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4b70
5391  #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4c70
5392  #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4d70
5393  #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4e70
5394  #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x4f70
5395  #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5470
5396  #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5670
5397  #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3                                       0x5770
5398  #define mmTMDS_DEBUG                                                            0x4a71
5399  #define mmDIG0_TMDS_DEBUG                                                       0x4a71
5400  #define mmDIG1_TMDS_DEBUG                                                       0x4b71
5401  #define mmDIG2_TMDS_DEBUG                                                       0x4c71
5402  #define mmDIG3_TMDS_DEBUG                                                       0x4d71
5403  #define mmDIG4_TMDS_DEBUG                                                       0x4e71
5404  #define mmDIG5_TMDS_DEBUG                                                       0x4f71
5405  #define mmDIG6_TMDS_DEBUG                                                       0x5471
5406  #define mmDIG7_TMDS_DEBUG                                                       0x5671
5407  #define mmDIG8_TMDS_DEBUG                                                       0x5771
5408  #define mmTMDS_CTL_BITS                                                         0x4a72
5409  #define mmDIG0_TMDS_CTL_BITS                                                    0x4a72
5410  #define mmDIG1_TMDS_CTL_BITS                                                    0x4b72
5411  #define mmDIG2_TMDS_CTL_BITS                                                    0x4c72
5412  #define mmDIG3_TMDS_CTL_BITS                                                    0x4d72
5413  #define mmDIG4_TMDS_CTL_BITS                                                    0x4e72
5414  #define mmDIG5_TMDS_CTL_BITS                                                    0x4f72
5415  #define mmDIG6_TMDS_CTL_BITS                                                    0x5472
5416  #define mmDIG7_TMDS_CTL_BITS                                                    0x5672
5417  #define mmDIG8_TMDS_CTL_BITS                                                    0x5772
5418  #define mmTMDS_DCBALANCER_CONTROL                                               0x4a73
5419  #define mmDIG0_TMDS_DCBALANCER_CONTROL                                          0x4a73
5420  #define mmDIG1_TMDS_DCBALANCER_CONTROL                                          0x4b73
5421  #define mmDIG2_TMDS_DCBALANCER_CONTROL                                          0x4c73
5422  #define mmDIG3_TMDS_DCBALANCER_CONTROL                                          0x4d73
5423  #define mmDIG4_TMDS_DCBALANCER_CONTROL                                          0x4e73
5424  #define mmDIG5_TMDS_DCBALANCER_CONTROL                                          0x4f73
5425  #define mmDIG6_TMDS_DCBALANCER_CONTROL                                          0x5473
5426  #define mmDIG7_TMDS_DCBALANCER_CONTROL                                          0x5673
5427  #define mmDIG8_TMDS_DCBALANCER_CONTROL                                          0x5773
5428  #define mmTMDS_CTL0_1_GEN_CNTL                                                  0x4a75
5429  #define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                             0x4a75
5430  #define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                             0x4b75
5431  #define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                             0x4c75
5432  #define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                             0x4d75
5433  #define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                             0x4e75
5434  #define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                             0x4f75
5435  #define mmDIG6_TMDS_CTL0_1_GEN_CNTL                                             0x5475
5436  #define mmDIG7_TMDS_CTL0_1_GEN_CNTL                                             0x5675
5437  #define mmDIG8_TMDS_CTL0_1_GEN_CNTL                                             0x5775
5438  #define mmTMDS_CTL2_3_GEN_CNTL                                                  0x4a76
5439  #define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                             0x4a76
5440  #define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                             0x4b76
5441  #define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                             0x4c76
5442  #define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                             0x4d76
5443  #define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                             0x4e76
5444  #define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                             0x4f76
5445  #define mmDIG6_TMDS_CTL2_3_GEN_CNTL                                             0x5476
5446  #define mmDIG7_TMDS_CTL2_3_GEN_CNTL                                             0x5676
5447  #define mmDIG8_TMDS_CTL2_3_GEN_CNTL                                             0x5776
5448  #define mmDIG_VERSION                                                           0x4a78
5449  #define mmDIG0_DIG_VERSION                                                      0x4a78
5450  #define mmDIG1_DIG_VERSION                                                      0x4b78
5451  #define mmDIG2_DIG_VERSION                                                      0x4c78
5452  #define mmDIG3_DIG_VERSION                                                      0x4d78
5453  #define mmDIG4_DIG_VERSION                                                      0x4e78
5454  #define mmDIG5_DIG_VERSION                                                      0x4f78
5455  #define mmDIG6_DIG_VERSION                                                      0x5478
5456  #define mmDIG7_DIG_VERSION                                                      0x5678
5457  #define mmDIG8_DIG_VERSION                                                      0x5778
5458  #define mmDIG_LANE_ENABLE                                                       0x4a79
5459  #define mmDIG0_DIG_LANE_ENABLE                                                  0x4a79
5460  #define mmDIG1_DIG_LANE_ENABLE                                                  0x4b79
5461  #define mmDIG2_DIG_LANE_ENABLE                                                  0x4c79
5462  #define mmDIG3_DIG_LANE_ENABLE                                                  0x4d79
5463  #define mmDIG4_DIG_LANE_ENABLE                                                  0x4e79
5464  #define mmDIG5_DIG_LANE_ENABLE                                                  0x4f79
5465  #define mmDIG6_DIG_LANE_ENABLE                                                  0x5479
5466  #define mmDIG7_DIG_LANE_ENABLE                                                  0x5679
5467  #define mmDIG8_DIG_LANE_ENABLE                                                  0x5779
5468  #define mmDIG_TEST_DEBUG_INDEX                                                  0x4a7a
5469  #define mmDIG0_DIG_TEST_DEBUG_INDEX                                             0x4a7a
5470  #define mmDIG1_DIG_TEST_DEBUG_INDEX                                             0x4b7a
5471  #define mmDIG2_DIG_TEST_DEBUG_INDEX                                             0x4c7a
5472  #define mmDIG3_DIG_TEST_DEBUG_INDEX                                             0x4d7a
5473  #define mmDIG4_DIG_TEST_DEBUG_INDEX                                             0x4e7a
5474  #define mmDIG5_DIG_TEST_DEBUG_INDEX                                             0x4f7a
5475  #define mmDIG6_DIG_TEST_DEBUG_INDEX                                             0x547a
5476  #define mmDIG7_DIG_TEST_DEBUG_INDEX                                             0x567a
5477  #define mmDIG8_DIG_TEST_DEBUG_INDEX                                             0x577a
5478  #define mmDIG_TEST_DEBUG_DATA                                                   0x4a7b
5479  #define mmDIG0_DIG_TEST_DEBUG_DATA                                              0x4a7b
5480  #define mmDIG1_DIG_TEST_DEBUG_DATA                                              0x4b7b
5481  #define mmDIG2_DIG_TEST_DEBUG_DATA                                              0x4c7b
5482  #define mmDIG3_DIG_TEST_DEBUG_DATA                                              0x4d7b
5483  #define mmDIG4_DIG_TEST_DEBUG_DATA                                              0x4e7b
5484  #define mmDIG5_DIG_TEST_DEBUG_DATA                                              0x4f7b
5485  #define mmDIG6_DIG_TEST_DEBUG_DATA                                              0x547b
5486  #define mmDIG7_DIG_TEST_DEBUG_DATA                                              0x567b
5487  #define mmDIG8_DIG_TEST_DEBUG_DATA                                              0x577b
5488  #define mmDIG_FE_TEST_DEBUG_INDEX                                               0x4a7c
5489  #define mmDIG0_DIG_FE_TEST_DEBUG_INDEX                                          0x4a7c
5490  #define mmDIG1_DIG_FE_TEST_DEBUG_INDEX                                          0x4b7c
5491  #define mmDIG2_DIG_FE_TEST_DEBUG_INDEX                                          0x4c7c
5492  #define mmDIG3_DIG_FE_TEST_DEBUG_INDEX                                          0x4d7c
5493  #define mmDIG4_DIG_FE_TEST_DEBUG_INDEX                                          0x4e7c
5494  #define mmDIG5_DIG_FE_TEST_DEBUG_INDEX                                          0x4f7c
5495  #define mmDIG6_DIG_FE_TEST_DEBUG_INDEX                                          0x547c
5496  #define mmDIG7_DIG_FE_TEST_DEBUG_INDEX                                          0x567c
5497  #define mmDIG8_DIG_FE_TEST_DEBUG_INDEX                                          0x577c
5498  #define mmDIG_FE_TEST_DEBUG_DATA                                                0x4a7d
5499  #define mmDIG0_DIG_FE_TEST_DEBUG_DATA                                           0x4a7d
5500  #define mmDIG1_DIG_FE_TEST_DEBUG_DATA                                           0x4b7d
5501  #define mmDIG2_DIG_FE_TEST_DEBUG_DATA                                           0x4c7d
5502  #define mmDIG3_DIG_FE_TEST_DEBUG_DATA                                           0x4d7d
5503  #define mmDIG4_DIG_FE_TEST_DEBUG_DATA                                           0x4e7d
5504  #define mmDIG5_DIG_FE_TEST_DEBUG_DATA                                           0x4f7d
5505  #define mmDIG6_DIG_FE_TEST_DEBUG_DATA                                           0x547d
5506  #define mmDIG7_DIG_FE_TEST_DEBUG_DATA                                           0x567d
5507  #define mmDIG8_DIG_FE_TEST_DEBUG_DATA                                           0x577d
5508  #define mmDMCU_CTRL                                                             0x1600
5509  #define mmDMCU_STATUS                                                           0x1601
5510  #define mmDMCU_PC_START_ADDR                                                    0x1602
5511  #define mmDMCU_FW_START_ADDR                                                    0x1603
5512  #define mmDMCU_FW_END_ADDR                                                      0x1604
5513  #define mmDMCU_FW_ISR_START_ADDR                                                0x1605
5514  #define mmDMCU_FW_CS_HI                                                         0x1606
5515  #define mmDMCU_FW_CS_LO                                                         0x1607
5516  #define mmDMCU_RAM_ACCESS_CTRL                                                  0x1608
5517  #define mmDMCU_ERAM_WR_CTRL                                                     0x1609
5518  #define mmDMCU_ERAM_WR_DATA                                                     0x160a
5519  #define mmDMCU_ERAM_RD_CTRL                                                     0x160b
5520  #define mmDMCU_ERAM_RD_DATA                                                     0x160c
5521  #define mmDMCU_IRAM_WR_CTRL                                                     0x160d
5522  #define mmDMCU_IRAM_WR_DATA                                                     0x160e
5523  #define mmDMCU_IRAM_RD_CTRL                                                     0x160f
5524  #define mmDMCU_IRAM_RD_DATA                                                     0x1610
5525  #define mmDMCU_EVENT_TRIGGER                                                    0x1611
5526  #define mmDMCU_UC_INTERNAL_INT_STATUS                                           0x1612
5527  #define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                         0x1613
5528  #define mmDMCU_INTERRUPT_STATUS                                                 0x1614
5529  #define mmDMCU_INTERRUPT_STATUS_1                                               0x1633
5530  #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                        0x1615
5531  #define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                          0x1616
5532  #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                        0x1631
5533  #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                     0x1617
5534  #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                   0x1632
5535  #define mmDC_DMCU_SCRATCH                                                       0x1618
5536  #define mmDMCU_INT_CNT                                                          0x1619
5537  #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                        0x161a
5538  #define mmDMCU_UC_CLK_GATING_CNTL                                               0x161b
5539  #define mmMASTER_COMM_DATA_REG1                                                 0x161c
5540  #define mmMASTER_COMM_DATA_REG2                                                 0x161d
5541  #define mmMASTER_COMM_DATA_REG3                                                 0x161e
5542  #define mmMASTER_COMM_CMD_REG                                                   0x161f
5543  #define mmMASTER_COMM_CNTL_REG                                                  0x1620
5544  #define mmSLAVE_COMM_DATA_REG1                                                  0x1621
5545  #define mmSLAVE_COMM_DATA_REG2                                                  0x1622
5546  #define mmSLAVE_COMM_DATA_REG3                                                  0x1623
5547  #define mmSLAVE_COMM_CMD_REG                                                    0x1624
5548  #define mmSLAVE_COMM_CNTL_REG                                                   0x1625
5549  #define mmDMCU_TEST_DEBUG_INDEX                                                 0x1626
5550  #define mmDMCU_TEST_DEBUG_DATA                                                  0x1627
5551  #define mmDMCU_PERFMON_INTERRUPT_STATUS1                                        0x1644
5552  #define mmDMCU_PERFMON_INTERRUPT_STATUS2                                        0x1645
5553  #define mmDMCU_PERFMON_INTERRUPT_STATUS3                                        0x1646
5554  #define mmDMCU_PERFMON_INTERRUPT_STATUS4                                        0x1647
5555  #define mmDMCU_PERFMON_INTERRUPT_STATUS5                                        0x1642
5556  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                 0x1674
5557  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                 0x1675
5558  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                 0x1676
5559  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                 0x1677
5560  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                 0x1643
5561  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                            0x1678
5562  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                            0x1679
5563  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                            0x167a
5564  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                            0x167b
5565  #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                            0x1673
5566  #define mmDMCU_DPRX_INTERRUPT_STATUS1                                           0x1634
5567  #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                    0x1635
5568  #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                               0x1636
5569  #define mmDP_LINK_CNTL                                                          0x4aa0
5570  #define mmDP0_DP_LINK_CNTL                                                      0x4aa0
5571  #define mmDP1_DP_LINK_CNTL                                                      0x4ba0
5572  #define mmDP2_DP_LINK_CNTL                                                      0x4ca0
5573  #define mmDP3_DP_LINK_CNTL                                                      0x4da0
5574  #define mmDP4_DP_LINK_CNTL                                                      0x4ea0
5575  #define mmDP5_DP_LINK_CNTL                                                      0x4fa0
5576  #define mmDP6_DP_LINK_CNTL                                                      0x54a0
5577  #define mmDP7_DP_LINK_CNTL                                                      0x56a0
5578  #define mmDP8_DP_LINK_CNTL                                                      0x57a0
5579  #define mmDP_PIXEL_FORMAT                                                       0x4aa1
5580  #define mmDP0_DP_PIXEL_FORMAT                                                   0x4aa1
5581  #define mmDP1_DP_PIXEL_FORMAT                                                   0x4ba1
5582  #define mmDP2_DP_PIXEL_FORMAT                                                   0x4ca1
5583  #define mmDP3_DP_PIXEL_FORMAT                                                   0x4da1
5584  #define mmDP4_DP_PIXEL_FORMAT                                                   0x4ea1
5585  #define mmDP5_DP_PIXEL_FORMAT                                                   0x4fa1
5586  #define mmDP6_DP_PIXEL_FORMAT                                                   0x54a1
5587  #define mmDP7_DP_PIXEL_FORMAT                                                   0x56a1
5588  #define mmDP8_DP_PIXEL_FORMAT                                                   0x57a1
5589  #define mmDP_MSA_COLORIMETRY                                                    0x4aa2
5590  #define mmDP0_DP_MSA_COLORIMETRY                                                0x4aa2
5591  #define mmDP1_DP_MSA_COLORIMETRY                                                0x4ba2
5592  #define mmDP2_DP_MSA_COLORIMETRY                                                0x4ca2
5593  #define mmDP3_DP_MSA_COLORIMETRY                                                0x4da2
5594  #define mmDP4_DP_MSA_COLORIMETRY                                                0x4ea2
5595  #define mmDP5_DP_MSA_COLORIMETRY                                                0x4fa2
5596  #define mmDP6_DP_MSA_COLORIMETRY                                                0x54a2
5597  #define mmDP7_DP_MSA_COLORIMETRY                                                0x56a2
5598  #define mmDP8_DP_MSA_COLORIMETRY                                                0x57a2
5599  #define mmDP_CONFIG                                                             0x4aa3
5600  #define mmDP0_DP_CONFIG                                                         0x4aa3
5601  #define mmDP1_DP_CONFIG                                                         0x4ba3
5602  #define mmDP2_DP_CONFIG                                                         0x4ca3
5603  #define mmDP3_DP_CONFIG                                                         0x4da3
5604  #define mmDP4_DP_CONFIG                                                         0x4ea3
5605  #define mmDP5_DP_CONFIG                                                         0x4fa3
5606  #define mmDP6_DP_CONFIG                                                         0x54a3
5607  #define mmDP7_DP_CONFIG                                                         0x56a3
5608  #define mmDP8_DP_CONFIG                                                         0x57a3
5609  #define mmDP_VID_STREAM_CNTL                                                    0x4aa4
5610  #define mmDP0_DP_VID_STREAM_CNTL                                                0x4aa4
5611  #define mmDP1_DP_VID_STREAM_CNTL                                                0x4ba4
5612  #define mmDP2_DP_VID_STREAM_CNTL                                                0x4ca4
5613  #define mmDP3_DP_VID_STREAM_CNTL                                                0x4da4
5614  #define mmDP4_DP_VID_STREAM_CNTL                                                0x4ea4
5615  #define mmDP5_DP_VID_STREAM_CNTL                                                0x4fa4
5616  #define mmDP6_DP_VID_STREAM_CNTL                                                0x54a4
5617  #define mmDP7_DP_VID_STREAM_CNTL                                                0x56a4
5618  #define mmDP8_DP_VID_STREAM_CNTL                                                0x57a4
5619  #define mmDP_STEER_FIFO                                                         0x4aa5
5620  #define mmDP0_DP_STEER_FIFO                                                     0x4aa5
5621  #define mmDP1_DP_STEER_FIFO                                                     0x4ba5
5622  #define mmDP2_DP_STEER_FIFO                                                     0x4ca5
5623  #define mmDP3_DP_STEER_FIFO                                                     0x4da5
5624  #define mmDP4_DP_STEER_FIFO                                                     0x4ea5
5625  #define mmDP5_DP_STEER_FIFO                                                     0x4fa5
5626  #define mmDP6_DP_STEER_FIFO                                                     0x54a5
5627  #define mmDP7_DP_STEER_FIFO                                                     0x56a5
5628  #define mmDP8_DP_STEER_FIFO                                                     0x57a5
5629  #define mmDP_MSA_MISC                                                           0x4aa6
5630  #define mmDP0_DP_MSA_MISC                                                       0x4aa6
5631  #define mmDP1_DP_MSA_MISC                                                       0x4ba6
5632  #define mmDP2_DP_MSA_MISC                                                       0x4ca6
5633  #define mmDP3_DP_MSA_MISC                                                       0x4da6
5634  #define mmDP4_DP_MSA_MISC                                                       0x4ea6
5635  #define mmDP5_DP_MSA_MISC                                                       0x4fa6
5636  #define mmDP6_DP_MSA_MISC                                                       0x54a6
5637  #define mmDP7_DP_MSA_MISC                                                       0x56a6
5638  #define mmDP8_DP_MSA_MISC                                                       0x57a6
5639  #define mmDP_VID_TIMING                                                         0x4aa8
5640  #define mmDP0_DP_VID_TIMING                                                     0x4aa8
5641  #define mmDP1_DP_VID_TIMING                                                     0x4ba8
5642  #define mmDP2_DP_VID_TIMING                                                     0x4ca8
5643  #define mmDP3_DP_VID_TIMING                                                     0x4da8
5644  #define mmDP4_DP_VID_TIMING                                                     0x4ea8
5645  #define mmDP5_DP_VID_TIMING                                                     0x4fa8
5646  #define mmDP6_DP_VID_TIMING                                                     0x54a8
5647  #define mmDP7_DP_VID_TIMING                                                     0x56a8
5648  #define mmDP8_DP_VID_TIMING                                                     0x57a8
5649  #define mmDP_VID_N                                                              0x4aa9
5650  #define mmDP0_DP_VID_N                                                          0x4aa9
5651  #define mmDP1_DP_VID_N                                                          0x4ba9
5652  #define mmDP2_DP_VID_N                                                          0x4ca9
5653  #define mmDP3_DP_VID_N                                                          0x4da9
5654  #define mmDP4_DP_VID_N                                                          0x4ea9
5655  #define mmDP5_DP_VID_N                                                          0x4fa9
5656  #define mmDP6_DP_VID_N                                                          0x54a9
5657  #define mmDP7_DP_VID_N                                                          0x56a9
5658  #define mmDP8_DP_VID_N                                                          0x57a9
5659  #define mmDP_VID_M                                                              0x4aaa
5660  #define mmDP0_DP_VID_M                                                          0x4aaa
5661  #define mmDP1_DP_VID_M                                                          0x4baa
5662  #define mmDP2_DP_VID_M                                                          0x4caa
5663  #define mmDP3_DP_VID_M                                                          0x4daa
5664  #define mmDP4_DP_VID_M                                                          0x4eaa
5665  #define mmDP5_DP_VID_M                                                          0x4faa
5666  #define mmDP6_DP_VID_M                                                          0x54aa
5667  #define mmDP7_DP_VID_M                                                          0x56aa
5668  #define mmDP8_DP_VID_M                                                          0x57aa
5669  #define mmDP_LINK_FRAMING_CNTL                                                  0x4aab
5670  #define mmDP0_DP_LINK_FRAMING_CNTL                                              0x4aab
5671  #define mmDP1_DP_LINK_FRAMING_CNTL                                              0x4bab
5672  #define mmDP2_DP_LINK_FRAMING_CNTL                                              0x4cab
5673  #define mmDP3_DP_LINK_FRAMING_CNTL                                              0x4dab
5674  #define mmDP4_DP_LINK_FRAMING_CNTL                                              0x4eab
5675  #define mmDP5_DP_LINK_FRAMING_CNTL                                              0x4fab
5676  #define mmDP6_DP_LINK_FRAMING_CNTL                                              0x54ab
5677  #define mmDP7_DP_LINK_FRAMING_CNTL                                              0x56ab
5678  #define mmDP8_DP_LINK_FRAMING_CNTL                                              0x57ab
5679  #define mmDP_HBR2_EYE_PATTERN                                                   0x4aac
5680  #define mmDP0_DP_HBR2_EYE_PATTERN                                               0x4aac
5681  #define mmDP1_DP_HBR2_EYE_PATTERN                                               0x4bac
5682  #define mmDP2_DP_HBR2_EYE_PATTERN                                               0x4cac
5683  #define mmDP3_DP_HBR2_EYE_PATTERN                                               0x4dac
5684  #define mmDP4_DP_HBR2_EYE_PATTERN                                               0x4eac
5685  #define mmDP5_DP_HBR2_EYE_PATTERN                                               0x4fac
5686  #define mmDP6_DP_HBR2_EYE_PATTERN                                               0x54ac
5687  #define mmDP7_DP_HBR2_EYE_PATTERN                                               0x56ac
5688  #define mmDP8_DP_HBR2_EYE_PATTERN                                               0x57ac
5689  #define mmDP_VID_MSA_VBID                                                       0x4aad
5690  #define mmDP0_DP_VID_MSA_VBID                                                   0x4aad
5691  #define mmDP1_DP_VID_MSA_VBID                                                   0x4bad
5692  #define mmDP2_DP_VID_MSA_VBID                                                   0x4cad
5693  #define mmDP3_DP_VID_MSA_VBID                                                   0x4dad
5694  #define mmDP4_DP_VID_MSA_VBID                                                   0x4ead
5695  #define mmDP5_DP_VID_MSA_VBID                                                   0x4fad
5696  #define mmDP6_DP_VID_MSA_VBID                                                   0x54ad
5697  #define mmDP7_DP_VID_MSA_VBID                                                   0x56ad
5698  #define mmDP8_DP_VID_MSA_VBID                                                   0x57ad
5699  #define mmDP_VID_INTERRUPT_CNTL                                                 0x4aae
5700  #define mmDP0_DP_VID_INTERRUPT_CNTL                                             0x4aae
5701  #define mmDP1_DP_VID_INTERRUPT_CNTL                                             0x4bae
5702  #define mmDP2_DP_VID_INTERRUPT_CNTL                                             0x4cae
5703  #define mmDP3_DP_VID_INTERRUPT_CNTL                                             0x4dae
5704  #define mmDP4_DP_VID_INTERRUPT_CNTL                                             0x4eae
5705  #define mmDP5_DP_VID_INTERRUPT_CNTL                                             0x4fae
5706  #define mmDP6_DP_VID_INTERRUPT_CNTL                                             0x54ae
5707  #define mmDP7_DP_VID_INTERRUPT_CNTL                                             0x56ae
5708  #define mmDP8_DP_VID_INTERRUPT_CNTL                                             0x57ae
5709  #define mmDP_DPHY_CNTL                                                          0x4aaf
5710  #define mmDP0_DP_DPHY_CNTL                                                      0x4aaf
5711  #define mmDP1_DP_DPHY_CNTL                                                      0x4baf
5712  #define mmDP2_DP_DPHY_CNTL                                                      0x4caf
5713  #define mmDP3_DP_DPHY_CNTL                                                      0x4daf
5714  #define mmDP4_DP_DPHY_CNTL                                                      0x4eaf
5715  #define mmDP5_DP_DPHY_CNTL                                                      0x4faf
5716  #define mmDP6_DP_DPHY_CNTL                                                      0x54af
5717  #define mmDP7_DP_DPHY_CNTL                                                      0x56af
5718  #define mmDP8_DP_DPHY_CNTL                                                      0x57af
5719  #define mmDP_DPHY_TRAINING_PATTERN_SEL                                          0x4ab0
5720  #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4ab0
5721  #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4bb0
5722  #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4cb0
5723  #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4db0
5724  #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4eb0
5725  #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                      0x4fb0
5726  #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                      0x54b0
5727  #define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL                                      0x56b0
5728  #define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL                                      0x57b0
5729  #define mmDP_DPHY_SYM0                                                          0x4ab1
5730  #define mmDP0_DP_DPHY_SYM0                                                      0x4ab1
5731  #define mmDP1_DP_DPHY_SYM0                                                      0x4bb1
5732  #define mmDP2_DP_DPHY_SYM0                                                      0x4cb1
5733  #define mmDP3_DP_DPHY_SYM0                                                      0x4db1
5734  #define mmDP4_DP_DPHY_SYM0                                                      0x4eb1
5735  #define mmDP5_DP_DPHY_SYM0                                                      0x4fb1
5736  #define mmDP6_DP_DPHY_SYM0                                                      0x54b1
5737  #define mmDP7_DP_DPHY_SYM0                                                      0x56b1
5738  #define mmDP8_DP_DPHY_SYM0                                                      0x57b1
5739  #define mmDP_DPHY_SYM1                                                          0x4ab2
5740  #define mmDP0_DP_DPHY_SYM1                                                      0x4ab2
5741  #define mmDP1_DP_DPHY_SYM1                                                      0x4bb2
5742  #define mmDP2_DP_DPHY_SYM1                                                      0x4cb2
5743  #define mmDP3_DP_DPHY_SYM1                                                      0x4db2
5744  #define mmDP4_DP_DPHY_SYM1                                                      0x4eb2
5745  #define mmDP5_DP_DPHY_SYM1                                                      0x4fb2
5746  #define mmDP6_DP_DPHY_SYM1                                                      0x54b2
5747  #define mmDP7_DP_DPHY_SYM1                                                      0x56b2
5748  #define mmDP8_DP_DPHY_SYM1                                                      0x57b2
5749  #define mmDP_DPHY_SYM2                                                          0x4ab3
5750  #define mmDP0_DP_DPHY_SYM2                                                      0x4ab3
5751  #define mmDP1_DP_DPHY_SYM2                                                      0x4bb3
5752  #define mmDP2_DP_DPHY_SYM2                                                      0x4cb3
5753  #define mmDP3_DP_DPHY_SYM2                                                      0x4db3
5754  #define mmDP4_DP_DPHY_SYM2                                                      0x4eb3
5755  #define mmDP5_DP_DPHY_SYM2                                                      0x4fb3
5756  #define mmDP6_DP_DPHY_SYM2                                                      0x54b3
5757  #define mmDP7_DP_DPHY_SYM2                                                      0x56b3
5758  #define mmDP8_DP_DPHY_SYM2                                                      0x57b3
5759  #define mmDP_DPHY_8B10B_CNTL                                                    0x4ab4
5760  #define mmDP0_DP_DPHY_8B10B_CNTL                                                0x4ab4
5761  #define mmDP1_DP_DPHY_8B10B_CNTL                                                0x4bb4
5762  #define mmDP2_DP_DPHY_8B10B_CNTL                                                0x4cb4
5763  #define mmDP3_DP_DPHY_8B10B_CNTL                                                0x4db4
5764  #define mmDP4_DP_DPHY_8B10B_CNTL                                                0x4eb4
5765  #define mmDP5_DP_DPHY_8B10B_CNTL                                                0x4fb4
5766  #define mmDP6_DP_DPHY_8B10B_CNTL                                                0x54b4
5767  #define mmDP7_DP_DPHY_8B10B_CNTL                                                0x56b4
5768  #define mmDP8_DP_DPHY_8B10B_CNTL                                                0x57b4
5769  #define mmDP_DPHY_PRBS_CNTL                                                     0x4ab5
5770  #define mmDP0_DP_DPHY_PRBS_CNTL                                                 0x4ab5
5771  #define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
5772  #define mmDP2_DP_DPHY_PRBS_CNTL                                                 0x4cb5
5773  #define mmDP3_DP_DPHY_PRBS_CNTL                                                 0x4db5
5774  #define mmDP4_DP_DPHY_PRBS_CNTL                                                 0x4eb5
5775  #define mmDP5_DP_DPHY_PRBS_CNTL                                                 0x4fb5
5776  #define mmDP6_DP_DPHY_PRBS_CNTL                                                 0x54b5
5777  #define mmDP7_DP_DPHY_PRBS_CNTL                                                 0x56b5
5778  #define mmDP8_DP_DPHY_PRBS_CNTL                                                 0x57b5
5779  #define mmDP_DPHY_SCRAM_CNTL                                                    0x4ab6
5780  #define mmDP0_DP_DPHY_SCRAM_CNTL                                                0x4ab6
5781  #define mmDP1_DP_DPHY_SCRAM_CNTL                                                0x4bb6
5782  #define mmDP2_DP_DPHY_SCRAM_CNTL                                                0x4cb6
5783  #define mmDP3_DP_DPHY_SCRAM_CNTL                                                0x4db6
5784  #define mmDP4_DP_DPHY_SCRAM_CNTL                                                0x4eb6
5785  #define mmDP5_DP_DPHY_SCRAM_CNTL                                                0x4fb6
5786  #define mmDP6_DP_DPHY_SCRAM_CNTL                                                0x54b6
5787  #define mmDP8_DP_DPHY_SCRAM_CNTL                                                0x56b6
5788  #define mmDP_DPHY_BS_SR_SWAP_CNTL                                               0x4adc
5789  #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4adc
5790  #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4bdc
5791  #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4cdc
5792  #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4ddc
5793  #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4edc
5794  #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                                           0x4fdc
5795  #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                                           0x54dc
5796  #define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL                                           0x56dc
5797  #define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL                                           0x57dc
5798  #define mmDP_DPHY_CRC_EN                                                        0x4ab7
5799  #define mmDP0_DP_DPHY_CRC_EN                                                    0x4ab7
5800  #define mmDP1_DP_DPHY_CRC_EN                                                    0x4bb7
5801  #define mmDP2_DP_DPHY_CRC_EN                                                    0x4cb7
5802  #define mmDP3_DP_DPHY_CRC_EN                                                    0x4db7
5803  #define mmDP4_DP_DPHY_CRC_EN                                                    0x4eb7
5804  #define mmDP5_DP_DPHY_CRC_EN                                                    0x4fb7
5805  #define mmDP6_DP_DPHY_CRC_EN                                                    0x54b7
5806  #define mmDP7_DP_DPHY_CRC_EN                                                    0x56b7
5807  #define mmDP8_DP_DPHY_CRC_EN                                                    0x57b7
5808  #define mmDP_DPHY_CRC_CNTL                                                      0x4ab8
5809  #define mmDP0_DP_DPHY_CRC_CNTL                                                  0x4ab8
5810  #define mmDP1_DP_DPHY_CRC_CNTL                                                  0x4bb8
5811  #define mmDP2_DP_DPHY_CRC_CNTL                                                  0x4cb8
5812  #define mmDP3_DP_DPHY_CRC_CNTL                                                  0x4db8
5813  #define mmDP4_DP_DPHY_CRC_CNTL                                                  0x4eb8
5814  #define mmDP5_DP_DPHY_CRC_CNTL                                                  0x4fb8
5815  #define mmDP6_DP_DPHY_CRC_CNTL                                                  0x54b8
5816  #define mmDP7_DP_DPHY_CRC_CNTL                                                  0x56b8
5817  #define mmDP8_DP_DPHY_CRC_CNTL                                                  0x57b8
5818  #define mmDP_DPHY_CRC_RESULT                                                    0x4ab9
5819  #define mmDP0_DP_DPHY_CRC_RESULT                                                0x4ab9
5820  #define mmDP1_DP_DPHY_CRC_RESULT                                                0x4bb9
5821  #define mmDP2_DP_DPHY_CRC_RESULT                                                0x4cb9
5822  #define mmDP3_DP_DPHY_CRC_RESULT                                                0x4db9
5823  #define mmDP4_DP_DPHY_CRC_RESULT                                                0x4eb9
5824  #define mmDP5_DP_DPHY_CRC_RESULT                                                0x4fb9
5825  #define mmDP6_DP_DPHY_CRC_RESULT                                                0x54b9
5826  #define mmDP7_DP_DPHY_CRC_RESULT                                                0x56b9
5827  #define mmDP8_DP_DPHY_CRC_RESULT                                                0x57b9
5828  #define mmDP_DPHY_CRC_MST_CNTL                                                  0x4aba
5829  #define mmDP0_DP_DPHY_CRC_MST_CNTL                                              0x4aba
5830  #define mmDP1_DP_DPHY_CRC_MST_CNTL                                              0x4bba
5831  #define mmDP2_DP_DPHY_CRC_MST_CNTL                                              0x4cba
5832  #define mmDP3_DP_DPHY_CRC_MST_CNTL                                              0x4dba
5833  #define mmDP4_DP_DPHY_CRC_MST_CNTL                                              0x4eba
5834  #define mmDP5_DP_DPHY_CRC_MST_CNTL                                              0x4fba
5835  #define mmDP6_DP_DPHY_CRC_MST_CNTL                                              0x54ba
5836  #define mmDP7_DP_DPHY_CRC_MST_CNTL                                              0x56ba
5837  #define mmDP8_DP_DPHY_CRC_MST_CNTL                                              0x57ba
5838  #define mmDP_DPHY_CRC_MST_STATUS                                                0x4abb
5839  #define mmDP0_DP_DPHY_CRC_MST_STATUS                                            0x4abb
5840  #define mmDP1_DP_DPHY_CRC_MST_STATUS                                            0x4bbb
5841  #define mmDP2_DP_DPHY_CRC_MST_STATUS                                            0x4cbb
5842  #define mmDP3_DP_DPHY_CRC_MST_STATUS                                            0x4dbb
5843  #define mmDP4_DP_DPHY_CRC_MST_STATUS                                            0x4ebb
5844  #define mmDP5_DP_DPHY_CRC_MST_STATUS                                            0x4fbb
5845  #define mmDP6_DP_DPHY_CRC_MST_STATUS                                            0x54bb
5846  #define mmDP7_DP_DPHY_CRC_MST_STATUS                                            0x56bb
5847  #define mmDP8_DP_DPHY_CRC_MST_STATUS                                            0x57bb
5848  #define mmDP_DPHY_FAST_TRAINING                                                 0x4abc
5849  #define mmDP0_DP_DPHY_FAST_TRAINING                                             0x4abc
5850  #define mmDP1_DP_DPHY_FAST_TRAINING                                             0x4bbc
5851  #define mmDP2_DP_DPHY_FAST_TRAINING                                             0x4cbc
5852  #define mmDP3_DP_DPHY_FAST_TRAINING                                             0x4dbc
5853  #define mmDP4_DP_DPHY_FAST_TRAINING                                             0x4ebc
5854  #define mmDP5_DP_DPHY_FAST_TRAINING                                             0x4fbc
5855  #define mmDP6_DP_DPHY_FAST_TRAINING                                             0x54bc
5856  #define mmDP7_DP_DPHY_FAST_TRAINING                                             0x56bc
5857  #define mmDP8_DP_DPHY_FAST_TRAINING                                             0x57bc
5858  #define mmDP_DPHY_FAST_TRAINING_STATUS                                          0x4abd
5859  #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                      0x4abd
5860  #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                      0x4bbd
5861  #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                      0x4cbd
5862  #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                      0x4dbd
5863  #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                      0x4ebd
5864  #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                      0x4fbd
5865  #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                      0x54bd
5866  #define mmDP7_DP_DPHY_FAST_TRAINING_STATUS                                      0x56bd
5867  #define mmDP8_DP_DPHY_FAST_TRAINING_STATUS                                      0x57bd
5868  #define mmDP_DPHY_HBR2_PATTERN_CONTROL                                          0x4add
5869  #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4add
5870  #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4bdd
5871  #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4cdd
5872  #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4ddd
5873  #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4edd
5874  #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4fdd
5875  #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x54dd
5876  #define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x56dd
5877  #define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x57dd
5878  #define mmDP_MSA_V_TIMING_OVERRIDE1                                             0x4abe
5879  #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                         0x4abe
5880  #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                         0x4bbe
5881  #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                         0x4cbe
5882  #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                         0x4dbe
5883  #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                         0x4ebe
5884  #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                         0x4fbe
5885  #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                         0x54be
5886  #define mmDP7_DP_MSA_V_TIMING_OVERRIDE1                                         0x56be
5887  #define mmDP8_DP_MSA_V_TIMING_OVERRIDE1                                         0x57be
5888  #define mmDP_MSA_V_TIMING_OVERRIDE2                                             0x4abf
5889  #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                         0x4abf
5890  #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                         0x4bbf
5891  #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                         0x4cbf
5892  #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                         0x4dbf
5893  #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                         0x4ebf
5894  #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                         0x4fbf
5895  #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                         0x54bf
5896  #define mmDP7_DP_MSA_V_TIMING_OVERRIDE2                                         0x56bf
5897  #define mmDP8_DP_MSA_V_TIMING_OVERRIDE2                                         0x57bf
5898  #define mmDP_SEC_CNTL                                                           0x4ac3
5899  #define mmDP0_DP_SEC_CNTL                                                       0x4ac3
5900  #define mmDP1_DP_SEC_CNTL                                                       0x4bc3
5901  #define mmDP2_DP_SEC_CNTL                                                       0x4cc3
5902  #define mmDP3_DP_SEC_CNTL                                                       0x4dc3
5903  #define mmDP4_DP_SEC_CNTL                                                       0x4ec3
5904  #define mmDP5_DP_SEC_CNTL                                                       0x4fc3
5905  #define mmDP6_DP_SEC_CNTL                                                       0x54c3
5906  #define mmDP7_DP_SEC_CNTL                                                       0x56c3
5907  #define mmDP8_DP_SEC_CNTL                                                       0x57c3
5908  #define mmDP_SEC_CNTL1                                                          0x4ac4
5909  #define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
5910  #define mmDP1_DP_SEC_CNTL1                                                      0x4bc4
5911  #define mmDP2_DP_SEC_CNTL1                                                      0x4cc4
5912  #define mmDP3_DP_SEC_CNTL1                                                      0x4dc4
5913  #define mmDP4_DP_SEC_CNTL1                                                      0x4ec4
5914  #define mmDP5_DP_SEC_CNTL1                                                      0x4fc4
5915  #define mmDP6_DP_SEC_CNTL1                                                      0x54c4
5916  #define mmDP7_DP_SEC_CNTL1                                                      0x56c4
5917  #define mmDP8_DP_SEC_CNTL1                                                      0x57c4
5918  #define mmDP_SEC_FRAMING1                                                       0x4ac5
5919  #define mmDP0_DP_SEC_FRAMING1                                                   0x4ac5
5920  #define mmDP1_DP_SEC_FRAMING1                                                   0x4bc5
5921  #define mmDP2_DP_SEC_FRAMING1                                                   0x4cc5
5922  #define mmDP3_DP_SEC_FRAMING1                                                   0x4dc5
5923  #define mmDP4_DP_SEC_FRAMING1                                                   0x4ec5
5924  #define mmDP5_DP_SEC_FRAMING1                                                   0x4fc5
5925  #define mmDP6_DP_SEC_FRAMING1                                                   0x54c5
5926  #define mmDP7_DP_SEC_FRAMING1                                                   0x56c5
5927  #define mmDP8_DP_SEC_FRAMING1                                                   0x57c5
5928  #define mmDP_SEC_FRAMING2                                                       0x4ac6
5929  #define mmDP0_DP_SEC_FRAMING2                                                   0x4ac6
5930  #define mmDP1_DP_SEC_FRAMING2                                                   0x4bc6
5931  #define mmDP2_DP_SEC_FRAMING2                                                   0x4cc6
5932  #define mmDP3_DP_SEC_FRAMING2                                                   0x4dc6
5933  #define mmDP4_DP_SEC_FRAMING2                                                   0x4ec6
5934  #define mmDP5_DP_SEC_FRAMING2                                                   0x4fc6
5935  #define mmDP6_DP_SEC_FRAMING2                                                   0x54c6
5936  #define mmDP7_DP_SEC_FRAMING2                                                   0x56c6
5937  #define mmDP8_DP_SEC_FRAMING2                                                   0x57c6
5938  #define mmDP_SEC_FRAMING3                                                       0x4ac7
5939  #define mmDP0_DP_SEC_FRAMING3                                                   0x4ac7
5940  #define mmDP1_DP_SEC_FRAMING3                                                   0x4bc7
5941  #define mmDP2_DP_SEC_FRAMING3                                                   0x4cc7
5942  #define mmDP3_DP_SEC_FRAMING3                                                   0x4dc7
5943  #define mmDP4_DP_SEC_FRAMING3                                                   0x4ec7
5944  #define mmDP5_DP_SEC_FRAMING3                                                   0x4fc7
5945  #define mmDP6_DP_SEC_FRAMING3                                                   0x54c7
5946  #define mmDP7_DP_SEC_FRAMING3                                                   0x56c7
5947  #define mmDP8_DP_SEC_FRAMING3                                                   0x57c7
5948  #define mmDP_SEC_FRAMING4                                                       0x4ac8
5949  #define mmDP0_DP_SEC_FRAMING4                                                   0x4ac8
5950  #define mmDP1_DP_SEC_FRAMING4                                                   0x4bc8
5951  #define mmDP2_DP_SEC_FRAMING4                                                   0x4cc8
5952  #define mmDP3_DP_SEC_FRAMING4                                                   0x4dc8
5953  #define mmDP4_DP_SEC_FRAMING4                                                   0x4ec8
5954  #define mmDP5_DP_SEC_FRAMING4                                                   0x4fc8
5955  #define mmDP6_DP_SEC_FRAMING4                                                   0x54c8
5956  #define mmDP7_DP_SEC_FRAMING4                                                   0x56c8
5957  #define mmDP8_DP_SEC_FRAMING4                                                   0x57c8
5958  #define mmDP_SEC_AUD_N                                                          0x4ac9
5959  #define mmDP0_DP_SEC_AUD_N                                                      0x4ac9
5960  #define mmDP1_DP_SEC_AUD_N                                                      0x4bc9
5961  #define mmDP2_DP_SEC_AUD_N                                                      0x4cc9
5962  #define mmDP3_DP_SEC_AUD_N                                                      0x4dc9
5963  #define mmDP4_DP_SEC_AUD_N                                                      0x4ec9
5964  #define mmDP5_DP_SEC_AUD_N                                                      0x4fc9
5965  #define mmDP6_DP_SEC_AUD_N                                                      0x54c9
5966  #define mmDP7_DP_SEC_AUD_N                                                      0x56c9
5967  #define mmDP8_DP_SEC_AUD_N                                                      0x57c9
5968  #define mmDP_SEC_AUD_N_READBACK                                                 0x4aca
5969  #define mmDP0_DP_SEC_AUD_N_READBACK                                             0x4aca
5970  #define mmDP1_DP_SEC_AUD_N_READBACK                                             0x4bca
5971  #define mmDP2_DP_SEC_AUD_N_READBACK                                             0x4cca
5972  #define mmDP3_DP_SEC_AUD_N_READBACK                                             0x4dca
5973  #define mmDP4_DP_SEC_AUD_N_READBACK                                             0x4eca
5974  #define mmDP5_DP_SEC_AUD_N_READBACK                                             0x4fca
5975  #define mmDP6_DP_SEC_AUD_N_READBACK                                             0x54ca
5976  #define mmDP7_DP_SEC_AUD_N_READBACK                                             0x56ca
5977  #define mmDP8_DP_SEC_AUD_N_READBACK                                             0x57ca
5978  #define mmDP_SEC_AUD_M                                                          0x4acb
5979  #define mmDP0_DP_SEC_AUD_M                                                      0x4acb
5980  #define mmDP1_DP_SEC_AUD_M                                                      0x4bcb
5981  #define mmDP2_DP_SEC_AUD_M                                                      0x4ccb
5982  #define mmDP3_DP_SEC_AUD_M                                                      0x4dcb
5983  #define mmDP4_DP_SEC_AUD_M                                                      0x4ecb
5984  #define mmDP5_DP_SEC_AUD_M                                                      0x4fcb
5985  #define mmDP6_DP_SEC_AUD_M                                                      0x54cb
5986  #define mmDP7_DP_SEC_AUD_M                                                      0x56cb
5987  #define mmDP8_DP_SEC_AUD_M                                                      0x57cb
5988  #define mmDP_SEC_AUD_M_READBACK                                                 0x4acc
5989  #define mmDP0_DP_SEC_AUD_M_READBACK                                             0x4acc
5990  #define mmDP1_DP_SEC_AUD_M_READBACK                                             0x4bcc
5991  #define mmDP2_DP_SEC_AUD_M_READBACK                                             0x4ccc
5992  #define mmDP3_DP_SEC_AUD_M_READBACK                                             0x4dcc
5993  #define mmDP4_DP_SEC_AUD_M_READBACK                                             0x4ecc
5994  #define mmDP5_DP_SEC_AUD_M_READBACK                                             0x4fcc
5995  #define mmDP6_DP_SEC_AUD_M_READBACK                                             0x54cc
5996  #define mmDP7_DP_SEC_AUD_M_READBACK                                             0x56cc
5997  #define mmDP8_DP_SEC_AUD_M_READBACK                                             0x57cc
5998  #define mmDP_SEC_TIMESTAMP                                                      0x4acd
5999  #define mmDP0_DP_SEC_TIMESTAMP                                                  0x4acd
6000  #define mmDP1_DP_SEC_TIMESTAMP                                                  0x4bcd
6001  #define mmDP2_DP_SEC_TIMESTAMP                                                  0x4ccd
6002  #define mmDP3_DP_SEC_TIMESTAMP                                                  0x4dcd
6003  #define mmDP4_DP_SEC_TIMESTAMP                                                  0x4ecd
6004  #define mmDP5_DP_SEC_TIMESTAMP                                                  0x4fcd
6005  #define mmDP6_DP_SEC_TIMESTAMP                                                  0x54cd
6006  #define mmDP7_DP_SEC_TIMESTAMP                                                  0x56cd
6007  #define mmDP8_DP_SEC_TIMESTAMP                                                  0x57cd
6008  #define mmDP_SEC_PACKET_CNTL                                                    0x4ace
6009  #define mmDP0_DP_SEC_PACKET_CNTL                                                0x4ace
6010  #define mmDP1_DP_SEC_PACKET_CNTL                                                0x4bce
6011  #define mmDP2_DP_SEC_PACKET_CNTL                                                0x4cce
6012  #define mmDP3_DP_SEC_PACKET_CNTL                                                0x4dce
6013  #define mmDP4_DP_SEC_PACKET_CNTL                                                0x4ece
6014  #define mmDP5_DP_SEC_PACKET_CNTL                                                0x4fce
6015  #define mmDP6_DP_SEC_PACKET_CNTL                                                0x54ce
6016  #define mmDP7_DP_SEC_PACKET_CNTL                                                0x56ce
6017  #define mmDP8_DP_SEC_PACKET_CNTL                                                0x57ce
6018  #define mmDP_MSE_RATE_CNTL                                                      0x4acf
6019  #define mmDP0_DP_MSE_RATE_CNTL                                                  0x4acf
6020  #define mmDP1_DP_MSE_RATE_CNTL                                                  0x4bcf
6021  #define mmDP2_DP_MSE_RATE_CNTL                                                  0x4ccf
6022  #define mmDP3_DP_MSE_RATE_CNTL                                                  0x4dcf
6023  #define mmDP4_DP_MSE_RATE_CNTL                                                  0x4ecf
6024  #define mmDP5_DP_MSE_RATE_CNTL                                                  0x4fcf
6025  #define mmDP6_DP_MSE_RATE_CNTL                                                  0x54cf
6026  #define mmDP7_DP_MSE_RATE_CNTL                                                  0x56cf
6027  #define mmDP8_DP_MSE_RATE_CNTL                                                  0x57cf
6028  #define mmDP_MSE_RATE_UPDATE                                                    0x4ad1
6029  #define mmDP0_DP_MSE_RATE_UPDATE                                                0x4ad1
6030  #define mmDP1_DP_MSE_RATE_UPDATE                                                0x4bd1
6031  #define mmDP2_DP_MSE_RATE_UPDATE                                                0x4cd1
6032  #define mmDP3_DP_MSE_RATE_UPDATE                                                0x4dd1
6033  #define mmDP4_DP_MSE_RATE_UPDATE                                                0x4ed1
6034  #define mmDP5_DP_MSE_RATE_UPDATE                                                0x4fd1
6035  #define mmDP6_DP_MSE_RATE_UPDATE                                                0x54d1
6036  #define mmDP7_DP_MSE_RATE_UPDATE                                                0x56d1
6037  #define mmDP8_DP_MSE_RATE_UPDATE                                                0x57d1
6038  #define mmDP_MSE_SAT0                                                           0x4ad2
6039  #define mmDP0_DP_MSE_SAT0                                                       0x4ad2
6040  #define mmDP1_DP_MSE_SAT0                                                       0x4bd2
6041  #define mmDP2_DP_MSE_SAT0                                                       0x4cd2
6042  #define mmDP3_DP_MSE_SAT0                                                       0x4dd2
6043  #define mmDP4_DP_MSE_SAT0                                                       0x4ed2
6044  #define mmDP5_DP_MSE_SAT0                                                       0x4fd2
6045  #define mmDP6_DP_MSE_SAT0                                                       0x54d2
6046  #define mmDP7_DP_MSE_SAT0                                                       0x56d2
6047  #define mmDP8_DP_MSE_SAT0                                                       0x57d2
6048  #define mmDP_MSE_SAT1                                                           0x4ad3
6049  #define mmDP0_DP_MSE_SAT1                                                       0x4ad3
6050  #define mmDP1_DP_MSE_SAT1                                                       0x4bd3
6051  #define mmDP2_DP_MSE_SAT1                                                       0x4cd3
6052  #define mmDP3_DP_MSE_SAT1                                                       0x4dd3
6053  #define mmDP4_DP_MSE_SAT1                                                       0x4ed3
6054  #define mmDP5_DP_MSE_SAT1                                                       0x4fd3
6055  #define mmDP6_DP_MSE_SAT1                                                       0x54d3
6056  #define mmDP7_DP_MSE_SAT1                                                       0x56d3
6057  #define mmDP8_DP_MSE_SAT1                                                       0x57d3
6058  #define mmDP_MSE_SAT2                                                           0x4ad4
6059  #define mmDP0_DP_MSE_SAT2                                                       0x4ad4
6060  #define mmDP1_DP_MSE_SAT2                                                       0x4bd4
6061  #define mmDP2_DP_MSE_SAT2                                                       0x4cd4
6062  #define mmDP3_DP_MSE_SAT2                                                       0x4dd4
6063  #define mmDP4_DP_MSE_SAT2                                                       0x4ed4
6064  #define mmDP5_DP_MSE_SAT2                                                       0x4fd4
6065  #define mmDP6_DP_MSE_SAT2                                                       0x54d4
6066  #define mmDP7_DP_MSE_SAT2                                                       0x56d4
6067  #define mmDP8_DP_MSE_SAT2                                                       0x57d4
6068  #define mmDP_MSE_SAT_UPDATE                                                     0x4ad5
6069  #define mmDP0_DP_MSE_SAT_UPDATE                                                 0x4ad5
6070  #define mmDP1_DP_MSE_SAT_UPDATE                                                 0x4bd5
6071  #define mmDP2_DP_MSE_SAT_UPDATE                                                 0x4cd5
6072  #define mmDP3_DP_MSE_SAT_UPDATE                                                 0x4dd5
6073  #define mmDP4_DP_MSE_SAT_UPDATE                                                 0x4ed5
6074  #define mmDP5_DP_MSE_SAT_UPDATE                                                 0x4fd5
6075  #define mmDP6_DP_MSE_SAT_UPDATE                                                 0x54d5
6076  #define mmDP7_DP_MSE_SAT_UPDATE                                                 0x56d5
6077  #define mmDP8_DP_MSE_SAT_UPDATE                                                 0x57d5
6078  #define mmDP_MSE_LINK_TIMING                                                    0x4ad6
6079  #define mmDP0_DP_MSE_LINK_TIMING                                                0x4ad6
6080  #define mmDP1_DP_MSE_LINK_TIMING                                                0x4bd6
6081  #define mmDP2_DP_MSE_LINK_TIMING                                                0x4cd6
6082  #define mmDP3_DP_MSE_LINK_TIMING                                                0x4dd6
6083  #define mmDP4_DP_MSE_LINK_TIMING                                                0x4ed6
6084  #define mmDP5_DP_MSE_LINK_TIMING                                                0x4fd6
6085  #define mmDP6_DP_MSE_LINK_TIMING                                                0x54d6
6086  #define mmDP7_DP_MSE_LINK_TIMING                                                0x56d6
6087  #define mmDP8_DP_MSE_LINK_TIMING                                                0x57d6
6088  #define mmDP_MSE_MISC_CNTL                                                      0x4ad7
6089  #define mmDP0_DP_MSE_MISC_CNTL                                                  0x4ad7
6090  #define mmDP1_DP_MSE_MISC_CNTL                                                  0x4bd7
6091  #define mmDP2_DP_MSE_MISC_CNTL                                                  0x4cd7
6092  #define mmDP3_DP_MSE_MISC_CNTL                                                  0x4dd7
6093  #define mmDP4_DP_MSE_MISC_CNTL                                                  0x4ed7
6094  #define mmDP5_DP_MSE_MISC_CNTL                                                  0x4fd7
6095  #define mmDP6_DP_MSE_MISC_CNTL                                                  0x54d7
6096  #define mmDP7_DP_MSE_MISC_CNTL                                                  0x56d7
6097  #define mmDP8_DP_MSE_MISC_CNTL                                                  0x57d7
6098  #define mmDP_MSE_SAT0_STATUS                                                    0x4adf
6099  #define mmDP0_DP_MSE_SAT0_STATUS                                                0x4adf
6100  #define mmDP1_DP_MSE_SAT0_STATUS                                                0x4bdf
6101  #define mmDP2_DP_MSE_SAT0_STATUS                                                0x4cdf
6102  #define mmDP3_DP_MSE_SAT0_STATUS                                                0x4ddf
6103  #define mmDP4_DP_MSE_SAT0_STATUS                                                0x4edf
6104  #define mmDP5_DP_MSE_SAT0_STATUS                                                0x4fdf
6105  #define mmDP6_DP_MSE_SAT0_STATUS                                                0x54df
6106  #define mmDP7_DP_MSE_SAT0_STATUS                                                0x56df
6107  #define mmDP8_DP_MSE_SAT0_STATUS                                                0x57df
6108  #define mmDP_MSE_SAT1_STATUS                                                    0x4ae0
6109  #define mmDP0_DP_MSE_SAT1_STATUS                                                0x4ae0
6110  #define mmDP1_DP_MSE_SAT1_STATUS                                                0x4be0
6111  #define mmDP2_DP_MSE_SAT1_STATUS                                                0x4ce0
6112  #define mmDP3_DP_MSE_SAT1_STATUS                                                0x4de0
6113  #define mmDP4_DP_MSE_SAT1_STATUS                                                0x4ee0
6114  #define mmDP5_DP_MSE_SAT1_STATUS                                                0x4fe0
6115  #define mmDP6_DP_MSE_SAT1_STATUS                                                0x54e0
6116  #define mmDP7_DP_MSE_SAT1_STATUS                                                0x56e0
6117  #define mmDP8_DP_MSE_SAT1_STATUS                                                0x57e0
6118  #define mmDP_MSE_SAT2_STATUS                                                    0x4ae1
6119  #define mmDP0_DP_MSE_SAT2_STATUS                                                0x4ae1
6120  #define mmDP1_DP_MSE_SAT2_STATUS                                                0x4be1
6121  #define mmDP2_DP_MSE_SAT2_STATUS                                                0x4ce1
6122  #define mmDP3_DP_MSE_SAT2_STATUS                                                0x4de1
6123  #define mmDP4_DP_MSE_SAT2_STATUS                                                0x4ee1
6124  #define mmDP5_DP_MSE_SAT2_STATUS                                                0x4fe1
6125  #define mmDP6_DP_MSE_SAT2_STATUS                                                0x54e1
6126  #define mmDP7_DP_MSE_SAT2_STATUS                                                0x56e1
6127  #define mmDP8_DP_MSE_SAT2_STATUS                                                0x57e1
6128  #define mmDP_TEST_DEBUG_INDEX                                                   0x4ad8
6129  #define mmDP0_DP_TEST_DEBUG_INDEX                                               0x4ad8
6130  #define mmDP1_DP_TEST_DEBUG_INDEX                                               0x4bd8
6131  #define mmDP2_DP_TEST_DEBUG_INDEX                                               0x4cd8
6132  #define mmDP3_DP_TEST_DEBUG_INDEX                                               0x4dd8
6133  #define mmDP4_DP_TEST_DEBUG_INDEX                                               0x4ed8
6134  #define mmDP5_DP_TEST_DEBUG_INDEX                                               0x4fd8
6135  #define mmDP6_DP_TEST_DEBUG_INDEX                                               0x54d8
6136  #define mmDP7_DP_TEST_DEBUG_INDEX                                               0x56d8
6137  #define mmDP8_DP_TEST_DEBUG_INDEX                                               0x57d8
6138  #define mmDP_TEST_DEBUG_DATA                                                    0x4ad9
6139  #define mmDP0_DP_TEST_DEBUG_DATA                                                0x4ad9
6140  #define mmDP1_DP_TEST_DEBUG_DATA                                                0x4bd9
6141  #define mmDP2_DP_TEST_DEBUG_DATA                                                0x4cd9
6142  #define mmDP3_DP_TEST_DEBUG_DATA                                                0x4dd9
6143  #define mmDP4_DP_TEST_DEBUG_DATA                                                0x4ed9
6144  #define mmDP5_DP_TEST_DEBUG_DATA                                                0x4fd9
6145  #define mmDP6_DP_TEST_DEBUG_DATA                                                0x54d9
6146  #define mmDP7_DP_TEST_DEBUG_DATA                                                0x56d9
6147  #define mmDP8_DP_TEST_DEBUG_DATA                                                0x57d9
6148  #define mmDP_FE_TEST_DEBUG_INDEX                                                0x4ada
6149  #define mmDP0_DP_FE_TEST_DEBUG_INDEX                                            0x4ada
6150  #define mmDP1_DP_FE_TEST_DEBUG_INDEX                                            0x4bda
6151  #define mmDP2_DP_FE_TEST_DEBUG_INDEX                                            0x4cda
6152  #define mmDP3_DP_FE_TEST_DEBUG_INDEX                                            0x4dda
6153  #define mmDP4_DP_FE_TEST_DEBUG_INDEX                                            0x4eda
6154  #define mmDP5_DP_FE_TEST_DEBUG_INDEX                                            0x4fda
6155  #define mmDP6_DP_FE_TEST_DEBUG_INDEX                                            0x54da
6156  #define mmDP7_DP_FE_TEST_DEBUG_INDEX                                            0x56da
6157  #define mmDP8_DP_FE_TEST_DEBUG_INDEX                                            0x57da
6158  #define mmDP_FE_TEST_DEBUG_DATA                                                 0x4adb
6159  #define mmDP0_DP_FE_TEST_DEBUG_DATA                                             0x4adb
6160  #define mmDP1_DP_FE_TEST_DEBUG_DATA                                             0x4bdb
6161  #define mmDP2_DP_FE_TEST_DEBUG_DATA                                             0x4cdb
6162  #define mmDP3_DP_FE_TEST_DEBUG_DATA                                             0x4ddb
6163  #define mmDP4_DP_FE_TEST_DEBUG_DATA                                             0x4edb
6164  #define mmDP5_DP_FE_TEST_DEBUG_DATA                                             0x4fdb
6165  #define mmDP6_DP_FE_TEST_DEBUG_DATA                                             0x54db
6166  #define mmDP7_DP_FE_TEST_DEBUG_DATA                                             0x56db
6167  #define mmDP8_DP_FE_TEST_DEBUG_DATA                                             0x57db
6168  #define mmAUX_CONTROL                                                           0x5c00
6169  #define mmDP_AUX0_AUX_CONTROL                                                   0x5c00
6170  #define mmDP_AUX1_AUX_CONTROL                                                   0x5c1c
6171  #define mmDP_AUX2_AUX_CONTROL                                                   0x5c38
6172  #define mmDP_AUX3_AUX_CONTROL                                                   0x5c54
6173  #define mmDP_AUX4_AUX_CONTROL                                                   0x5c70
6174  #define mmDP_AUX5_AUX_CONTROL                                                   0x5c8c
6175  #define mmAUX_SW_CONTROL                                                        0x5c01
6176  #define mmDP_AUX0_AUX_SW_CONTROL                                                0x5c01
6177  #define mmDP_AUX1_AUX_SW_CONTROL                                                0x5c1d
6178  #define mmDP_AUX2_AUX_SW_CONTROL                                                0x5c39
6179  #define mmDP_AUX3_AUX_SW_CONTROL                                                0x5c55
6180  #define mmDP_AUX4_AUX_SW_CONTROL                                                0x5c71
6181  #define mmDP_AUX5_AUX_SW_CONTROL                                                0x5c8d
6182  #define mmAUX_ARB_CONTROL                                                       0x5c02
6183  #define mmDP_AUX0_AUX_ARB_CONTROL                                               0x5c02
6184  #define mmDP_AUX1_AUX_ARB_CONTROL                                               0x5c1e
6185  #define mmDP_AUX2_AUX_ARB_CONTROL                                               0x5c3a
6186  #define mmDP_AUX3_AUX_ARB_CONTROL                                               0x5c56
6187  #define mmDP_AUX4_AUX_ARB_CONTROL                                               0x5c72
6188  #define mmDP_AUX5_AUX_ARB_CONTROL                                               0x5c8e
6189  #define mmAUX_INTERRUPT_CONTROL                                                 0x5c03
6190  #define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                         0x5c03
6191  #define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                         0x5c1f
6192  #define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                         0x5c3b
6193  #define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                         0x5c57
6194  #define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                         0x5c73
6195  #define mmDP_AUX5_AUX_INTERRUPT_CONTROL                                         0x5c8f
6196  #define mmAUX_SW_STATUS                                                         0x5c04
6197  #define mmDP_AUX0_AUX_SW_STATUS                                                 0x5c04
6198  #define mmDP_AUX1_AUX_SW_STATUS                                                 0x5c20
6199  #define mmDP_AUX2_AUX_SW_STATUS                                                 0x5c3c
6200  #define mmDP_AUX3_AUX_SW_STATUS                                                 0x5c58
6201  #define mmDP_AUX4_AUX_SW_STATUS                                                 0x5c74
6202  #define mmDP_AUX5_AUX_SW_STATUS                                                 0x5c90
6203  #define mmAUX_LS_STATUS                                                         0x5c05
6204  #define mmDP_AUX0_AUX_LS_STATUS                                                 0x5c05
6205  #define mmDP_AUX1_AUX_LS_STATUS                                                 0x5c21
6206  #define mmDP_AUX2_AUX_LS_STATUS                                                 0x5c3d
6207  #define mmDP_AUX3_AUX_LS_STATUS                                                 0x5c59
6208  #define mmDP_AUX4_AUX_LS_STATUS                                                 0x5c75
6209  #define mmDP_AUX5_AUX_LS_STATUS                                                 0x5c91
6210  #define mmAUX_SW_DATA                                                           0x5c06
6211  #define mmDP_AUX0_AUX_SW_DATA                                                   0x5c06
6212  #define mmDP_AUX1_AUX_SW_DATA                                                   0x5c22
6213  #define mmDP_AUX2_AUX_SW_DATA                                                   0x5c3e
6214  #define mmDP_AUX3_AUX_SW_DATA                                                   0x5c5a
6215  #define mmDP_AUX4_AUX_SW_DATA                                                   0x5c76
6216  #define mmDP_AUX5_AUX_SW_DATA                                                   0x5c92
6217  #define mmAUX_LS_DATA                                                           0x5c07
6218  #define mmDP_AUX0_AUX_LS_DATA                                                   0x5c07
6219  #define mmDP_AUX1_AUX_LS_DATA                                                   0x5c23
6220  #define mmDP_AUX2_AUX_LS_DATA                                                   0x5c3f
6221  #define mmDP_AUX3_AUX_LS_DATA                                                   0x5c5b
6222  #define mmDP_AUX4_AUX_LS_DATA                                                   0x5c77
6223  #define mmDP_AUX5_AUX_LS_DATA                                                   0x5c93
6224  #define mmAUX_DPHY_TX_REF_CONTROL                                               0x5c08
6225  #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                       0x5c08
6226  #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                       0x5c24
6227  #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                       0x5c40
6228  #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                       0x5c5c
6229  #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                       0x5c78
6230  #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                       0x5c94
6231  #define mmAUX_DPHY_TX_CONTROL                                                   0x5c09
6232  #define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                           0x5c09
6233  #define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                           0x5c25
6234  #define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                           0x5c41
6235  #define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                           0x5c5d
6236  #define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                           0x5c79
6237  #define mmDP_AUX5_AUX_DPHY_TX_CONTROL                                           0x5c95
6238  #define mmAUX_DPHY_RX_CONTROL0                                                  0x5c0a
6239  #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                          0x5c0a
6240  #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                          0x5c26
6241  #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                          0x5c42
6242  #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                          0x5c5e
6243  #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                          0x5c7a
6244  #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                          0x5c96
6245  #define mmAUX_DPHY_RX_CONTROL1                                                  0x5c0b
6246  #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                          0x5c0b
6247  #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                          0x5c27
6248  #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                          0x5c43
6249  #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                          0x5c5f
6250  #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                          0x5c7b
6251  #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                          0x5c97
6252  #define mmAUX_DPHY_TX_STATUS                                                    0x5c0c
6253  #define mmDP_AUX0_AUX_DPHY_TX_STATUS                                            0x5c0c
6254  #define mmDP_AUX1_AUX_DPHY_TX_STATUS                                            0x5c28
6255  #define mmDP_AUX2_AUX_DPHY_TX_STATUS                                            0x5c44
6256  #define mmDP_AUX3_AUX_DPHY_TX_STATUS                                            0x5c60
6257  #define mmDP_AUX4_AUX_DPHY_TX_STATUS                                            0x5c7c
6258  #define mmDP_AUX5_AUX_DPHY_TX_STATUS                                            0x5c98
6259  #define mmAUX_DPHY_RX_STATUS                                                    0x5c0d
6260  #define mmDP_AUX0_AUX_DPHY_RX_STATUS                                            0x5c0d
6261  #define mmDP_AUX1_AUX_DPHY_RX_STATUS                                            0x5c29
6262  #define mmDP_AUX2_AUX_DPHY_RX_STATUS                                            0x5c45
6263  #define mmDP_AUX3_AUX_DPHY_RX_STATUS                                            0x5c61
6264  #define mmDP_AUX4_AUX_DPHY_RX_STATUS                                            0x5c7d
6265  #define mmDP_AUX5_AUX_DPHY_RX_STATUS                                            0x5c99
6266  #define mmAUX_GTC_SYNC_ERROR_CONTROL                                            0x5c0f
6267  #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c0f
6268  #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c2b
6269  #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c47
6270  #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c63
6271  #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c7f
6272  #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                    0x5c9b
6273  #define mmAUX_GTC_SYNC_CONTROLLER_STATUS                                        0x5c10
6274  #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c10
6275  #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c2c
6276  #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c48
6277  #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c64
6278  #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c80
6279  #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                0x5c9c
6280  #define mmAUX_GTC_SYNC_STATUS                                                   0x5c11
6281  #define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                           0x5c11
6282  #define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                           0x5c2d
6283  #define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                           0x5c49
6284  #define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                           0x5c65
6285  #define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                           0x5c81
6286  #define mmDP_AUX5_AUX_GTC_SYNC_STATUS                                           0x5c9d
6287  #define mmAUX_TEST_DEBUG_INDEX                                                  0x5c14
6288  #define mmDP_AUX0_AUX_TEST_DEBUG_INDEX                                          0x5c14
6289  #define mmDP_AUX1_AUX_TEST_DEBUG_INDEX                                          0x5c30
6290  #define mmDP_AUX2_AUX_TEST_DEBUG_INDEX                                          0x5c4c
6291  #define mmDP_AUX3_AUX_TEST_DEBUG_INDEX                                          0x5c68
6292  #define mmDP_AUX4_AUX_TEST_DEBUG_INDEX                                          0x5c84
6293  #define mmDP_AUX5_AUX_TEST_DEBUG_INDEX                                          0x5ca0
6294  #define mmAUX_TEST_DEBUG_DATA                                                   0x5c15
6295  #define mmDP_AUX0_AUX_TEST_DEBUG_DATA                                           0x5c15
6296  #define mmDP_AUX1_AUX_TEST_DEBUG_DATA                                           0x5c31
6297  #define mmDP_AUX2_AUX_TEST_DEBUG_DATA                                           0x5c4d
6298  #define mmDP_AUX3_AUX_TEST_DEBUG_DATA                                           0x5c69
6299  #define mmDP_AUX4_AUX_TEST_DEBUG_DATA                                           0x5c85
6300  #define mmDP_AUX5_AUX_TEST_DEBUG_DATA                                           0x5ca1
6301  #define ixDP_AUX_DEBUG_A                                                        0x10
6302  #define ixDP_AUX_DEBUG_B                                                        0x11
6303  #define ixDP_AUX_DEBUG_C                                                        0x12
6304  #define ixDP_AUX_DEBUG_D                                                        0x13
6305  #define ixDP_AUX_DEBUG_E                                                        0x14
6306  #define ixDP_AUX_DEBUG_F                                                        0x15
6307  #define ixDP_AUX_DEBUG_G                                                        0x16
6308  #define ixDP_AUX_DEBUG_H                                                        0x17
6309  #define ixDP_AUX_DEBUG_I                                                        0x18
6310  #define ixDP_AUX_DEBUG_J                                                        0x19
6311  #define ixDP_AUX_DEBUG_K                                                        0x1a
6312  #define ixDP_AUX_DEBUG_L                                                        0x1b
6313  #define ixDP_AUX_DEBUG_M                                                        0x1c
6314  #define ixDP_AUX_DEBUG_N                                                        0x1d
6315  #define ixDP_AUX_DEBUG_O                                                        0x1e
6316  #define ixDP_AUX_DEBUG_P                                                        0x1f
6317  #define ixDP_AUX_DEBUG_Q                                                        0x20
6318  #define mmDVO_ENABLE                                                            0x16a0
6319  #define mmDVO_SOURCE_SELECT                                                     0x16a1
6320  #define mmDVO_OUTPUT                                                            0x16a2
6321  #define mmDVO_CONTROL                                                           0x16a3
6322  #define mmDVO_CRC_EN                                                            0x16a4
6323  #define mmDVO_CRC2_SIG_MASK                                                     0x16a5
6324  #define mmDVO_CRC2_SIG_RESULT                                                   0x16a6
6325  #define mmDVO_FIFO_ERROR_STATUS                                                 0x16a7
6326  #define mmDVO_TEST_DEBUG_INDEX                                                  0x16a8
6327  #define mmDVO_TEST_DEBUG_DATA                                                   0x16a9
6328  #define mmFBC_CNTL                                                              0x280
6329  #define mmFBC_IDLE_FORCE_CLEAR_MASK                                             0x282
6330  #define mmFBC_START_STOP_DELAY                                                  0x283
6331  #define mmFBC_COMP_CNTL                                                         0x284
6332  #define mmFBC_COMP_MODE                                                         0x285
6333  #define mmFBC_DEBUG0                                                            0x286
6334  #define mmFBC_DEBUG1                                                            0x287
6335  #define mmFBC_DEBUG2                                                            0x288
6336  #define mmFBC_IND_LUT0                                                          0x289
6337  #define mmFBC_IND_LUT1                                                          0x28a
6338  #define mmFBC_IND_LUT2                                                          0x28b
6339  #define mmFBC_IND_LUT3                                                          0x28c
6340  #define mmFBC_IND_LUT4                                                          0x28d
6341  #define mmFBC_IND_LUT5                                                          0x28e
6342  #define mmFBC_IND_LUT6                                                          0x28f
6343  #define mmFBC_IND_LUT7                                                          0x290
6344  #define mmFBC_IND_LUT8                                                          0x291
6345  #define mmFBC_IND_LUT9                                                          0x292
6346  #define mmFBC_IND_LUT10                                                         0x293
6347  #define mmFBC_IND_LUT11                                                         0x294
6348  #define mmFBC_IND_LUT12                                                         0x295
6349  #define mmFBC_IND_LUT13                                                         0x296
6350  #define mmFBC_IND_LUT14                                                         0x297
6351  #define mmFBC_IND_LUT15                                                         0x298
6352  #define mmFBC_CSM_REGION_OFFSET_01                                              0x299
6353  #define mmFBC_CSM_REGION_OFFSET_23                                              0x29a
6354  #define mmFBC_CLIENT_REGION_MASK                                                0x29b
6355  #define mmFBC_DEBUG_COMP                                                        0x29c
6356  #define mmFBC_DEBUG_CSR                                                         0x29d
6357  #define mmFBC_DEBUG_CSR_RDATA                                                   0x29e
6358  #define mmFBC_DEBUG_CSR_WDATA                                                   0x29f
6359  #define mmFBC_DEBUG_CSR_RDATA_HI                                                0x2a0
6360  #define mmFBC_DEBUG_CSR_WDATA_HI                                                0x2a1
6361  #define mmFBC_MISC                                                              0x2a2
6362  #define mmFBC_STATUS                                                            0x2a3
6363  #define mmFBC_ALPHA_CNTL                                                        0x2a6
6364  #define mmFBC_ALPHA_RGB_OVERRIDE                                                0x2a7
6365  #define mmFBC_TEST_DEBUG_INDEX                                                  0x2a4
6366  #define mmFBC_TEST_DEBUG_DATA                                                   0x2a5
6367  #define mmFMT_CLAMP_COMPONENT_R                                                 0x1be8
6368  #define mmFMT0_FMT_CLAMP_COMPONENT_R                                            0x1be8
6369  #define mmFMT1_FMT_CLAMP_COMPONENT_R                                            0x1de8
6370  #define mmFMT2_FMT_CLAMP_COMPONENT_R                                            0x1fe8
6371  #define mmFMT3_FMT_CLAMP_COMPONENT_R                                            0x41e8
6372  #define mmFMT4_FMT_CLAMP_COMPONENT_R                                            0x43e8
6373  #define mmFMT5_FMT_CLAMP_COMPONENT_R                                            0x45e8
6374  #define mmFMT_CLAMP_COMPONENT_G                                                 0x1be9
6375  #define mmFMT0_FMT_CLAMP_COMPONENT_G                                            0x1be9
6376  #define mmFMT1_FMT_CLAMP_COMPONENT_G                                            0x1de9
6377  #define mmFMT2_FMT_CLAMP_COMPONENT_G                                            0x1fe9
6378  #define mmFMT3_FMT_CLAMP_COMPONENT_G                                            0x41e9
6379  #define mmFMT4_FMT_CLAMP_COMPONENT_G                                            0x43e9
6380  #define mmFMT5_FMT_CLAMP_COMPONENT_G                                            0x45e9
6381  #define mmFMT_CLAMP_COMPONENT_B                                                 0x1bea
6382  #define mmFMT0_FMT_CLAMP_COMPONENT_B                                            0x1bea
6383  #define mmFMT1_FMT_CLAMP_COMPONENT_B                                            0x1dea
6384  #define mmFMT2_FMT_CLAMP_COMPONENT_B                                            0x1fea
6385  #define mmFMT3_FMT_CLAMP_COMPONENT_B                                            0x41ea
6386  #define mmFMT4_FMT_CLAMP_COMPONENT_B                                            0x43ea
6387  #define mmFMT5_FMT_CLAMP_COMPONENT_B                                            0x45ea
6388  #define mmFMT_DYNAMIC_EXP_CNTL                                                  0x1bed
6389  #define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                             0x1bed
6390  #define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                             0x1ded
6391  #define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                             0x1fed
6392  #define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                             0x41ed
6393  #define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                             0x43ed
6394  #define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                             0x45ed
6395  #define mmFMT_CONTROL                                                           0x1bee
6396  #define mmFMT0_FMT_CONTROL                                                      0x1bee
6397  #define mmFMT1_FMT_CONTROL                                                      0x1dee
6398  #define mmFMT2_FMT_CONTROL                                                      0x1fee
6399  #define mmFMT3_FMT_CONTROL                                                      0x41ee
6400  #define mmFMT4_FMT_CONTROL                                                      0x43ee
6401  #define mmFMT5_FMT_CONTROL                                                      0x45ee
6402  #define mmFMT_BIT_DEPTH_CONTROL                                                 0x1bf2
6403  #define mmFMT0_FMT_BIT_DEPTH_CONTROL                                            0x1bf2
6404  #define mmFMT1_FMT_BIT_DEPTH_CONTROL                                            0x1df2
6405  #define mmFMT2_FMT_BIT_DEPTH_CONTROL                                            0x1ff2
6406  #define mmFMT3_FMT_BIT_DEPTH_CONTROL                                            0x41f2
6407  #define mmFMT4_FMT_BIT_DEPTH_CONTROL                                            0x43f2
6408  #define mmFMT5_FMT_BIT_DEPTH_CONTROL                                            0x45f2
6409  #define mmFMT_DITHER_RAND_R_SEED                                                0x1bf3
6410  #define mmFMT0_FMT_DITHER_RAND_R_SEED                                           0x1bf3
6411  #define mmFMT1_FMT_DITHER_RAND_R_SEED                                           0x1df3
6412  #define mmFMT2_FMT_DITHER_RAND_R_SEED                                           0x1ff3
6413  #define mmFMT3_FMT_DITHER_RAND_R_SEED                                           0x41f3
6414  #define mmFMT4_FMT_DITHER_RAND_R_SEED                                           0x43f3
6415  #define mmFMT5_FMT_DITHER_RAND_R_SEED                                           0x45f3
6416  #define mmFMT_DITHER_RAND_G_SEED                                                0x1bf4
6417  #define mmFMT0_FMT_DITHER_RAND_G_SEED                                           0x1bf4
6418  #define mmFMT1_FMT_DITHER_RAND_G_SEED                                           0x1df4
6419  #define mmFMT2_FMT_DITHER_RAND_G_SEED                                           0x1ff4
6420  #define mmFMT3_FMT_DITHER_RAND_G_SEED                                           0x41f4
6421  #define mmFMT4_FMT_DITHER_RAND_G_SEED                                           0x43f4
6422  #define mmFMT5_FMT_DITHER_RAND_G_SEED                                           0x45f4
6423  #define mmFMT_DITHER_RAND_B_SEED                                                0x1bf5
6424  #define mmFMT0_FMT_DITHER_RAND_B_SEED                                           0x1bf5
6425  #define mmFMT1_FMT_DITHER_RAND_B_SEED                                           0x1df5
6426  #define mmFMT2_FMT_DITHER_RAND_B_SEED                                           0x1ff5
6427  #define mmFMT3_FMT_DITHER_RAND_B_SEED                                           0x41f5
6428  #define mmFMT4_FMT_DITHER_RAND_B_SEED                                           0x43f5
6429  #define mmFMT5_FMT_DITHER_RAND_B_SEED                                           0x45f5
6430  #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL                                   0x1bf6
6431  #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1bf6
6432  #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1df6
6433  #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x1ff6
6434  #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x41f6
6435  #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x43f6
6436  #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL                              0x45f6
6437  #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                     0x1bf7
6438  #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1bf7
6439  #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1df7
6440  #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x1ff7
6441  #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x41f7
6442  #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x43f7
6443  #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX                0x45f7
6444  #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                     0x1bf8
6445  #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1bf8
6446  #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1df8
6447  #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x1ff8
6448  #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x41f8
6449  #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x43f8
6450  #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX                0x45f8
6451  #define mmFMT_CLAMP_CNTL                                                        0x1bf9
6452  #define mmFMT0_FMT_CLAMP_CNTL                                                   0x1bf9
6453  #define mmFMT1_FMT_CLAMP_CNTL                                                   0x1df9
6454  #define mmFMT2_FMT_CLAMP_CNTL                                                   0x1ff9
6455  #define mmFMT3_FMT_CLAMP_CNTL                                                   0x41f9
6456  #define mmFMT4_FMT_CLAMP_CNTL                                                   0x43f9
6457  #define mmFMT5_FMT_CLAMP_CNTL                                                   0x45f9
6458  #define mmFMT_CRC_CNTL                                                          0x1bfa
6459  #define mmFMT0_FMT_CRC_CNTL                                                     0x1bfa
6460  #define mmFMT1_FMT_CRC_CNTL                                                     0x1dfa
6461  #define mmFMT2_FMT_CRC_CNTL                                                     0x1ffa
6462  #define mmFMT3_FMT_CRC_CNTL                                                     0x41fa
6463  #define mmFMT4_FMT_CRC_CNTL                                                     0x43fa
6464  #define mmFMT5_FMT_CRC_CNTL                                                     0x45fa
6465  #define mmFMT_CRC_SIG_RED_GREEN_MASK                                            0x1bfb
6466  #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1bfb
6467  #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1dfb
6468  #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK                                       0x1ffb
6469  #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                                       0x41fb
6470  #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                                       0x43fb
6471  #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                                       0x45fb
6472  #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK                                         0x1bfc
6473  #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1bfc
6474  #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1dfc
6475  #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x1ffc
6476  #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x41fc
6477  #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x43fc
6478  #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                                    0x45fc
6479  #define mmFMT_CRC_SIG_RED_GREEN                                                 0x1bfd
6480  #define mmFMT0_FMT_CRC_SIG_RED_GREEN                                            0x1bfd
6481  #define mmFMT1_FMT_CRC_SIG_RED_GREEN                                            0x1dfd
6482  #define mmFMT2_FMT_CRC_SIG_RED_GREEN                                            0x1ffd
6483  #define mmFMT3_FMT_CRC_SIG_RED_GREEN                                            0x41fd
6484  #define mmFMT4_FMT_CRC_SIG_RED_GREEN                                            0x43fd
6485  #define mmFMT5_FMT_CRC_SIG_RED_GREEN                                            0x45fd
6486  #define mmFMT_CRC_SIG_BLUE_CONTROL                                              0x1bfe
6487  #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL                                         0x1bfe
6488  #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL                                         0x1dfe
6489  #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL                                         0x1ffe
6490  #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                                         0x41fe
6491  #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL                                         0x43fe
6492  #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                                         0x45fe
6493  #define mmFMT_DEBUG_CNTL                                                        0x1bff
6494  #define mmFMT0_FMT_DEBUG_CNTL                                                   0x1bff
6495  #define mmFMT1_FMT_DEBUG_CNTL                                                   0x1dff
6496  #define mmFMT2_FMT_DEBUG_CNTL                                                   0x1fff
6497  #define mmFMT3_FMT_DEBUG_CNTL                                                   0x41ff
6498  #define mmFMT4_FMT_DEBUG_CNTL                                                   0x43ff
6499  #define mmFMT5_FMT_DEBUG_CNTL                                                   0x45ff
6500  #define mmFMT_SIDE_BY_SIDE_STEREO_CONTROL                                       0x1bf0
6501  #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x1bf0
6502  #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x1df0
6503  #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x1ff0
6504  #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x41f0
6505  #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x43f0
6506  #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                  0x45f0
6507  #define mmFMT_420_HBLANK_EARLY_START                                            0x1bf1
6508  #define mmFMT0_FMT_420_HBLANK_EARLY_START                                       0x1bf1
6509  #define mmFMT1_FMT_420_HBLANK_EARLY_START                                       0x1df1
6510  #define mmFMT2_FMT_420_HBLANK_EARLY_START                                       0x1ff1
6511  #define mmFMT3_FMT_420_HBLANK_EARLY_START                                       0x41f1
6512  #define mmFMT4_FMT_420_HBLANK_EARLY_START                                       0x43f1
6513  #define mmFMT5_FMT_420_HBLANK_EARLY_START                                       0x45f1
6514  #define mmFMT_TEST_DEBUG_INDEX                                                  0x1beb
6515  #define mmFMT0_FMT_TEST_DEBUG_INDEX                                             0x1beb
6516  #define mmFMT1_FMT_TEST_DEBUG_INDEX                                             0x1deb
6517  #define mmFMT2_FMT_TEST_DEBUG_INDEX                                             0x1feb
6518  #define mmFMT3_FMT_TEST_DEBUG_INDEX                                             0x41eb
6519  #define mmFMT4_FMT_TEST_DEBUG_INDEX                                             0x43eb
6520  #define mmFMT5_FMT_TEST_DEBUG_INDEX                                             0x45eb
6521  #define mmFMT_TEST_DEBUG_DATA                                                   0x1bec
6522  #define mmFMT0_FMT_TEST_DEBUG_DATA                                              0x1bec
6523  #define mmFMT1_FMT_TEST_DEBUG_DATA                                              0x1dec
6524  #define mmFMT2_FMT_TEST_DEBUG_DATA                                              0x1fec
6525  #define mmFMT3_FMT_TEST_DEBUG_DATA                                              0x41ec
6526  #define mmFMT4_FMT_TEST_DEBUG_DATA                                              0x43ec
6527  #define mmFMT5_FMT_TEST_DEBUG_DATA                                              0x45ec
6528  #define ixFMT_DEBUG0                                                            0x1
6529  #define ixFMT_DEBUG1                                                            0x2
6530  #define ixFMT_DEBUG2                                                            0x3
6531  #define ixFMT_DEBUG3                                                            0x4
6532  #define ixFMT_DEBUG_ID                                                          0x0
6533  #define mmLB_DATA_FORMAT                                                        0x1ac0
6534  #define mmLB0_LB_DATA_FORMAT                                                    0x1ac0
6535  #define mmLB1_LB_DATA_FORMAT                                                    0x1cc0
6536  #define mmLB2_LB_DATA_FORMAT                                                    0x1ec0
6537  #define mmLB3_LB_DATA_FORMAT                                                    0x40c0
6538  #define mmLB4_LB_DATA_FORMAT                                                    0x42c0
6539  #define mmLB5_LB_DATA_FORMAT                                                    0x44c0
6540  #define mmLB_MEMORY_CTRL                                                        0x1ac1
6541  #define mmLB0_LB_MEMORY_CTRL                                                    0x1ac1
6542  #define mmLB1_LB_MEMORY_CTRL                                                    0x1cc1
6543  #define mmLB2_LB_MEMORY_CTRL                                                    0x1ec1
6544  #define mmLB3_LB_MEMORY_CTRL                                                    0x40c1
6545  #define mmLB4_LB_MEMORY_CTRL                                                    0x42c1
6546  #define mmLB5_LB_MEMORY_CTRL                                                    0x44c1
6547  #define mmLB_MEMORY_SIZE_STATUS                                                 0x1ac2
6548  #define mmLB0_LB_MEMORY_SIZE_STATUS                                             0x1ac2
6549  #define mmLB1_LB_MEMORY_SIZE_STATUS                                             0x1cc2
6550  #define mmLB2_LB_MEMORY_SIZE_STATUS                                             0x1ec2
6551  #define mmLB3_LB_MEMORY_SIZE_STATUS                                             0x40c2
6552  #define mmLB4_LB_MEMORY_SIZE_STATUS                                             0x42c2
6553  #define mmLB5_LB_MEMORY_SIZE_STATUS                                             0x44c2
6554  #define mmLB_DESKTOP_HEIGHT                                                     0x1ac3
6555  #define mmLB0_LB_DESKTOP_HEIGHT                                                 0x1ac3
6556  #define mmLB1_LB_DESKTOP_HEIGHT                                                 0x1cc3
6557  #define mmLB2_LB_DESKTOP_HEIGHT                                                 0x1ec3
6558  #define mmLB3_LB_DESKTOP_HEIGHT                                                 0x40c3
6559  #define mmLB4_LB_DESKTOP_HEIGHT                                                 0x42c3
6560  #define mmLB5_LB_DESKTOP_HEIGHT                                                 0x44c3
6561  #define mmLB_VLINE_START_END                                                    0x1ac4
6562  #define mmLB0_LB_VLINE_START_END                                                0x1ac4
6563  #define mmLB1_LB_VLINE_START_END                                                0x1cc4
6564  #define mmLB2_LB_VLINE_START_END                                                0x1ec4
6565  #define mmLB3_LB_VLINE_START_END                                                0x40c4
6566  #define mmLB4_LB_VLINE_START_END                                                0x42c4
6567  #define mmLB5_LB_VLINE_START_END                                                0x44c4
6568  #define mmLB_VLINE2_START_END                                                   0x1ac5
6569  #define mmLB0_LB_VLINE2_START_END                                               0x1ac5
6570  #define mmLB1_LB_VLINE2_START_END                                               0x1cc5
6571  #define mmLB2_LB_VLINE2_START_END                                               0x1ec5
6572  #define mmLB3_LB_VLINE2_START_END                                               0x40c5
6573  #define mmLB4_LB_VLINE2_START_END                                               0x42c5
6574  #define mmLB5_LB_VLINE2_START_END                                               0x44c5
6575  #define mmLB_V_COUNTER                                                          0x1ac6
6576  #define mmLB0_LB_V_COUNTER                                                      0x1ac6
6577  #define mmLB1_LB_V_COUNTER                                                      0x1cc6
6578  #define mmLB2_LB_V_COUNTER                                                      0x1ec6
6579  #define mmLB3_LB_V_COUNTER                                                      0x40c6
6580  #define mmLB4_LB_V_COUNTER                                                      0x42c6
6581  #define mmLB5_LB_V_COUNTER                                                      0x44c6
6582  #define mmLB_SNAPSHOT_V_COUNTER                                                 0x1ac7
6583  #define mmLB0_LB_SNAPSHOT_V_COUNTER                                             0x1ac7
6584  #define mmLB1_LB_SNAPSHOT_V_COUNTER                                             0x1cc7
6585  #define mmLB2_LB_SNAPSHOT_V_COUNTER                                             0x1ec7
6586  #define mmLB3_LB_SNAPSHOT_V_COUNTER                                             0x40c7
6587  #define mmLB4_LB_SNAPSHOT_V_COUNTER                                             0x42c7
6588  #define mmLB5_LB_SNAPSHOT_V_COUNTER                                             0x44c7
6589  #define mmLB_INTERRUPT_MASK                                                     0x1ac8
6590  #define mmLB0_LB_INTERRUPT_MASK                                                 0x1ac8
6591  #define mmLB1_LB_INTERRUPT_MASK                                                 0x1cc8
6592  #define mmLB2_LB_INTERRUPT_MASK                                                 0x1ec8
6593  #define mmLB3_LB_INTERRUPT_MASK                                                 0x40c8
6594  #define mmLB4_LB_INTERRUPT_MASK                                                 0x42c8
6595  #define mmLB5_LB_INTERRUPT_MASK                                                 0x44c8
6596  #define mmLB_VLINE_STATUS                                                       0x1ac9
6597  #define mmLB0_LB_VLINE_STATUS                                                   0x1ac9
6598  #define mmLB1_LB_VLINE_STATUS                                                   0x1cc9
6599  #define mmLB2_LB_VLINE_STATUS                                                   0x1ec9
6600  #define mmLB3_LB_VLINE_STATUS                                                   0x40c9
6601  #define mmLB4_LB_VLINE_STATUS                                                   0x42c9
6602  #define mmLB5_LB_VLINE_STATUS                                                   0x44c9
6603  #define mmLB_VLINE2_STATUS                                                      0x1aca
6604  #define mmLB0_LB_VLINE2_STATUS                                                  0x1aca
6605  #define mmLB1_LB_VLINE2_STATUS                                                  0x1cca
6606  #define mmLB2_LB_VLINE2_STATUS                                                  0x1eca
6607  #define mmLB3_LB_VLINE2_STATUS                                                  0x40ca
6608  #define mmLB4_LB_VLINE2_STATUS                                                  0x42ca
6609  #define mmLB5_LB_VLINE2_STATUS                                                  0x44ca
6610  #define mmLB_VBLANK_STATUS                                                      0x1acb
6611  #define mmLB0_LB_VBLANK_STATUS                                                  0x1acb
6612  #define mmLB1_LB_VBLANK_STATUS                                                  0x1ccb
6613  #define mmLB2_LB_VBLANK_STATUS                                                  0x1ecb
6614  #define mmLB3_LB_VBLANK_STATUS                                                  0x40cb
6615  #define mmLB4_LB_VBLANK_STATUS                                                  0x42cb
6616  #define mmLB5_LB_VBLANK_STATUS                                                  0x44cb
6617  #define mmLB_SYNC_RESET_SEL                                                     0x1acc
6618  #define mmLB0_LB_SYNC_RESET_SEL                                                 0x1acc
6619  #define mmLB1_LB_SYNC_RESET_SEL                                                 0x1ccc
6620  #define mmLB2_LB_SYNC_RESET_SEL                                                 0x1ecc
6621  #define mmLB3_LB_SYNC_RESET_SEL                                                 0x40cc
6622  #define mmLB4_LB_SYNC_RESET_SEL                                                 0x42cc
6623  #define mmLB5_LB_SYNC_RESET_SEL                                                 0x44cc
6624  #define mmLB_BLACK_KEYER_R_CR                                                   0x1acd
6625  #define mmLB0_LB_BLACK_KEYER_R_CR                                               0x1acd
6626  #define mmLB1_LB_BLACK_KEYER_R_CR                                               0x1ccd
6627  #define mmLB2_LB_BLACK_KEYER_R_CR                                               0x1ecd
6628  #define mmLB3_LB_BLACK_KEYER_R_CR                                               0x40cd
6629  #define mmLB4_LB_BLACK_KEYER_R_CR                                               0x42cd
6630  #define mmLB5_LB_BLACK_KEYER_R_CR                                               0x44cd
6631  #define mmLB_BLACK_KEYER_G_Y                                                    0x1ace
6632  #define mmLB0_LB_BLACK_KEYER_G_Y                                                0x1ace
6633  #define mmLB1_LB_BLACK_KEYER_G_Y                                                0x1cce
6634  #define mmLB2_LB_BLACK_KEYER_G_Y                                                0x1ece
6635  #define mmLB3_LB_BLACK_KEYER_G_Y                                                0x40ce
6636  #define mmLB4_LB_BLACK_KEYER_G_Y                                                0x42ce
6637  #define mmLB5_LB_BLACK_KEYER_G_Y                                                0x44ce
6638  #define mmLB_BLACK_KEYER_B_CB                                                   0x1acf
6639  #define mmLB0_LB_BLACK_KEYER_B_CB                                               0x1acf
6640  #define mmLB1_LB_BLACK_KEYER_B_CB                                               0x1ccf
6641  #define mmLB2_LB_BLACK_KEYER_B_CB                                               0x1ecf
6642  #define mmLB3_LB_BLACK_KEYER_B_CB                                               0x40cf
6643  #define mmLB4_LB_BLACK_KEYER_B_CB                                               0x42cf
6644  #define mmLB5_LB_BLACK_KEYER_B_CB                                               0x44cf
6645  #define mmLB_KEYER_COLOR_CTRL                                                   0x1ad0
6646  #define mmLB0_LB_KEYER_COLOR_CTRL                                               0x1ad0
6647  #define mmLB1_LB_KEYER_COLOR_CTRL                                               0x1cd0
6648  #define mmLB2_LB_KEYER_COLOR_CTRL                                               0x1ed0
6649  #define mmLB3_LB_KEYER_COLOR_CTRL                                               0x40d0
6650  #define mmLB4_LB_KEYER_COLOR_CTRL                                               0x42d0
6651  #define mmLB5_LB_KEYER_COLOR_CTRL                                               0x44d0
6652  #define mmLB_KEYER_COLOR_R_CR                                                   0x1ad1
6653  #define mmLB0_LB_KEYER_COLOR_R_CR                                               0x1ad1
6654  #define mmLB1_LB_KEYER_COLOR_R_CR                                               0x1cd1
6655  #define mmLB2_LB_KEYER_COLOR_R_CR                                               0x1ed1
6656  #define mmLB3_LB_KEYER_COLOR_R_CR                                               0x40d1
6657  #define mmLB4_LB_KEYER_COLOR_R_CR                                               0x42d1
6658  #define mmLB5_LB_KEYER_COLOR_R_CR                                               0x44d1
6659  #define mmLB_KEYER_COLOR_G_Y                                                    0x1ad2
6660  #define mmLB0_LB_KEYER_COLOR_G_Y                                                0x1ad2
6661  #define mmLB1_LB_KEYER_COLOR_G_Y                                                0x1cd2
6662  #define mmLB2_LB_KEYER_COLOR_G_Y                                                0x1ed2
6663  #define mmLB3_LB_KEYER_COLOR_G_Y                                                0x40d2
6664  #define mmLB4_LB_KEYER_COLOR_G_Y                                                0x42d2
6665  #define mmLB5_LB_KEYER_COLOR_G_Y                                                0x44d2
6666  #define mmLB_KEYER_COLOR_B_CB                                                   0x1ad3
6667  #define mmLB0_LB_KEYER_COLOR_B_CB                                               0x1ad3
6668  #define mmLB1_LB_KEYER_COLOR_B_CB                                               0x1cd3
6669  #define mmLB2_LB_KEYER_COLOR_B_CB                                               0x1ed3
6670  #define mmLB3_LB_KEYER_COLOR_B_CB                                               0x40d3
6671  #define mmLB4_LB_KEYER_COLOR_B_CB                                               0x42d3
6672  #define mmLB5_LB_KEYER_COLOR_B_CB                                               0x44d3
6673  #define mmLB_KEYER_COLOR_REP_R_CR                                               0x1ad4
6674  #define mmLB0_LB_KEYER_COLOR_REP_R_CR                                           0x1ad4
6675  #define mmLB1_LB_KEYER_COLOR_REP_R_CR                                           0x1cd4
6676  #define mmLB2_LB_KEYER_COLOR_REP_R_CR                                           0x1ed4
6677  #define mmLB3_LB_KEYER_COLOR_REP_R_CR                                           0x40d4
6678  #define mmLB4_LB_KEYER_COLOR_REP_R_CR                                           0x42d4
6679  #define mmLB5_LB_KEYER_COLOR_REP_R_CR                                           0x44d4
6680  #define mmLB_KEYER_COLOR_REP_G_Y                                                0x1ad5
6681  #define mmLB0_LB_KEYER_COLOR_REP_G_Y                                            0x1ad5
6682  #define mmLB1_LB_KEYER_COLOR_REP_G_Y                                            0x1cd5
6683  #define mmLB2_LB_KEYER_COLOR_REP_G_Y                                            0x1ed5
6684  #define mmLB3_LB_KEYER_COLOR_REP_G_Y                                            0x40d5
6685  #define mmLB4_LB_KEYER_COLOR_REP_G_Y                                            0x42d5
6686  #define mmLB5_LB_KEYER_COLOR_REP_G_Y                                            0x44d5
6687  #define mmLB_KEYER_COLOR_REP_B_CB                                               0x1ad6
6688  #define mmLB0_LB_KEYER_COLOR_REP_B_CB                                           0x1ad6
6689  #define mmLB1_LB_KEYER_COLOR_REP_B_CB                                           0x1cd6
6690  #define mmLB2_LB_KEYER_COLOR_REP_B_CB                                           0x1ed6
6691  #define mmLB3_LB_KEYER_COLOR_REP_B_CB                                           0x40d6
6692  #define mmLB4_LB_KEYER_COLOR_REP_B_CB                                           0x42d6
6693  #define mmLB5_LB_KEYER_COLOR_REP_B_CB                                           0x44d6
6694  #define mmLB_BUFFER_LEVEL_STATUS                                                0x1ad7
6695  #define mmLB0_LB_BUFFER_LEVEL_STATUS                                            0x1ad7
6696  #define mmLB1_LB_BUFFER_LEVEL_STATUS                                            0x1cd7
6697  #define mmLB2_LB_BUFFER_LEVEL_STATUS                                            0x1ed7
6698  #define mmLB3_LB_BUFFER_LEVEL_STATUS                                            0x40d7
6699  #define mmLB4_LB_BUFFER_LEVEL_STATUS                                            0x42d7
6700  #define mmLB5_LB_BUFFER_LEVEL_STATUS                                            0x44d7
6701  #define mmLB_BUFFER_URGENCY_CTRL                                                0x1ad8
6702  #define mmLB0_LB_BUFFER_URGENCY_CTRL                                            0x1ad8
6703  #define mmLB1_LB_BUFFER_URGENCY_CTRL                                            0x1cd8
6704  #define mmLB2_LB_BUFFER_URGENCY_CTRL                                            0x1ed8
6705  #define mmLB3_LB_BUFFER_URGENCY_CTRL                                            0x40d8
6706  #define mmLB4_LB_BUFFER_URGENCY_CTRL                                            0x42d8
6707  #define mmLB5_LB_BUFFER_URGENCY_CTRL                                            0x44d8
6708  #define mmLB_BUFFER_URGENCY_STATUS                                              0x1ad9
6709  #define mmLB0_LB_BUFFER_URGENCY_STATUS                                          0x1ad9
6710  #define mmLB1_LB_BUFFER_URGENCY_STATUS                                          0x1cd9
6711  #define mmLB2_LB_BUFFER_URGENCY_STATUS                                          0x1ed9
6712  #define mmLB3_LB_BUFFER_URGENCY_STATUS                                          0x40d9
6713  #define mmLB4_LB_BUFFER_URGENCY_STATUS                                          0x42d9
6714  #define mmLB5_LB_BUFFER_URGENCY_STATUS                                          0x44d9
6715  #define mmLB_BUFFER_STATUS                                                      0x1ada
6716  #define mmLB0_LB_BUFFER_STATUS                                                  0x1ada
6717  #define mmLB1_LB_BUFFER_STATUS                                                  0x1cda
6718  #define mmLB2_LB_BUFFER_STATUS                                                  0x1eda
6719  #define mmLB3_LB_BUFFER_STATUS                                                  0x40da
6720  #define mmLB4_LB_BUFFER_STATUS                                                  0x42da
6721  #define mmLB5_LB_BUFFER_STATUS                                                  0x44da
6722  #define mmLB_NO_OUTSTANDING_REQ_STATUS                                          0x1adc
6723  #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1adc
6724  #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1cdc
6725  #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS                                      0x1edc
6726  #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                                      0x40dc
6727  #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                                      0x42dc
6728  #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                                      0x44dc
6729  #define mmMVP_AFR_FLIP_MODE                                                     0x1ae0
6730  #define mmLB0_MVP_AFR_FLIP_MODE                                                 0x1ae0
6731  #define mmLB1_MVP_AFR_FLIP_MODE                                                 0x1ce0
6732  #define mmLB2_MVP_AFR_FLIP_MODE                                                 0x1ee0
6733  #define mmLB3_MVP_AFR_FLIP_MODE                                                 0x40e0
6734  #define mmLB4_MVP_AFR_FLIP_MODE                                                 0x42e0
6735  #define mmLB5_MVP_AFR_FLIP_MODE                                                 0x44e0
6736  #define mmMVP_AFR_FLIP_FIFO_CNTL                                                0x1ae1
6737  #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ae1
6738  #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ce1
6739  #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL                                            0x1ee1
6740  #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL                                            0x40e1
6741  #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL                                            0x42e1
6742  #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL                                            0x44e1
6743  #define mmMVP_FLIP_LINE_NUM_INSERT                                              0x1ae2
6744  #define mmLB0_MVP_FLIP_LINE_NUM_INSERT                                          0x1ae2
6745  #define mmLB1_MVP_FLIP_LINE_NUM_INSERT                                          0x1ce2
6746  #define mmLB2_MVP_FLIP_LINE_NUM_INSERT                                          0x1ee2
6747  #define mmLB3_MVP_FLIP_LINE_NUM_INSERT                                          0x40e2
6748  #define mmLB4_MVP_FLIP_LINE_NUM_INSERT                                          0x42e2
6749  #define mmLB5_MVP_FLIP_LINE_NUM_INSERT                                          0x44e2
6750  #define mmDC_MVP_LB_CONTROL                                                     0x1ae3
6751  #define mmLB0_DC_MVP_LB_CONTROL                                                 0x1ae3
6752  #define mmLB1_DC_MVP_LB_CONTROL                                                 0x1ce3
6753  #define mmLB2_DC_MVP_LB_CONTROL                                                 0x1ee3
6754  #define mmLB3_DC_MVP_LB_CONTROL                                                 0x40e3
6755  #define mmLB4_DC_MVP_LB_CONTROL                                                 0x42e3
6756  #define mmLB5_DC_MVP_LB_CONTROL                                                 0x44e3
6757  #define mmLB_DEBUG                                                              0x1ae4
6758  #define mmLB0_LB_DEBUG                                                          0x1ae4
6759  #define mmLB1_LB_DEBUG                                                          0x1ce4
6760  #define mmLB2_LB_DEBUG                                                          0x1ee4
6761  #define mmLB3_LB_DEBUG                                                          0x40e4
6762  #define mmLB4_LB_DEBUG                                                          0x42e4
6763  #define mmLB5_LB_DEBUG                                                          0x44e4
6764  #define mmLB_DEBUG2                                                             0x1ae5
6765  #define mmLB0_LB_DEBUG2                                                         0x1ae5
6766  #define mmLB1_LB_DEBUG2                                                         0x1ce5
6767  #define mmLB2_LB_DEBUG2                                                         0x1ee5
6768  #define mmLB3_LB_DEBUG2                                                         0x40e5
6769  #define mmLB4_LB_DEBUG2                                                         0x42e5
6770  #define mmLB5_LB_DEBUG2                                                         0x44e5
6771  #define mmLB_DEBUG3                                                             0x1ae6
6772  #define mmLB0_LB_DEBUG3                                                         0x1ae6
6773  #define mmLB1_LB_DEBUG3                                                         0x1ce6
6774  #define mmLB2_LB_DEBUG3                                                         0x1ee6
6775  #define mmLB3_LB_DEBUG3                                                         0x40e6
6776  #define mmLB4_LB_DEBUG3                                                         0x42e6
6777  #define mmLB5_LB_DEBUG3                                                         0x44e6
6778  #define mmLB_TEST_DEBUG_INDEX                                                   0x1afe
6779  #define mmLB0_LB_TEST_DEBUG_INDEX                                               0x1afe
6780  #define mmLB1_LB_TEST_DEBUG_INDEX                                               0x1cfe
6781  #define mmLB2_LB_TEST_DEBUG_INDEX                                               0x1efe
6782  #define mmLB3_LB_TEST_DEBUG_INDEX                                               0x40fe
6783  #define mmLB4_LB_TEST_DEBUG_INDEX                                               0x42fe
6784  #define mmLB5_LB_TEST_DEBUG_INDEX                                               0x44fe
6785  #define mmLB_TEST_DEBUG_DATA                                                    0x1aff
6786  #define mmLB0_LB_TEST_DEBUG_DATA                                                0x1aff
6787  #define mmLB1_LB_TEST_DEBUG_DATA                                                0x1cff
6788  #define mmLB2_LB_TEST_DEBUG_DATA                                                0x1eff
6789  #define mmLB3_LB_TEST_DEBUG_DATA                                                0x40ff
6790  #define mmLB4_LB_TEST_DEBUG_DATA                                                0x42ff
6791  #define mmLB5_LB_TEST_DEBUG_DATA                                                0x44ff
6792  #define mmLBV_DATA_FORMAT                                                       0x463c
6793  #define mmLBV0_LBV_DATA_FORMAT                                                  0x463c
6794  #define mmLBV1_LBV_DATA_FORMAT                                                  0x983c
6795  #define mmLBV_MEMORY_CTRL                                                       0x463d
6796  #define mmLBV0_LBV_MEMORY_CTRL                                                  0x463d
6797  #define mmLBV1_LBV_MEMORY_CTRL                                                  0x983d
6798  #define mmLBV_MEMORY_SIZE_STATUS                                                0x463e
6799  #define mmLBV0_LBV_MEMORY_SIZE_STATUS                                           0x463e
6800  #define mmLBV1_LBV_MEMORY_SIZE_STATUS                                           0x983e
6801  #define mmLBV_DESKTOP_HEIGHT                                                    0x463f
6802  #define mmLBV0_LBV_DESKTOP_HEIGHT                                               0x463f
6803  #define mmLBV1_LBV_DESKTOP_HEIGHT                                               0x983f
6804  #define mmLBV_VLINE_START_END                                                   0x4640
6805  #define mmLBV0_LBV_VLINE_START_END                                              0x4640
6806  #define mmLBV1_LBV_VLINE_START_END                                              0x9840
6807  #define mmLBV_VLINE2_START_END                                                  0x4641
6808  #define mmLBV0_LBV_VLINE2_START_END                                             0x4641
6809  #define mmLBV1_LBV_VLINE2_START_END                                             0x9841
6810  #define mmLBV_V_COUNTER                                                         0x4642
6811  #define mmLBV0_LBV_V_COUNTER                                                    0x4642
6812  #define mmLBV1_LBV_V_COUNTER                                                    0x9842
6813  #define mmLBV_SNAPSHOT_V_COUNTER                                                0x4643
6814  #define mmLBV0_LBV_SNAPSHOT_V_COUNTER                                           0x4643
6815  #define mmLBV1_LBV_SNAPSHOT_V_COUNTER                                           0x9843
6816  #define mmLBV_V_COUNTER_CHROMA                                                  0x4644
6817  #define mmLBV0_LBV_V_COUNTER_CHROMA                                             0x4644
6818  #define mmLBV1_LBV_V_COUNTER_CHROMA                                             0x9844
6819  #define mmLBV_SNAPSHOT_V_COUNTER_CHROMA                                         0x4645
6820  #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA                                    0x4645
6821  #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA                                    0x9845
6822  #define mmLBV_INTERRUPT_MASK                                                    0x4646
6823  #define mmLBV0_LBV_INTERRUPT_MASK                                               0x4646
6824  #define mmLBV1_LBV_INTERRUPT_MASK                                               0x9846
6825  #define mmLBV_VLINE_STATUS                                                      0x4647
6826  #define mmLBV0_LBV_VLINE_STATUS                                                 0x4647
6827  #define mmLBV1_LBV_VLINE_STATUS                                                 0x9847
6828  #define mmLBV_VLINE2_STATUS                                                     0x4648
6829  #define mmLBV0_LBV_VLINE2_STATUS                                                0x4648
6830  #define mmLBV1_LBV_VLINE2_STATUS                                                0x9848
6831  #define mmLBV_VBLANK_STATUS                                                     0x4649
6832  #define mmLBV0_LBV_VBLANK_STATUS                                                0x4649
6833  #define mmLBV1_LBV_VBLANK_STATUS                                                0x9849
6834  #define mmLBV_SYNC_RESET_SEL                                                    0x464a
6835  #define mmLBV0_LBV_SYNC_RESET_SEL                                               0x464a
6836  #define mmLBV1_LBV_SYNC_RESET_SEL                                               0x984a
6837  #define mmLBV_BLACK_KEYER_R_CR                                                  0x464b
6838  #define mmLBV0_LBV_BLACK_KEYER_R_CR                                             0x464b
6839  #define mmLBV1_LBV_BLACK_KEYER_R_CR                                             0x984b
6840  #define mmLBV_BLACK_KEYER_G_Y                                                   0x464c
6841  #define mmLBV0_LBV_BLACK_KEYER_G_Y                                              0x464c
6842  #define mmLBV1_LBV_BLACK_KEYER_G_Y                                              0x984c
6843  #define mmLBV_BLACK_KEYER_B_CB                                                  0x464d
6844  #define mmLBV0_LBV_BLACK_KEYER_B_CB                                             0x464d
6845  #define mmLBV1_LBV_BLACK_KEYER_B_CB                                             0x984d
6846  #define mmLBV_KEYER_COLOR_CTRL                                                  0x464e
6847  #define mmLBV0_LBV_KEYER_COLOR_CTRL                                             0x464e
6848  #define mmLBV1_LBV_KEYER_COLOR_CTRL                                             0x984e
6849  #define mmLBV_KEYER_COLOR_R_CR                                                  0x464f
6850  #define mmLBV0_LBV_KEYER_COLOR_R_CR                                             0x464f
6851  #define mmLBV1_LBV_KEYER_COLOR_R_CR                                             0x984f
6852  #define mmLBV_KEYER_COLOR_G_Y                                                   0x4650
6853  #define mmLBV0_LBV_KEYER_COLOR_G_Y                                              0x4650
6854  #define mmLBV1_LBV_KEYER_COLOR_G_Y                                              0x9850
6855  #define mmLBV_KEYER_COLOR_B_CB                                                  0x4651
6856  #define mmLBV0_LBV_KEYER_COLOR_B_CB                                             0x4651
6857  #define mmLBV1_LBV_KEYER_COLOR_B_CB                                             0x9851
6858  #define mmLBV_KEYER_COLOR_REP_R_CR                                              0x4652
6859  #define mmLBV0_LBV_KEYER_COLOR_REP_R_CR                                         0x4652
6860  #define mmLBV1_LBV_KEYER_COLOR_REP_R_CR                                         0x9852
6861  #define mmLBV_KEYER_COLOR_REP_G_Y                                               0x4653
6862  #define mmLBV0_LBV_KEYER_COLOR_REP_G_Y                                          0x4653
6863  #define mmLBV1_LBV_KEYER_COLOR_REP_G_Y                                          0x9853
6864  #define mmLBV_KEYER_COLOR_REP_B_CB                                              0x4654
6865  #define mmLBV0_LBV_KEYER_COLOR_REP_B_CB                                         0x4654
6866  #define mmLBV1_LBV_KEYER_COLOR_REP_B_CB                                         0x9854
6867  #define mmLBV_BUFFER_LEVEL_STATUS                                               0x4655
6868  #define mmLBV0_LBV_BUFFER_LEVEL_STATUS                                          0x4655
6869  #define mmLBV1_LBV_BUFFER_LEVEL_STATUS                                          0x9855
6870  #define mmLBV_BUFFER_URGENCY_CTRL                                               0x4656
6871  #define mmLBV0_LBV_BUFFER_URGENCY_CTRL                                          0x4656
6872  #define mmLBV1_LBV_BUFFER_URGENCY_CTRL                                          0x9856
6873  #define mmLBV_BUFFER_URGENCY_STATUS                                             0x4657
6874  #define mmLBV0_LBV_BUFFER_URGENCY_STATUS                                        0x4657
6875  #define mmLBV1_LBV_BUFFER_URGENCY_STATUS                                        0x9857
6876  #define mmLBV_BUFFER_STATUS                                                     0x4658
6877  #define mmLBV0_LBV_BUFFER_STATUS                                                0x4658
6878  #define mmLBV1_LBV_BUFFER_STATUS                                                0x9858
6879  #define mmLBV_NO_OUTSTANDING_REQ_STATUS                                         0x4659
6880  #define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS                                    0x4659
6881  #define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS                                    0x9859
6882  #define mmLBV_DEBUG                                                             0x465a
6883  #define mmLBV0_LBV_DEBUG                                                        0x465a
6884  #define mmLBV1_LBV_DEBUG                                                        0x985a
6885  #define mmLBV_DEBUG2                                                            0x465b
6886  #define mmLBV0_LBV_DEBUG2                                                       0x465b
6887  #define mmLBV1_LBV_DEBUG2                                                       0x985b
6888  #define mmLBV_DEBUG3                                                            0x465c
6889  #define mmLBV0_LBV_DEBUG3                                                       0x465c
6890  #define mmLBV1_LBV_DEBUG3                                                       0x985c
6891  #define mmLBV_TEST_DEBUG_INDEX                                                  0x4666
6892  #define mmLBV0_LBV_TEST_DEBUG_INDEX                                             0x4666
6893  #define mmLBV1_LBV_TEST_DEBUG_INDEX                                             0x9866
6894  #define mmLBV_TEST_DEBUG_DATA                                                   0x4667
6895  #define mmLBV0_LBV_TEST_DEBUG_DATA                                              0x4667
6896  #define mmLBV1_LBV_TEST_DEBUG_DATA                                              0x9867
6897  #define mmMVP_CONTROL1                                                          0x2ac
6898  #define mmMVP_CONTROL2                                                          0x2ad
6899  #define mmMVP_FIFO_CONTROL                                                      0x2ae
6900  #define mmMVP_FIFO_STATUS                                                       0x2af
6901  #define mmMVP_SLAVE_STATUS                                                      0x2b0
6902  #define mmMVP_INBAND_CNTL_CAP                                                   0x2b1
6903  #define mmMVP_BLACK_KEYER                                                       0x2b2
6904  #define mmMVP_CRC_CNTL                                                          0x2b3
6905  #define mmMVP_CRC_RESULT_BLUE_GREEN                                             0x2b4
6906  #define mmMVP_CRC_RESULT_RED                                                    0x2b5
6907  #define mmMVP_CONTROL3                                                          0x2b6
6908  #define mmMVP_RECEIVE_CNT_CNTL1                                                 0x2b7
6909  #define mmMVP_RECEIVE_CNT_CNTL2                                                 0x2b8
6910  #define mmMVP_DEBUG                                                             0x2bb
6911  #define mmMVP_TEST_DEBUG_INDEX                                                  0x2b9
6912  #define mmMVP_TEST_DEBUG_DATA                                                   0x2ba
6913  #define ixMVP_DEBUG_12                                                          0xc
6914  #define ixMVP_DEBUG_13                                                          0xd
6915  #define ixMVP_DEBUG_14                                                          0xe
6916  #define ixMVP_DEBUG_15                                                          0xf
6917  #define ixMVP_DEBUG_16                                                          0x10
6918  #define ixMVP_DEBUG_17                                                          0x11
6919  #define mmSCL_COEF_RAM_SELECT                                                   0x1b40
6920  #define mmSCL0_SCL_COEF_RAM_SELECT                                              0x1b40
6921  #define mmSCL1_SCL_COEF_RAM_SELECT                                              0x1d40
6922  #define mmSCL2_SCL_COEF_RAM_SELECT                                              0x1f40
6923  #define mmSCL3_SCL_COEF_RAM_SELECT                                              0x4140
6924  #define mmSCL4_SCL_COEF_RAM_SELECT                                              0x4340
6925  #define mmSCL5_SCL_COEF_RAM_SELECT                                              0x4540
6926  #define mmSCL_COEF_RAM_TAP_DATA                                                 0x1b41
6927  #define mmSCL0_SCL_COEF_RAM_TAP_DATA                                            0x1b41
6928  #define mmSCL1_SCL_COEF_RAM_TAP_DATA                                            0x1d41
6929  #define mmSCL2_SCL_COEF_RAM_TAP_DATA                                            0x1f41
6930  #define mmSCL3_SCL_COEF_RAM_TAP_DATA                                            0x4141
6931  #define mmSCL4_SCL_COEF_RAM_TAP_DATA                                            0x4341
6932  #define mmSCL5_SCL_COEF_RAM_TAP_DATA                                            0x4541
6933  #define mmSCL_MODE                                                              0x1b42
6934  #define mmSCL0_SCL_MODE                                                         0x1b42
6935  #define mmSCL1_SCL_MODE                                                         0x1d42
6936  #define mmSCL2_SCL_MODE                                                         0x1f42
6937  #define mmSCL3_SCL_MODE                                                         0x4142
6938  #define mmSCL4_SCL_MODE                                                         0x4342
6939  #define mmSCL5_SCL_MODE                                                         0x4542
6940  #define mmSCL_TAP_CONTROL                                                       0x1b43
6941  #define mmSCL0_SCL_TAP_CONTROL                                                  0x1b43
6942  #define mmSCL1_SCL_TAP_CONTROL                                                  0x1d43
6943  #define mmSCL2_SCL_TAP_CONTROL                                                  0x1f43
6944  #define mmSCL3_SCL_TAP_CONTROL                                                  0x4143
6945  #define mmSCL4_SCL_TAP_CONTROL                                                  0x4343
6946  #define mmSCL5_SCL_TAP_CONTROL                                                  0x4543
6947  #define mmSCL_CONTROL                                                           0x1b44
6948  #define mmSCL0_SCL_CONTROL                                                      0x1b44
6949  #define mmSCL1_SCL_CONTROL                                                      0x1d44
6950  #define mmSCL2_SCL_CONTROL                                                      0x1f44
6951  #define mmSCL3_SCL_CONTROL                                                      0x4144
6952  #define mmSCL4_SCL_CONTROL                                                      0x4344
6953  #define mmSCL5_SCL_CONTROL                                                      0x4544
6954  #define mmSCL_BYPASS_CONTROL                                                    0x1b45
6955  #define mmSCL0_SCL_BYPASS_CONTROL                                               0x1b45
6956  #define mmSCL1_SCL_BYPASS_CONTROL                                               0x1d45
6957  #define mmSCL2_SCL_BYPASS_CONTROL                                               0x1f45
6958  #define mmSCL3_SCL_BYPASS_CONTROL                                               0x4145
6959  #define mmSCL4_SCL_BYPASS_CONTROL                                               0x4345
6960  #define mmSCL5_SCL_BYPASS_CONTROL                                               0x4545
6961  #define mmSCL_MANUAL_REPLICATE_CONTROL                                          0x1b46
6962  #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL                                     0x1b46
6963  #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL                                     0x1d46
6964  #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL                                     0x1f46
6965  #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                                     0x4146
6966  #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                                     0x4346
6967  #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                                     0x4546
6968  #define mmSCL_AUTOMATIC_MODE_CONTROL                                            0x1b47
6969  #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL                                       0x1b47
6970  #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL                                       0x1d47
6971  #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL                                       0x1f47
6972  #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                                       0x4147
6973  #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                                       0x4347
6974  #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                                       0x4547
6975  #define mmSCL_HORZ_FILTER_CONTROL                                               0x1b48
6976  #define mmSCL0_SCL_HORZ_FILTER_CONTROL                                          0x1b48
6977  #define mmSCL1_SCL_HORZ_FILTER_CONTROL                                          0x1d48
6978  #define mmSCL2_SCL_HORZ_FILTER_CONTROL                                          0x1f48
6979  #define mmSCL3_SCL_HORZ_FILTER_CONTROL                                          0x4148
6980  #define mmSCL4_SCL_HORZ_FILTER_CONTROL                                          0x4348
6981  #define mmSCL5_SCL_HORZ_FILTER_CONTROL                                          0x4548
6982  #define mmSCL_HORZ_FILTER_SCALE_RATIO                                           0x1b49
6983  #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1b49
6984  #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1d49
6985  #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                      0x1f49
6986  #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4149
6987  #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4349
6988  #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                                      0x4549
6989  #define mmSCL_HORZ_FILTER_INIT                                                  0x1b4a
6990  #define mmSCL0_SCL_HORZ_FILTER_INIT                                             0x1b4a
6991  #define mmSCL1_SCL_HORZ_FILTER_INIT                                             0x1d4a
6992  #define mmSCL2_SCL_HORZ_FILTER_INIT                                             0x1f4a
6993  #define mmSCL3_SCL_HORZ_FILTER_INIT                                             0x414a
6994  #define mmSCL4_SCL_HORZ_FILTER_INIT                                             0x434a
6995  #define mmSCL5_SCL_HORZ_FILTER_INIT                                             0x454a
6996  #define mmSCL_VERT_FILTER_CONTROL                                               0x1b4b
6997  #define mmSCL0_SCL_VERT_FILTER_CONTROL                                          0x1b4b
6998  #define mmSCL1_SCL_VERT_FILTER_CONTROL                                          0x1d4b
6999  #define mmSCL2_SCL_VERT_FILTER_CONTROL                                          0x1f4b
7000  #define mmSCL3_SCL_VERT_FILTER_CONTROL                                          0x414b
7001  #define mmSCL4_SCL_VERT_FILTER_CONTROL                                          0x434b
7002  #define mmSCL5_SCL_VERT_FILTER_CONTROL                                          0x454b
7003  #define mmSCL_VERT_FILTER_SCALE_RATIO                                           0x1b4c
7004  #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO                                      0x1b4c
7005  #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO                                      0x1d4c
7006  #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO                                      0x1f4c
7007  #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                                      0x414c
7008  #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                                      0x434c
7009  #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                                      0x454c
7010  #define mmSCL_VERT_FILTER_INIT                                                  0x1b4d
7011  #define mmSCL0_SCL_VERT_FILTER_INIT                                             0x1b4d
7012  #define mmSCL1_SCL_VERT_FILTER_INIT                                             0x1d4d
7013  #define mmSCL2_SCL_VERT_FILTER_INIT                                             0x1f4d
7014  #define mmSCL3_SCL_VERT_FILTER_INIT                                             0x414d
7015  #define mmSCL4_SCL_VERT_FILTER_INIT                                             0x434d
7016  #define mmSCL5_SCL_VERT_FILTER_INIT                                             0x454d
7017  #define mmSCL_VERT_FILTER_INIT_BOT                                              0x1b4e
7018  #define mmSCL0_SCL_VERT_FILTER_INIT_BOT                                         0x1b4e
7019  #define mmSCL1_SCL_VERT_FILTER_INIT_BOT                                         0x1d4e
7020  #define mmSCL2_SCL_VERT_FILTER_INIT_BOT                                         0x1f4e
7021  #define mmSCL3_SCL_VERT_FILTER_INIT_BOT                                         0x414e
7022  #define mmSCL4_SCL_VERT_FILTER_INIT_BOT                                         0x434e
7023  #define mmSCL5_SCL_VERT_FILTER_INIT_BOT                                         0x454e
7024  #define mmSCL_ROUND_OFFSET                                                      0x1b4f
7025  #define mmSCL0_SCL_ROUND_OFFSET                                                 0x1b4f
7026  #define mmSCL1_SCL_ROUND_OFFSET                                                 0x1d4f
7027  #define mmSCL2_SCL_ROUND_OFFSET                                                 0x1f4f
7028  #define mmSCL3_SCL_ROUND_OFFSET                                                 0x414f
7029  #define mmSCL4_SCL_ROUND_OFFSET                                                 0x434f
7030  #define mmSCL5_SCL_ROUND_OFFSET                                                 0x454f
7031  #define mmSCL_UPDATE                                                            0x1b51
7032  #define mmSCL0_SCL_UPDATE                                                       0x1b51
7033  #define mmSCL1_SCL_UPDATE                                                       0x1d51
7034  #define mmSCL2_SCL_UPDATE                                                       0x1f51
7035  #define mmSCL3_SCL_UPDATE                                                       0x4151
7036  #define mmSCL4_SCL_UPDATE                                                       0x4351
7037  #define mmSCL5_SCL_UPDATE                                                       0x4551
7038  #define mmSCL_F_SHARP_CONTROL                                                   0x1b53
7039  #define mmSCL0_SCL_F_SHARP_CONTROL                                              0x1b53
7040  #define mmSCL1_SCL_F_SHARP_CONTROL                                              0x1d53
7041  #define mmSCL2_SCL_F_SHARP_CONTROL                                              0x1f53
7042  #define mmSCL3_SCL_F_SHARP_CONTROL                                              0x4153
7043  #define mmSCL4_SCL_F_SHARP_CONTROL                                              0x4353
7044  #define mmSCL5_SCL_F_SHARP_CONTROL                                              0x4553
7045  #define mmSCL_ALU_CONTROL                                                       0x1b54
7046  #define mmSCL0_SCL_ALU_CONTROL                                                  0x1b54
7047  #define mmSCL1_SCL_ALU_CONTROL                                                  0x1d54
7048  #define mmSCL2_SCL_ALU_CONTROL                                                  0x1f54
7049  #define mmSCL3_SCL_ALU_CONTROL                                                  0x4154
7050  #define mmSCL4_SCL_ALU_CONTROL                                                  0x4354
7051  #define mmSCL5_SCL_ALU_CONTROL                                                  0x4554
7052  #define mmSCL_COEF_RAM_CONFLICT_STATUS                                          0x1b55
7053  #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1b55
7054  #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1d55
7055  #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS                                     0x1f55
7056  #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4155
7057  #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4355
7058  #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                                     0x4555
7059  #define mmVIEWPORT_START_SECONDARY                                              0x1b5b
7060  #define mmSCL0_VIEWPORT_START_SECONDARY                                         0x1b5b
7061  #define mmSCL1_VIEWPORT_START_SECONDARY                                         0x1d5b
7062  #define mmSCL2_VIEWPORT_START_SECONDARY                                         0x1f5b
7063  #define mmSCL3_VIEWPORT_START_SECONDARY                                         0x415b
7064  #define mmSCL4_VIEWPORT_START_SECONDARY                                         0x435b
7065  #define mmSCL5_VIEWPORT_START_SECONDARY                                         0x455b
7066  #define mmVIEWPORT_START                                                        0x1b5c
7067  #define mmSCL0_VIEWPORT_START                                                   0x1b5c
7068  #define mmSCL1_VIEWPORT_START                                                   0x1d5c
7069  #define mmSCL2_VIEWPORT_START                                                   0x1f5c
7070  #define mmSCL3_VIEWPORT_START                                                   0x415c
7071  #define mmSCL4_VIEWPORT_START                                                   0x435c
7072  #define mmSCL5_VIEWPORT_START                                                   0x455c
7073  #define mmVIEWPORT_SIZE                                                         0x1b5d
7074  #define mmSCL0_VIEWPORT_SIZE                                                    0x1b5d
7075  #define mmSCL1_VIEWPORT_SIZE                                                    0x1d5d
7076  #define mmSCL2_VIEWPORT_SIZE                                                    0x1f5d
7077  #define mmSCL3_VIEWPORT_SIZE                                                    0x415d
7078  #define mmSCL4_VIEWPORT_SIZE                                                    0x435d
7079  #define mmSCL5_VIEWPORT_SIZE                                                    0x455d
7080  #define mmEXT_OVERSCAN_LEFT_RIGHT                                               0x1b5e
7081  #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT                                          0x1b5e
7082  #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT                                          0x1d5e
7083  #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT                                          0x1f5e
7084  #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                                          0x415e
7085  #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                                          0x435e
7086  #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                                          0x455e
7087  #define mmEXT_OVERSCAN_TOP_BOTTOM                                               0x1b5f
7088  #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM                                          0x1b5f
7089  #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM                                          0x1d5f
7090  #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM                                          0x1f5f
7091  #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                                          0x415f
7092  #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                                          0x435f
7093  #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                                          0x455f
7094  #define mmSCL_MODE_CHANGE_DET1                                                  0x1b60
7095  #define mmSCL0_SCL_MODE_CHANGE_DET1                                             0x1b60
7096  #define mmSCL1_SCL_MODE_CHANGE_DET1                                             0x1d60
7097  #define mmSCL2_SCL_MODE_CHANGE_DET1                                             0x1f60
7098  #define mmSCL3_SCL_MODE_CHANGE_DET1                                             0x4160
7099  #define mmSCL4_SCL_MODE_CHANGE_DET1                                             0x4360
7100  #define mmSCL5_SCL_MODE_CHANGE_DET1                                             0x4560
7101  #define mmSCL_MODE_CHANGE_DET2                                                  0x1b61
7102  #define mmSCL0_SCL_MODE_CHANGE_DET2                                             0x1b61
7103  #define mmSCL1_SCL_MODE_CHANGE_DET2                                             0x1d61
7104  #define mmSCL2_SCL_MODE_CHANGE_DET2                                             0x1f61
7105  #define mmSCL3_SCL_MODE_CHANGE_DET2                                             0x4161
7106  #define mmSCL4_SCL_MODE_CHANGE_DET2                                             0x4361
7107  #define mmSCL5_SCL_MODE_CHANGE_DET2                                             0x4561
7108  #define mmSCL_MODE_CHANGE_DET3                                                  0x1b62
7109  #define mmSCL0_SCL_MODE_CHANGE_DET3                                             0x1b62
7110  #define mmSCL1_SCL_MODE_CHANGE_DET3                                             0x1d62
7111  #define mmSCL2_SCL_MODE_CHANGE_DET3                                             0x1f62
7112  #define mmSCL3_SCL_MODE_CHANGE_DET3                                             0x4162
7113  #define mmSCL4_SCL_MODE_CHANGE_DET3                                             0x4362
7114  #define mmSCL5_SCL_MODE_CHANGE_DET3                                             0x4562
7115  #define mmSCL_MODE_CHANGE_MASK                                                  0x1b63
7116  #define mmSCL0_SCL_MODE_CHANGE_MASK                                             0x1b63
7117  #define mmSCL1_SCL_MODE_CHANGE_MASK                                             0x1d63
7118  #define mmSCL2_SCL_MODE_CHANGE_MASK                                             0x1f63
7119  #define mmSCL3_SCL_MODE_CHANGE_MASK                                             0x4163
7120  #define mmSCL4_SCL_MODE_CHANGE_MASK                                             0x4363
7121  #define mmSCL5_SCL_MODE_CHANGE_MASK                                             0x4563
7122  #define mmSCL_DEBUG2                                                            0x1b69
7123  #define mmSCL0_SCL_DEBUG2                                                       0x1b69
7124  #define mmSCL1_SCL_DEBUG2                                                       0x1d69
7125  #define mmSCL2_SCL_DEBUG2                                                       0x1f69
7126  #define mmSCL3_SCL_DEBUG2                                                       0x4169
7127  #define mmSCL4_SCL_DEBUG2                                                       0x4369
7128  #define mmSCL5_SCL_DEBUG2                                                       0x4569
7129  #define mmSCL_DEBUG                                                             0x1b6a
7130  #define mmSCL0_SCL_DEBUG                                                        0x1b6a
7131  #define mmSCL1_SCL_DEBUG                                                        0x1d6a
7132  #define mmSCL2_SCL_DEBUG                                                        0x1f6a
7133  #define mmSCL3_SCL_DEBUG                                                        0x416a
7134  #define mmSCL4_SCL_DEBUG                                                        0x436a
7135  #define mmSCL5_SCL_DEBUG                                                        0x456a
7136  #define mmSCL_TEST_DEBUG_INDEX                                                  0x1b6b
7137  #define mmSCL0_SCL_TEST_DEBUG_INDEX                                             0x1b6b
7138  #define mmSCL1_SCL_TEST_DEBUG_INDEX                                             0x1d6b
7139  #define mmSCL2_SCL_TEST_DEBUG_INDEX                                             0x1f6b
7140  #define mmSCL3_SCL_TEST_DEBUG_INDEX                                             0x416b
7141  #define mmSCL4_SCL_TEST_DEBUG_INDEX                                             0x436b
7142  #define mmSCL5_SCL_TEST_DEBUG_INDEX                                             0x456b
7143  #define mmSCL_TEST_DEBUG_DATA                                                   0x1b6c
7144  #define mmSCL0_SCL_TEST_DEBUG_DATA                                              0x1b6c
7145  #define mmSCL1_SCL_TEST_DEBUG_DATA                                              0x1d6c
7146  #define mmSCL2_SCL_TEST_DEBUG_DATA                                              0x1f6c
7147  #define mmSCL3_SCL_TEST_DEBUG_DATA                                              0x416c
7148  #define mmSCL4_SCL_TEST_DEBUG_DATA                                              0x436c
7149  #define mmSCL5_SCL_TEST_DEBUG_DATA                                              0x456c
7150  #define mmSCLV_COEF_RAM_SELECT                                                  0x4670
7151  #define mmSCLV0_SCLV_COEF_RAM_SELECT                                            0x4670
7152  #define mmSCLV1_SCLV_COEF_RAM_SELECT                                            0x9870
7153  #define mmSCLV_COEF_RAM_TAP_DATA                                                0x4671
7154  #define mmSCLV0_SCLV_COEF_RAM_TAP_DATA                                          0x4671
7155  #define mmSCLV1_SCLV_COEF_RAM_TAP_DATA                                          0x9871
7156  #define mmSCLV_MODE                                                             0x4672
7157  #define mmSCLV0_SCLV_MODE                                                       0x4672
7158  #define mmSCLV1_SCLV_MODE                                                       0x9872
7159  #define mmSCLV_TAP_CONTROL                                                      0x4673
7160  #define mmSCLV0_SCLV_TAP_CONTROL                                                0x4673
7161  #define mmSCLV1_SCLV_TAP_CONTROL                                                0x9873
7162  #define mmSCLV_CONTROL                                                          0x4674
7163  #define mmSCLV0_SCLV_CONTROL                                                    0x4674
7164  #define mmSCLV1_SCLV_CONTROL                                                    0x9874
7165  #define mmSCLV_MANUAL_REPLICATE_CONTROL                                         0x4675
7166  #define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL                                   0x4675
7167  #define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL                                   0x9875
7168  #define mmSCLV_AUTOMATIC_MODE_CONTROL                                           0x4676
7169  #define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL                                     0x4676
7170  #define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL                                     0x9876
7171  #define mmSCLV_HORZ_FILTER_CONTROL                                              0x4677
7172  #define mmSCLV0_SCLV_HORZ_FILTER_CONTROL                                        0x4677
7173  #define mmSCLV1_SCLV_HORZ_FILTER_CONTROL                                        0x9877
7174  #define mmSCLV_HORZ_FILTER_SCALE_RATIO                                          0x4678
7175  #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO                                    0x4678
7176  #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO                                    0x9878
7177  #define mmSCLV_HORZ_FILTER_INIT                                                 0x4679
7178  #define mmSCLV0_SCLV_HORZ_FILTER_INIT                                           0x4679
7179  #define mmSCLV1_SCLV_HORZ_FILTER_INIT                                           0x9879
7180  #define mmSCLV_HORZ_FILTER_SCALE_RATIO_C                                        0x467a
7181  #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C                                  0x467a
7182  #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C                                  0x987a
7183  #define mmSCLV_HORZ_FILTER_INIT_C                                               0x467b
7184  #define mmSCLV0_SCLV_HORZ_FILTER_INIT_C                                         0x467b
7185  #define mmSCLV1_SCLV_HORZ_FILTER_INIT_C                                         0x987b
7186  #define mmSCLV_VERT_FILTER_CONTROL                                              0x467c
7187  #define mmSCLV0_SCLV_VERT_FILTER_CONTROL                                        0x467c
7188  #define mmSCLV1_SCLV_VERT_FILTER_CONTROL                                        0x987c
7189  #define mmSCLV_VERT_FILTER_SCALE_RATIO                                          0x467d
7190  #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO                                    0x467d
7191  #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO                                    0x987d
7192  #define mmSCLV_VERT_FILTER_INIT                                                 0x467e
7193  #define mmSCLV0_SCLV_VERT_FILTER_INIT                                           0x467e
7194  #define mmSCLV1_SCLV_VERT_FILTER_INIT                                           0x987e
7195  #define mmSCLV_VERT_FILTER_INIT_BOT                                             0x467f
7196  #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT                                       0x467f
7197  #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT                                       0x987f
7198  #define mmSCLV_VERT_FILTER_SCALE_RATIO_C                                        0x4680
7199  #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C                                  0x4680
7200  #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C                                  0x9880
7201  #define mmSCLV_VERT_FILTER_INIT_C                                               0x4681
7202  #define mmSCLV0_SCLV_VERT_FILTER_INIT_C                                         0x4681
7203  #define mmSCLV1_SCLV_VERT_FILTER_INIT_C                                         0x9881
7204  #define mmSCLV_VERT_FILTER_INIT_BOT_C                                           0x4682
7205  #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C                                     0x4682
7206  #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C                                     0x9882
7207  #define mmSCLV_ROUND_OFFSET                                                     0x4683
7208  #define mmSCLV0_SCLV_ROUND_OFFSET                                               0x4683
7209  #define mmSCLV1_SCLV_ROUND_OFFSET                                               0x9883
7210  #define mmSCLV_UPDATE                                                           0x4684
7211  #define mmSCLV0_SCLV_UPDATE                                                     0x4684
7212  #define mmSCLV1_SCLV_UPDATE                                                     0x9884
7213  #define mmSCLV_ALU_CONTROL                                                      0x4685
7214  #define mmSCLV0_SCLV_ALU_CONTROL                                                0x4685
7215  #define mmSCLV1_SCLV_ALU_CONTROL                                                0x9885
7216  #define mmSCLV_VIEWPORT_START                                                   0x4686
7217  #define mmSCLV0_SCLV_VIEWPORT_START                                             0x4686
7218  #define mmSCLV1_SCLV_VIEWPORT_START                                             0x9886
7219  #define mmSCLV_VIEWPORT_START_SECONDARY                                         0x4687
7220  #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY                                   0x4687
7221  #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY                                   0x9887
7222  #define mmSCLV_VIEWPORT_SIZE                                                    0x4688
7223  #define mmSCLV0_SCLV_VIEWPORT_SIZE                                              0x4688
7224  #define mmSCLV1_SCLV_VIEWPORT_SIZE                                              0x9888
7225  #define mmSCLV_VIEWPORT_START_C                                                 0x4689
7226  #define mmSCLV0_SCLV_VIEWPORT_START_C                                           0x4689
7227  #define mmSCLV1_SCLV_VIEWPORT_START_C                                           0x9889
7228  #define mmSCLV_VIEWPORT_START_SECONDARY_C                                       0x468a
7229  #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C                                 0x468a
7230  #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C                                 0x988a
7231  #define mmSCLV_VIEWPORT_SIZE_C                                                  0x468b
7232  #define mmSCLV0_SCLV_VIEWPORT_SIZE_C                                            0x468b
7233  #define mmSCLV1_SCLV_VIEWPORT_SIZE_C                                            0x988b
7234  #define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT                                          0x468c
7235  #define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT                                    0x468c
7236  #define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT                                    0x988c
7237  #define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM                                          0x468d
7238  #define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM                                    0x468d
7239  #define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM                                    0x988d
7240  #define mmSCLV_MODE_CHANGE_DET1                                                 0x468e
7241  #define mmSCLV0_SCLV_MODE_CHANGE_DET1                                           0x468e
7242  #define mmSCLV1_SCLV_MODE_CHANGE_DET1                                           0x988e
7243  #define mmSCLV_MODE_CHANGE_DET2                                                 0x468f
7244  #define mmSCLV0_SCLV_MODE_CHANGE_DET2                                           0x468f
7245  #define mmSCLV1_SCLV_MODE_CHANGE_DET2                                           0x988f
7246  #define mmSCLV_MODE_CHANGE_DET3                                                 0x4690
7247  #define mmSCLV0_SCLV_MODE_CHANGE_DET3                                           0x4690
7248  #define mmSCLV1_SCLV_MODE_CHANGE_DET3                                           0x9890
7249  #define mmSCLV_MODE_CHANGE_MASK                                                 0x4691
7250  #define mmSCLV0_SCLV_MODE_CHANGE_MASK                                           0x4691
7251  #define mmSCLV1_SCLV_MODE_CHANGE_MASK                                           0x9891
7252  #define mmSCLV_HORZ_FILTER_INIT_BOT                                             0x4692
7253  #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT                                       0x4692
7254  #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT                                       0x9892
7255  #define mmSCLV_HORZ_FILTER_INIT_BOT_C                                           0x4693
7256  #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C                                     0x4693
7257  #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C                                     0x9893
7258  #define mmSCLV_DEBUG2                                                           0x4694
7259  #define mmSCLV0_SCLV_DEBUG2                                                     0x4694
7260  #define mmSCLV1_SCLV_DEBUG2                                                     0x9894
7261  #define mmSCLV_DEBUG                                                            0x4695
7262  #define mmSCLV0_SCLV_DEBUG                                                      0x4695
7263  #define mmSCLV1_SCLV_DEBUG                                                      0x9895
7264  #define mmSCLV_TEST_DEBUG_INDEX                                                 0x4696
7265  #define mmSCLV0_SCLV_TEST_DEBUG_INDEX                                           0x4696
7266  #define mmSCLV1_SCLV_TEST_DEBUG_INDEX                                           0x9896
7267  #define mmSCLV_TEST_DEBUG_DATA                                                  0x4697
7268  #define mmSCLV0_SCLV_TEST_DEBUG_DATA                                            0x4697
7269  #define mmSCLV1_SCLV_TEST_DEBUG_DATA                                            0x9897
7270  #define mmCOL_MAN_UPDATE                                                        0x46a4
7271  #define mmCOL_MAN0_COL_MAN_UPDATE                                               0x46a4
7272  #define mmCOL_MAN1_COL_MAN_UPDATE                                               0x98a4
7273  #define mmCOL_MAN_INPUT_CSC_CONTROL                                             0x46a5
7274  #define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL                                    0x46a5
7275  #define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL                                    0x98a5
7276  #define mmINPUT_CSC_C11_C12_A                                                   0x46a6
7277  #define mmCOL_MAN0_INPUT_CSC_C11_C12_A                                          0x46a6
7278  #define mmCOL_MAN1_INPUT_CSC_C11_C12_A                                          0x98a6
7279  #define mmINPUT_CSC_C13_C14_A                                                   0x46a7
7280  #define mmCOL_MAN0_INPUT_CSC_C13_C14_A                                          0x46a7
7281  #define mmCOL_MAN1_INPUT_CSC_C13_C14_A                                          0x98a7
7282  #define mmINPUT_CSC_C21_C22_A                                                   0x46a8
7283  #define mmCOL_MAN0_INPUT_CSC_C21_C22_A                                          0x46a8
7284  #define mmCOL_MAN1_INPUT_CSC_C21_C22_A                                          0x98a8
7285  #define mmINPUT_CSC_C23_C24_A                                                   0x46a9
7286  #define mmCOL_MAN0_INPUT_CSC_C23_C24_A                                          0x46a9
7287  #define mmCOL_MAN1_INPUT_CSC_C23_C24_A                                          0x98a9
7288  #define mmINPUT_CSC_C31_C32_A                                                   0x46aa
7289  #define mmCOL_MAN0_INPUT_CSC_C31_C32_A                                          0x46aa
7290  #define mmCOL_MAN1_INPUT_CSC_C31_C32_A                                          0x98aa
7291  #define mmINPUT_CSC_C33_C34_A                                                   0x46ab
7292  #define mmCOL_MAN0_INPUT_CSC_C33_C34_A                                          0x46ab
7293  #define mmCOL_MAN1_INPUT_CSC_C33_C34_A                                          0x98ab
7294  #define mmINPUT_CSC_C11_C12_B                                                   0x46ac
7295  #define mmCOL_MAN0_INPUT_CSC_C11_C12_B                                          0x46ac
7296  #define mmCOL_MAN1_INPUT_CSC_C11_C12_B                                          0x98ac
7297  #define mmINPUT_CSC_C13_C14_B                                                   0x46ad
7298  #define mmCOL_MAN0_INPUT_CSC_C13_C14_B                                          0x46ad
7299  #define mmCOL_MAN1_INPUT_CSC_C13_C14_B                                          0x98ad
7300  #define mmINPUT_CSC_C21_C22_B                                                   0x46ae
7301  #define mmCOL_MAN0_INPUT_CSC_C21_C22_B                                          0x46ae
7302  #define mmCOL_MAN1_INPUT_CSC_C21_C22_B                                          0x98ae
7303  #define mmINPUT_CSC_C23_C24_B                                                   0x46af
7304  #define mmCOL_MAN0_INPUT_CSC_C23_C24_B                                          0x46af
7305  #define mmCOL_MAN1_INPUT_CSC_C23_C24_B                                          0x98af
7306  #define mmINPUT_CSC_C31_C32_B                                                   0x46b0
7307  #define mmCOL_MAN0_INPUT_CSC_C31_C32_B                                          0x46b0
7308  #define mmCOL_MAN1_INPUT_CSC_C31_C32_B                                          0x98b0
7309  #define mmINPUT_CSC_C33_C34_B                                                   0x46b1
7310  #define mmCOL_MAN0_INPUT_CSC_C33_C34_B                                          0x46b1
7311  #define mmCOL_MAN1_INPUT_CSC_C33_C34_B                                          0x98b1
7312  #define mmPRESCALE_CONTROL                                                      0x46b2
7313  #define mmCOL_MAN0_PRESCALE_CONTROL                                             0x46b2
7314  #define mmCOL_MAN1_PRESCALE_CONTROL                                             0x98b2
7315  #define mmPRESCALE_VALUES_R                                                     0x46b3
7316  #define mmCOL_MAN0_PRESCALE_VALUES_R                                            0x46b3
7317  #define mmCOL_MAN1_PRESCALE_VALUES_R                                            0x98b3
7318  #define mmPRESCALE_VALUES_G                                                     0x46b4
7319  #define mmCOL_MAN0_PRESCALE_VALUES_G                                            0x46b4
7320  #define mmCOL_MAN1_PRESCALE_VALUES_G                                            0x98b4
7321  #define mmPRESCALE_VALUES_B                                                     0x46b5
7322  #define mmCOL_MAN0_PRESCALE_VALUES_B                                            0x46b5
7323  #define mmCOL_MAN1_PRESCALE_VALUES_B                                            0x98b5
7324  #define mmCOL_MAN_OUTPUT_CSC_CONTROL                                            0x46b6
7325  #define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL                                   0x46b6
7326  #define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL                                   0x98b6
7327  #define mmOUTPUT_CSC_C11_C12_A                                                  0x46b7
7328  #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A                                         0x46b7
7329  #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A                                         0x98b7
7330  #define mmOUTPUT_CSC_C13_C14_A                                                  0x46b8
7331  #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A                                         0x46b8
7332  #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A                                         0x98b8
7333  #define mmOUTPUT_CSC_C21_C22_A                                                  0x46b9
7334  #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A                                         0x46b9
7335  #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A                                         0x98b9
7336  #define mmOUTPUT_CSC_C23_C24_A                                                  0x46ba
7337  #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A                                         0x46ba
7338  #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A                                         0x98ba
7339  #define mmOUTPUT_CSC_C31_C32_A                                                  0x46bb
7340  #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A                                         0x46bb
7341  #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A                                         0x98bb
7342  #define mmOUTPUT_CSC_C33_C34_A                                                  0x46bc
7343  #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A                                         0x46bc
7344  #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A                                         0x98bc
7345  #define mmOUTPUT_CSC_C11_C12_B                                                  0x46bd
7346  #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B                                         0x46bd
7347  #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B                                         0x98bd
7348  #define mmOUTPUT_CSC_C13_C14_B                                                  0x46be
7349  #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B                                         0x46be
7350  #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B                                         0x98be
7351  #define mmOUTPUT_CSC_C21_C22_B                                                  0x46bf
7352  #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B                                         0x46bf
7353  #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B                                         0x98bf
7354  #define mmOUTPUT_CSC_C23_C24_B                                                  0x46c0
7355  #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B                                         0x46c0
7356  #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B                                         0x98c0
7357  #define mmOUTPUT_CSC_C31_C32_B                                                  0x46c1
7358  #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B                                         0x46c1
7359  #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B                                         0x98c1
7360  #define mmOUTPUT_CSC_C33_C34_B                                                  0x46c2
7361  #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B                                         0x46c2
7362  #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B                                         0x98c2
7363  #define mmDENORM_CLAMP_CONTROL                                                  0x46c3
7364  #define mmCOL_MAN0_DENORM_CLAMP_CONTROL                                         0x46c3
7365  #define mmCOL_MAN1_DENORM_CLAMP_CONTROL                                         0x98c3
7366  #define mmDENORM_CLAMP_RANGE_R_CR                                               0x46c4
7367  #define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR                                      0x46c4
7368  #define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR                                      0x98c4
7369  #define mmDENORM_CLAMP_RANGE_G_Y                                                0x46c5
7370  #define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y                                       0x46c5
7371  #define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y                                       0x98c5
7372  #define mmDENORM_CLAMP_RANGE_B_CB                                               0x46c6
7373  #define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB                                      0x46c6
7374  #define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB                                      0x98c6
7375  #define mmCOL_MAN_FP_CONVERTED_FIELD                                            0x46c7
7376  #define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD                                   0x46c7
7377  #define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD                                   0x98c7
7378  #define mmGAMMA_CORR_CONTROL                                                    0x46c8
7379  #define mmCOL_MAN0_GAMMA_CORR_CONTROL                                           0x46c8
7380  #define mmCOL_MAN1_GAMMA_CORR_CONTROL                                           0x98c8
7381  #define mmGAMMA_CORR_LUT_INDEX                                                  0x46c9
7382  #define mmCOL_MAN0_GAMMA_CORR_LUT_INDEX                                         0x46c9
7383  #define mmCOL_MAN1_GAMMA_CORR_LUT_INDEX                                         0x98c9
7384  #define mmGAMMA_CORR_LUT_DATA                                                   0x46ca
7385  #define mmCOL_MAN0_GAMMA_CORR_LUT_DATA                                          0x46ca
7386  #define mmCOL_MAN1_GAMMA_CORR_LUT_DATA                                          0x98ca
7387  #define mmGAMMA_CORR_LUT_WRITE_EN_MASK                                          0x46cb
7388  #define mmCOL_MAN0_GAMMA_CORR_LUT_WRITE_EN_MASK                                 0x46cb
7389  #define mmCOL_MAN1_GAMMA_CORR_LUT_WRITE_EN_MASK                                 0x98cb
7390  #define mmGAMMA_CORR_CNTLA_START_CNTL                                           0x46cc
7391  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_START_CNTL                                  0x46cc
7392  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_START_CNTL                                  0x98cc
7393  #define mmGAMMA_CORR_CNTLA_SLOPE_CNTL                                           0x46cd
7394  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_SLOPE_CNTL                                  0x46cd
7395  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_SLOPE_CNTL                                  0x98cd
7396  #define mmGAMMA_CORR_CNTLA_END_CNTL1                                            0x46ce
7397  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL1                                   0x46ce
7398  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL1                                   0x98ce
7399  #define mmGAMMA_CORR_CNTLA_END_CNTL2                                            0x46cf
7400  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL2                                   0x46cf
7401  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL2                                   0x98cf
7402  #define mmGAMMA_CORR_CNTLA_REGION_0_1                                           0x46d0
7403  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_0_1                                  0x46d0
7404  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_0_1                                  0x98d0
7405  #define mmGAMMA_CORR_CNTLA_REGION_2_3                                           0x46d1
7406  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_2_3                                  0x46d1
7407  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_2_3                                  0x98d1
7408  #define mmGAMMA_CORR_CNTLA_REGION_4_5                                           0x46d2
7409  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_4_5                                  0x46d2
7410  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_4_5                                  0x98d2
7411  #define mmGAMMA_CORR_CNTLA_REGION_6_7                                           0x46d3
7412  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_6_7                                  0x46d3
7413  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_6_7                                  0x98d3
7414  #define mmGAMMA_CORR_CNTLA_REGION_8_9                                           0x46d4
7415  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_8_9                                  0x46d4
7416  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_8_9                                  0x98d4
7417  #define mmGAMMA_CORR_CNTLA_REGION_10_11                                         0x46d5
7418  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_10_11                                0x46d5
7419  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_10_11                                0x98d5
7420  #define mmGAMMA_CORR_CNTLA_REGION_12_13                                         0x46d6
7421  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_12_13                                0x46d6
7422  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_12_13                                0x98d6
7423  #define mmGAMMA_CORR_CNTLA_REGION_14_15                                         0x46d7
7424  #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_14_15                                0x46d7
7425  #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_14_15                                0x98d7
7426  #define mmGAMMA_CORR_CNTLB_START_CNTL                                           0x46d8
7427  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_START_CNTL                                  0x46d8
7428  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_START_CNTL                                  0x98d8
7429  #define mmGAMMA_CORR_CNTLB_SLOPE_CNTL                                           0x46d9
7430  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_SLOPE_CNTL                                  0x46d9
7431  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_SLOPE_CNTL                                  0x98d9
7432  #define mmGAMMA_CORR_CNTLB_END_CNTL1                                            0x46da
7433  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL1                                   0x46da
7434  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL1                                   0x98da
7435  #define mmGAMMA_CORR_CNTLB_END_CNTL2                                            0x46db
7436  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL2                                   0x46db
7437  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL2                                   0x98db
7438  #define mmGAMMA_CORR_CNTLB_REGION_0_1                                           0x46dc
7439  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_0_1                                  0x46dc
7440  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_0_1                                  0x98dc
7441  #define mmGAMMA_CORR_CNTLB_REGION_2_3                                           0x46dd
7442  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_2_3                                  0x46dd
7443  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_2_3                                  0x98dd
7444  #define mmGAMMA_CORR_CNTLB_REGION_4_5                                           0x46de
7445  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_4_5                                  0x46de
7446  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_4_5                                  0x98de
7447  #define mmGAMMA_CORR_CNTLB_REGION_6_7                                           0x46df
7448  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_6_7                                  0x46df
7449  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_6_7                                  0x98df
7450  #define mmGAMMA_CORR_CNTLB_REGION_8_9                                           0x46e0
7451  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_8_9                                  0x46e0
7452  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_8_9                                  0x98e0
7453  #define mmGAMMA_CORR_CNTLB_REGION_10_11                                         0x46e1
7454  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_10_11                                0x46e1
7455  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_10_11                                0x98e1
7456  #define mmGAMMA_CORR_CNTLB_REGION_12_13                                         0x46e2
7457  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_12_13                                0x46e2
7458  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_12_13                                0x98e2
7459  #define mmGAMMA_CORR_CNTLB_REGION_14_15                                         0x46e3
7460  #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_14_15                                0x46e3
7461  #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_14_15                                0x98e3
7462  #define mmPACK_FIFO_ERROR                                                       0x46e4
7463  #define mmCOL_MAN0_PACK_FIFO_ERROR                                              0x46e4
7464  #define mmCOL_MAN1_PACK_FIFO_ERROR                                              0x98e4
7465  #define mmOUTPUT_FIFO_ERROR                                                     0x46e5
7466  #define mmCOL_MAN0_OUTPUT_FIFO_ERROR                                            0x46e5
7467  #define mmCOL_MAN1_OUTPUT_FIFO_ERROR                                            0x98e5
7468  #define mmINPUT_GAMMA_LUT_AUTOFILL                                              0x46e6
7469  #define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL                                     0x46e6
7470  #define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL                                     0x98e6
7471  #define mmINPUT_GAMMA_LUT_RW_INDEX                                              0x46e7
7472  #define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX                                     0x46e7
7473  #define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX                                     0x98e7
7474  #define mmINPUT_GAMMA_LUT_SEQ_COLOR                                             0x46e8
7475  #define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR                                    0x46e8
7476  #define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR                                    0x98e8
7477  #define mmINPUT_GAMMA_LUT_PWL_DATA                                              0x46e9
7478  #define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA                                     0x46e9
7479  #define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA                                     0x98e9
7480  #define mmINPUT_GAMMA_LUT_30_COLOR                                              0x46ea
7481  #define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR                                     0x46ea
7482  #define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR                                     0x98ea
7483  #define mmCOL_MAN_INPUT_GAMMA_CONTROL1                                          0x46eb
7484  #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1                                 0x46eb
7485  #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1                                 0x98eb
7486  #define mmCOL_MAN_INPUT_GAMMA_CONTROL2                                          0x46ec
7487  #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2                                 0x46ec
7488  #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2                                 0x98ec
7489  #define mmINPUT_GAMMA_BW_OFFSETS_B                                              0x46ed
7490  #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B                                     0x46ed
7491  #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B                                     0x98ed
7492  #define mmINPUT_GAMMA_BW_OFFSETS_G                                              0x46ee
7493  #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G                                     0x46ee
7494  #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G                                     0x98ee
7495  #define mmINPUT_GAMMA_BW_OFFSETS_R                                              0x46ef
7496  #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R                                     0x46ef
7497  #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R                                     0x98ef
7498  #define mmCOL_MAN_DEBUG_CONTROL                                                 0x46f0
7499  #define mmCOL_MAN0_COL_MAN_DEBUG_CONTROL                                        0x46f0
7500  #define mmCOL_MAN1_COL_MAN_DEBUG_CONTROL                                        0x98f0
7501  #define mmCOL_MAN_TEST_DEBUG_INDEX                                              0x46f1
7502  #define mmCOL_MAN0_COL_MAN_TEST_DEBUG_INDEX                                     0x46f1
7503  #define mmCOL_MAN1_COL_MAN_TEST_DEBUG_INDEX                                     0x98f1
7504  #define mmCOL_MAN_TEST_DEBUG_DATA                                               0x46f3
7505  #define mmCOL_MAN0_COL_MAN_TEST_DEBUG_DATA                                      0x46f3
7506  #define mmCOL_MAN1_COL_MAN_TEST_DEBUG_DATA                                      0x98f3
7507  #define mmUNP_GRPH_ENABLE                                                       0x4600
7508  #define mmUNP0_UNP_GRPH_ENABLE                                                  0x4600
7509  #define mmUNP1_UNP_GRPH_ENABLE                                                  0x9800
7510  #define mmUNP_GRPH_CONTROL                                                      0x4601
7511  #define mmUNP0_UNP_GRPH_CONTROL                                                 0x4601
7512  #define mmUNP1_UNP_GRPH_CONTROL                                                 0x9801
7513  #define mmUNP_GRPH_CONTROL_C                                                    0x4602
7514  #define mmUNP0_UNP_GRPH_CONTROL_C                                               0x4602
7515  #define mmUNP1_UNP_GRPH_CONTROL_C                                               0x9802
7516  #define mmUNP_GRPH_CONTROL_EXP                                                  0x4603
7517  #define mmUNP0_UNP_GRPH_CONTROL_EXP                                             0x4603
7518  #define mmUNP1_UNP_GRPH_CONTROL_EXP                                             0x9803
7519  #define mmUNP_GRPH_SWAP_CNTL                                                    0x4605
7520  #define mmUNP0_UNP_GRPH_SWAP_CNTL                                               0x4605
7521  #define mmUNP1_UNP_GRPH_SWAP_CNTL                                               0x9805
7522  #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                                    0x4606
7523  #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                               0x4606
7524  #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                               0x9806
7525  #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                                    0x4607
7526  #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                               0x4607
7527  #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                               0x9807
7528  #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                               0x4608
7529  #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                          0x4608
7530  #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                          0x9808
7531  #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                               0x4609
7532  #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                          0x4609
7533  #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                          0x9809
7534  #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                             0x460a
7535  #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                        0x460a
7536  #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                        0x980a
7537  #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                             0x460b
7538  #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                        0x460b
7539  #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                        0x980b
7540  #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                        0x460c
7541  #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                   0x460c
7542  #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                   0x980c
7543  #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                        0x460d
7544  #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                   0x460d
7545  #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                   0x980d
7546  #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                                  0x460e
7547  #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                             0x460e
7548  #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                             0x980e
7549  #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                                  0x460f
7550  #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                             0x460f
7551  #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                             0x980f
7552  #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                             0x4610
7553  #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                        0x4610
7554  #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                        0x9810
7555  #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                             0x4611
7556  #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                        0x4611
7557  #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                        0x9811
7558  #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                           0x4612
7559  #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                      0x4612
7560  #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                      0x9812
7561  #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                           0x4613
7562  #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                      0x4613
7563  #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                      0x9813
7564  #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                      0x4614
7565  #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                 0x4614
7566  #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                 0x9814
7567  #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                      0x4615
7568  #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                 0x4615
7569  #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                 0x9815
7570  #define mmUNP_GRPH_PITCH_L                                                      0x4616
7571  #define mmUNP0_UNP_GRPH_PITCH_L                                                 0x4616
7572  #define mmUNP1_UNP_GRPH_PITCH_L                                                 0x9816
7573  #define mmUNP_GRPH_PITCH_C                                                      0x4617
7574  #define mmUNP0_UNP_GRPH_PITCH_C                                                 0x4617
7575  #define mmUNP1_UNP_GRPH_PITCH_C                                                 0x9817
7576  #define mmUNP_GRPH_SURFACE_OFFSET_X_L                                           0x4618
7577  #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L                                      0x4618
7578  #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L                                      0x9818
7579  #define mmUNP_GRPH_SURFACE_OFFSET_X_C                                           0x4619
7580  #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C                                      0x4619
7581  #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C                                      0x9819
7582  #define mmUNP_GRPH_SURFACE_OFFSET_Y_L                                           0x461a
7583  #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L                                      0x461a
7584  #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L                                      0x981a
7585  #define mmUNP_GRPH_SURFACE_OFFSET_Y_C                                           0x461b
7586  #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C                                      0x461b
7587  #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C                                      0x981b
7588  #define mmUNP_GRPH_X_START_L                                                    0x461c
7589  #define mmUNP0_UNP_GRPH_X_START_L                                               0x461c
7590  #define mmUNP1_UNP_GRPH_X_START_L                                               0x981c
7591  #define mmUNP_GRPH_X_START_C                                                    0x461d
7592  #define mmUNP0_UNP_GRPH_X_START_C                                               0x461d
7593  #define mmUNP1_UNP_GRPH_X_START_C                                               0x981d
7594  #define mmUNP_GRPH_Y_START_L                                                    0x461e
7595  #define mmUNP0_UNP_GRPH_Y_START_L                                               0x461e
7596  #define mmUNP1_UNP_GRPH_Y_START_L                                               0x981e
7597  #define mmUNP_GRPH_Y_START_C                                                    0x461f
7598  #define mmUNP0_UNP_GRPH_Y_START_C                                               0x461f
7599  #define mmUNP1_UNP_GRPH_Y_START_C                                               0x981f
7600  #define mmUNP_GRPH_X_END_L                                                      0x4620
7601  #define mmUNP0_UNP_GRPH_X_END_L                                                 0x4620
7602  #define mmUNP1_UNP_GRPH_X_END_L                                                 0x9820
7603  #define mmUNP_GRPH_X_END_C                                                      0x4621
7604  #define mmUNP0_UNP_GRPH_X_END_C                                                 0x4621
7605  #define mmUNP1_UNP_GRPH_X_END_C                                                 0x9821
7606  #define mmUNP_GRPH_Y_END_L                                                      0x4622
7607  #define mmUNP0_UNP_GRPH_Y_END_L                                                 0x4622
7608  #define mmUNP1_UNP_GRPH_Y_END_L                                                 0x9822
7609  #define mmUNP_GRPH_Y_END_C                                                      0x4623
7610  #define mmUNP0_UNP_GRPH_Y_END_C                                                 0x4623
7611  #define mmUNP1_UNP_GRPH_Y_END_C                                                 0x9823
7612  #define mmUNP_GRPH_UPDATE                                                       0x4624
7613  #define mmUNP0_UNP_GRPH_UPDATE                                                  0x4624
7614  #define mmUNP1_UNP_GRPH_UPDATE                                                  0x9824
7615  #define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT                                    0x463a
7616  #define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT                               0x463a
7617  #define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT                               0x983a
7618  #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L                                      0x4625
7619  #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L                                 0x4625
7620  #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L                                 0x9825
7621  #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C                                      0x4626
7622  #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C                                 0x4626
7623  #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C                                 0x9826
7624  #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                                 0x4627
7625  #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                            0x4627
7626  #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                            0x9827
7627  #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                                 0x4628
7628  #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                            0x4628
7629  #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                            0x9828
7630  #define mmUNP_DVMM_PTE_CONTROL                                                  0x4629
7631  #define mmUNP_GRPH_INTERRUPT_STATUS                                             0x462b
7632  #define mmUNP0_UNP_GRPH_INTERRUPT_STATUS                                        0x462b
7633  #define mmUNP1_UNP_GRPH_INTERRUPT_STATUS                                        0x982b
7634  #define mmUNP_GRPH_INTERRUPT_CONTROL                                            0x462c
7635  #define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL                                       0x462c
7636  #define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL                                       0x982c
7637  #define mmUNP_GRPH_STEREOSYNC_FLIP                                              0x462e
7638  #define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP                                         0x462e
7639  #define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP                                         0x982e
7640  #define mmUNP_FLIP_CONTROL                                                      0x462f
7641  #define mmUNP0_UNP_FLIP_CONTROL                                                 0x462f
7642  #define mmUNP1_UNP_FLIP_CONTROL                                                 0x982f
7643  #define mmUNP_CRC_CONTROL                                                       0x4630
7644  #define mmUNP0_UNP_CRC_CONTROL                                                  0x4630
7645  #define mmUNP1_UNP_CRC_CONTROL                                                  0x9830
7646  #define mmUNP_CRC_MASK                                                          0x4631
7647  #define mmUNP0_UNP_CRC_MASK                                                     0x4631
7648  #define mmUNP1_UNP_CRC_MASK                                                     0x9831
7649  #define mmUNP_CRC_CURRENT                                                       0x4632
7650  #define mmUNP0_UNP_CRC_CURRENT                                                  0x4632
7651  #define mmUNP1_UNP_CRC_CURRENT                                                  0x9832
7652  #define mmUNP_CRC_LAST                                                          0x4633
7653  #define mmUNP0_UNP_CRC_LAST                                                     0x4633
7654  #define mmUNP1_UNP_CRC_LAST                                                     0x9833
7655  #define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK                                         0x4634
7656  #define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x4634
7657  #define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK                                    0x9834
7658  #define mmUNP_HW_ROTATION                                                       0x4635
7659  #define mmUNP0_UNP_HW_ROTATION                                                  0x4635
7660  #define mmUNP1_UNP_HW_ROTATION                                                  0x9835
7661  #define mmUNP_DEBUG                                                             0x4636
7662  #define mmUNP0_UNP_DEBUG                                                        0x4636
7663  #define mmUNP1_UNP_DEBUG                                                        0x9836
7664  #define mmUNP_DEBUG2                                                            0x4637
7665  #define mmUNP0_UNP_DEBUG2                                                       0x4637
7666  #define mmUNP1_UNP_DEBUG2                                                       0x9837
7667  #define mmUNP_DVMM_DEBUG                                                        0x463b
7668  #define mmUNP0_UNP_DVMM_DEBUG                                                   0x463b
7669  #define mmUNP1_UNP_DVMM_DEBUG                                                   0x983b
7670  #define mmUNP_TEST_DEBUG_INDEX                                                  0x4638
7671  #define mmUNP0_UNP_TEST_DEBUG_INDEX                                             0x4638
7672  #define mmUNP1_UNP_TEST_DEBUG_INDEX                                             0x9838
7673  #define mmUNP_TEST_DEBUG_DATA                                                   0x4639
7674  #define mmUNP0_UNP_TEST_DEBUG_DATA                                              0x4639
7675  #define mmUNP1_UNP_TEST_DEBUG_DATA                                              0x9839
7676  #define mmGENMO_WT                                                              0xf0
7677  #define mmGENMO_RD                                                              0xf3
7678  #define mmGENENB                                                                0xf0
7679  #define mmGENFC_WT                                                              0xee
7680  #define mmVGA0_GENFC_WT                                                         0xee
7681  #define mmVGA1_GENFC_WT                                                         0xf6
7682  #define mmGENFC_RD                                                              0xf2
7683  #define mmGENS0                                                                 0xf0
7684  #define mmGENS1                                                                 0xee
7685  #define mmVGA0_GENS1                                                            0xee
7686  #define mmVGA1_GENS1                                                            0xf6
7687  #define mmDAC_DATA                                                              0xf2
7688  #define mmDAC_MASK                                                              0xf1
7689  #define mmDAC_R_INDEX                                                           0xf1
7690  #define mmDAC_W_INDEX                                                           0xf2
7691  #define mmSEQ8_IDX                                                              0xf1
7692  #define mmSEQ8_DATA                                                             0xf1
7693  #define ixSEQ00                                                                 0x0
7694  #define ixSEQ01                                                                 0x1
7695  #define ixSEQ02                                                                 0x2
7696  #define ixSEQ03                                                                 0x3
7697  #define ixSEQ04                                                                 0x4
7698  #define mmCRTC8_IDX                                                             0xed
7699  #define mmVGA0_CRTC8_IDX                                                        0xed
7700  #define mmVGA1_CRTC8_IDX                                                        0xf5
7701  #define mmCRTC8_DATA                                                            0xed
7702  #define mmVGA0_CRTC8_DATA                                                       0xed
7703  #define mmVGA1_CRTC8_DATA                                                       0xf5
7704  #define ixCRT00                                                                 0x0
7705  #define ixCRT01                                                                 0x1
7706  #define ixCRT02                                                                 0x2
7707  #define ixCRT03                                                                 0x3
7708  #define ixCRT04                                                                 0x4
7709  #define ixCRT05                                                                 0x5
7710  #define ixCRT06                                                                 0x6
7711  #define ixCRT07                                                                 0x7
7712  #define ixCRT08                                                                 0x8
7713  #define ixCRT09                                                                 0x9
7714  #define ixCRT0A                                                                 0xa
7715  #define ixCRT0B                                                                 0xb
7716  #define ixCRT0C                                                                 0xc
7717  #define ixCRT0D                                                                 0xd
7718  #define ixCRT0E                                                                 0xe
7719  #define ixCRT0F                                                                 0xf
7720  #define ixCRT10                                                                 0x10
7721  #define ixCRT11                                                                 0x11
7722  #define ixCRT12                                                                 0x12
7723  #define ixCRT13                                                                 0x13
7724  #define ixCRT14                                                                 0x14
7725  #define ixCRT15                                                                 0x15
7726  #define ixCRT16                                                                 0x16
7727  #define ixCRT17                                                                 0x17
7728  #define ixCRT18                                                                 0x18
7729  #define ixCRT1E                                                                 0x1e
7730  #define ixCRT1F                                                                 0x1f
7731  #define ixCRT22                                                                 0x22
7732  #define mmGRPH8_IDX                                                             0xf3
7733  #define mmGRPH8_DATA                                                            0xf3
7734  #define ixGRA00                                                                 0x0
7735  #define ixGRA01                                                                 0x1
7736  #define ixGRA02                                                                 0x2
7737  #define ixGRA03                                                                 0x3
7738  #define ixGRA04                                                                 0x4
7739  #define ixGRA05                                                                 0x5
7740  #define ixGRA06                                                                 0x6
7741  #define ixGRA07                                                                 0x7
7742  #define ixGRA08                                                                 0x8
7743  #define mmATTRX                                                                 0xf0
7744  #define mmATTRDW                                                                0xf0
7745  #define mmATTRDR                                                                0xf0
7746  #define ixATTR00                                                                0x0
7747  #define ixATTR01                                                                0x1
7748  #define ixATTR02                                                                0x2
7749  #define ixATTR03                                                                0x3
7750  #define ixATTR04                                                                0x4
7751  #define ixATTR05                                                                0x5
7752  #define ixATTR06                                                                0x6
7753  #define ixATTR07                                                                0x7
7754  #define ixATTR08                                                                0x8
7755  #define ixATTR09                                                                0x9
7756  #define ixATTR0A                                                                0xa
7757  #define ixATTR0B                                                                0xb
7758  #define ixATTR0C                                                                0xc
7759  #define ixATTR0D                                                                0xd
7760  #define ixATTR0E                                                                0xe
7761  #define ixATTR0F                                                                0xf
7762  #define ixATTR10                                                                0x10
7763  #define ixATTR11                                                                0x11
7764  #define ixATTR12                                                                0x12
7765  #define ixATTR13                                                                0x13
7766  #define ixATTR14                                                                0x14
7767  #define mmVGA_RENDER_CONTROL                                                    0xc0
7768  #define mmVGA_SOURCE_SELECT                                                     0xfc
7769  #define mmVGA_SEQUENCER_RESET_CONTROL                                           0xc1
7770  #define mmVGA_MODE_CONTROL                                                      0xc2
7771  #define mmVGA_SURFACE_PITCH_SELECT                                              0xc3
7772  #define mmVGA_MEMORY_BASE_ADDRESS                                               0xc4
7773  #define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                          0xc9
7774  #define mmVGA_DISPBUF1_SURFACE_ADDR                                             0xc6
7775  #define mmVGA_DISPBUF2_SURFACE_ADDR                                             0xc8
7776  #define mmVGA_HDP_CONTROL                                                       0xca
7777  #define mmVGA_CACHE_CONTROL                                                     0xcb
7778  #define mmD1VGA_CONTROL                                                         0xcc
7779  #define mmD2VGA_CONTROL                                                         0xce
7780  #define mmD3VGA_CONTROL                                                         0xf8
7781  #define mmD4VGA_CONTROL                                                         0xf9
7782  #define mmD5VGA_CONTROL                                                         0xfa
7783  #define mmD6VGA_CONTROL                                                         0xfb
7784  #define mmVGA_HW_DEBUG                                                          0xcf
7785  #define mmVGA_STATUS                                                            0xd0
7786  #define mmVGA_INTERRUPT_CONTROL                                                 0xd1
7787  #define mmVGA_STATUS_CLEAR                                                      0xd2
7788  #define mmVGA_INTERRUPT_STATUS                                                  0xd3
7789  #define mmVGA_MAIN_CONTROL                                                      0xd4
7790  #define mmVGA_TEST_CONTROL                                                      0xd5
7791  #define mmVGA_DEBUG_READBACK_INDEX                                              0xd6
7792  #define mmVGA_DEBUG_READBACK_DATA                                               0xd7
7793  #define mmVGA_MEM_WRITE_PAGE_ADDR                                               0x12
7794  #define mmVGA_MEM_READ_PAGE_ADDR                                                0x13
7795  #define mmVGA_TEST_DEBUG_INDEX                                                  0xc5
7796  #define mmVGA_TEST_DEBUG_DATA                                                   0xc7
7797  #define ixVGADCC_DBG_DCCIF_C                                                    0x7e
7798  #define mmBPHYC_DAC_MACRO_CNTL                                                  0x48b9
7799  #define mmBPHYC_DAC_AUTO_CALIB_CONTROL                                          0x48ba
7800  #define mmDPG_PIPE_ARBITRATION_CONTROL1                                         0x1b30
7801  #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1                                0x1b30
7802  #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1                                0x1d30
7803  #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1                                0x1f30
7804  #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                                0x4130
7805  #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                                0x4330
7806  #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                                0x4530
7807  #define mmDPG_PIPE_ARBITRATION_CONTROL2                                         0x1b31
7808  #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2                                0x1b31
7809  #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2                                0x1d31
7810  #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2                                0x1f31
7811  #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                                0x4131
7812  #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                                0x4331
7813  #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                                0x4531
7814  #define mmDPG_WATERMARK_MASK_CONTROL                                            0x1b32
7815  #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL                                   0x1b32
7816  #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL                                   0x1d32
7817  #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL                                   0x1f32
7818  #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                                   0x4132
7819  #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                                   0x4332
7820  #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                                   0x4532
7821  #define mmDPG_PIPE_URGENCY_CONTROL                                              0x1b33
7822  #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL                                     0x1b33
7823  #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL                                     0x1d33
7824  #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL                                     0x1f33
7825  #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                                     0x4133
7826  #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                                     0x4333
7827  #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                                     0x4533
7828  #define mmDPG_PIPE_DPM_CONTROL                                                  0x1b34
7829  #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL                                         0x1b34
7830  #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL                                         0x1d34
7831  #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL                                         0x1f34
7832  #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL                                         0x4134
7833  #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL                                         0x4334
7834  #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL                                         0x4534
7835  #define mmDPG_PIPE_STUTTER_CONTROL                                              0x1b35
7836  #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL                                     0x1b35
7837  #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL                                     0x1d35
7838  #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL                                     0x1f35
7839  #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                                     0x4135
7840  #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                                     0x4335
7841  #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                                     0x4535
7842  #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL                                     0x1b36
7843  #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1b36
7844  #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1d36
7845  #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x1f36
7846  #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4136
7847  #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4336
7848  #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL                            0x4536
7849  #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH                                     0x1b37
7850  #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1b37
7851  #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1d37
7852  #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x1f37
7853  #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4137
7854  #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4337
7855  #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH                            0x4537
7856  #define mmDPG_REPEATER_PROGRAM                                                  0x1b3a
7857  #define mmDMIF_PG0_DPG_REPEATER_PROGRAM                                         0x1b3a
7858  #define mmDMIF_PG1_DPG_REPEATER_PROGRAM                                         0x1d3a
7859  #define mmDMIF_PG2_DPG_REPEATER_PROGRAM                                         0x1f3a
7860  #define mmDMIF_PG3_DPG_REPEATER_PROGRAM                                         0x413a
7861  #define mmDMIF_PG4_DPG_REPEATER_PROGRAM                                         0x433a
7862  #define mmDMIF_PG5_DPG_REPEATER_PROGRAM                                         0x453a
7863  #define mmDPG_HW_DEBUG_A                                                        0x1b3b
7864  #define mmDMIF_PG0_DPG_HW_DEBUG_A                                               0x1b3b
7865  #define mmDMIF_PG1_DPG_HW_DEBUG_A                                               0x1d3b
7866  #define mmDMIF_PG2_DPG_HW_DEBUG_A                                               0x1f3b
7867  #define mmDMIF_PG3_DPG_HW_DEBUG_A                                               0x413b
7868  #define mmDMIF_PG4_DPG_HW_DEBUG_A                                               0x433b
7869  #define mmDMIF_PG5_DPG_HW_DEBUG_A                                               0x453b
7870  #define mmDPG_HW_DEBUG_B                                                        0x1b3c
7871  #define mmDMIF_PG0_DPG_HW_DEBUG_B                                               0x1b3c
7872  #define mmDMIF_PG1_DPG_HW_DEBUG_B                                               0x1d3c
7873  #define mmDMIF_PG2_DPG_HW_DEBUG_B                                               0x1f3c
7874  #define mmDMIF_PG3_DPG_HW_DEBUG_B                                               0x413c
7875  #define mmDMIF_PG4_DPG_HW_DEBUG_B                                               0x433c
7876  #define mmDMIF_PG5_DPG_HW_DEBUG_B                                               0x453c
7877  #define mmDPG_HW_DEBUG_11                                                       0x1b3d
7878  #define mmDMIF_PG0_DPG_HW_DEBUG_11                                              0x1b3d
7879  #define mmDMIF_PG1_DPG_HW_DEBUG_11                                              0x1d3d
7880  #define mmDMIF_PG2_DPG_HW_DEBUG_11                                              0x1f3d
7881  #define mmDMIF_PG3_DPG_HW_DEBUG_11                                              0x413d
7882  #define mmDMIF_PG4_DPG_HW_DEBUG_11                                              0x433d
7883  #define mmDMIF_PG5_DPG_HW_DEBUG_11                                              0x453d
7884  #define mmDPG_CHK_PRE_PROC_CNTL                                                 0x1b3e
7885  #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL                                        0x1b3e
7886  #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL                                        0x1d3e
7887  #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL                                        0x1f3e
7888  #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL                                        0x413e
7889  #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL                                        0x433e
7890  #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL                                        0x453e
7891  #define mmDPG_DVMM_STATUS                                                       0x1b3f
7892  #define mmDMIF_PG0_DPG_DVMM_STATUS                                              0x1b3f
7893  #define mmDMIF_PG1_DPG_DVMM_STATUS                                              0x1d3f
7894  #define mmDMIF_PG2_DPG_DVMM_STATUS                                              0x1f3f
7895  #define mmDMIF_PG3_DPG_DVMM_STATUS                                              0x413f
7896  #define mmDMIF_PG4_DPG_DVMM_STATUS                                              0x433f
7897  #define mmDMIF_PG5_DPG_DVMM_STATUS                                              0x453f
7898  #define mmDPG_TEST_DEBUG_INDEX                                                  0x1b38
7899  #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX                                         0x1b38
7900  #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX                                         0x1d38
7901  #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX                                         0x1f38
7902  #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX                                         0x4138
7903  #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX                                         0x4338
7904  #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX                                         0x4538
7905  #define mmDPG_TEST_DEBUG_DATA                                                   0x1b39
7906  #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA                                          0x1b39
7907  #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA                                          0x1d39
7908  #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA                                          0x1f39
7909  #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA                                          0x4139
7910  #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA                                          0x4339
7911  #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA                                          0x4539
7912  #define mmDPGV0_PIPE_ARBITRATION_CONTROL1                                       0x4730
7913  #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1                             0x4730
7914  #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1                             0x9930
7915  #define mmDPGV1_PIPE_ARBITRATION_CONTROL1                                       0x473d
7916  #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1                             0x473d
7917  #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1                             0x993d
7918  #define mmDPGV0_PIPE_ARBITRATION_CONTROL2                                       0x4731
7919  #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2                             0x4731
7920  #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2                             0x9931
7921  #define mmDPGV1_PIPE_ARBITRATION_CONTROL2                                       0x473e
7922  #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2                             0x473e
7923  #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2                             0x993e
7924  #define mmDPGV0_WATERMARK_MASK_CONTROL                                          0x4732
7925  #define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL                                0x4732
7926  #define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL                                0x9932
7927  #define mmDPGV1_WATERMARK_MASK_CONTROL                                          0x473f
7928  #define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL                                0x473f
7929  #define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL                                0x993f
7930  #define mmDPGV0_PIPE_URGENCY_CONTROL                                            0x4733
7931  #define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL                                  0x4733
7932  #define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL                                  0x9933
7933  #define mmDPGV1_PIPE_URGENCY_CONTROL                                            0x4740
7934  #define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL                                  0x4740
7935  #define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL                                  0x9940
7936  #define mmDPGV0_PIPE_DPM_CONTROL                                                0x4734
7937  #define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL                                      0x4734
7938  #define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL                                      0x9934
7939  #define mmDPGV1_PIPE_DPM_CONTROL                                                0x4741
7940  #define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL                                      0x4741
7941  #define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL                                      0x9941
7942  #define mmDPGV0_PIPE_STUTTER_CONTROL                                            0x4735
7943  #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL                                  0x4735
7944  #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL                                  0x9935
7945  #define mmDPGV1_PIPE_STUTTER_CONTROL                                            0x4742
7946  #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL                                  0x4742
7947  #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL                                  0x9942
7948  #define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                                   0x4736
7949  #define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x4736
7950  #define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x9936
7951  #define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                                   0x4743
7952  #define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x4743
7953  #define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                         0x9943
7954  #define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                                   0x4737
7955  #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                         0x4737
7956  #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                         0x9937
7957  #define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                                   0x4744
7958  #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                         0x4744
7959  #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                         0x9944
7960  #define mmDPGV0_REPEATER_PROGRAM                                                0x4738
7961  #define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM                                      0x4738
7962  #define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM                                      0x9938
7963  #define mmDPGV1_REPEATER_PROGRAM                                                0x4745
7964  #define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM                                      0x4745
7965  #define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM                                      0x9945
7966  #define mmDPGV0_HW_DEBUG_A                                                      0x4739
7967  #define mmDMIFV_PG0_DPGV0_HW_DEBUG_A                                            0x4739
7968  #define mmDMIFV_PG1_DPGV0_HW_DEBUG_A                                            0x9939
7969  #define mmDPGV1_HW_DEBUG_A                                                      0x4746
7970  #define mmDMIFV_PG0_DPGV1_HW_DEBUG_A                                            0x4746
7971  #define mmDMIFV_PG1_DPGV1_HW_DEBUG_A                                            0x9946
7972  #define mmDPGV0_HW_DEBUG_B                                                      0x473a
7973  #define mmDMIFV_PG0_DPGV0_HW_DEBUG_B                                            0x473a
7974  #define mmDMIFV_PG1_DPGV0_HW_DEBUG_B                                            0x993a
7975  #define mmDPGV1_HW_DEBUG_B                                                      0x4747
7976  #define mmDMIFV_PG0_DPGV1_HW_DEBUG_B                                            0x4747
7977  #define mmDMIFV_PG1_DPGV1_HW_DEBUG_B                                            0x9947
7978  #define mmDPGV0_HW_DEBUG_11                                                     0x473b
7979  #define mmDMIFV_PG0_DPGV0_HW_DEBUG_11                                           0x473b
7980  #define mmDMIFV_PG1_DPGV0_HW_DEBUG_11                                           0x993b
7981  #define mmDPGV1_HW_DEBUG_11                                                     0x4748
7982  #define mmDMIFV_PG0_DPGV1_HW_DEBUG_11                                           0x4748
7983  #define mmDMIFV_PG1_DPGV1_HW_DEBUG_11                                           0x9948
7984  #define mmDPGV0_CHK_PRE_PROC_CNTL                                               0x473c
7985  #define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL                                     0x473c
7986  #define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL                                     0x993c
7987  #define mmDPGV1_CHK_PRE_PROC_CNTL                                               0x4749
7988  #define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL                                     0x4749
7989  #define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL                                     0x9949
7990  #define mmDPGV_TEST_DEBUG_INDEX                                                 0x474e
7991  #define mmDMIFV_PG0_DPGV_TEST_DEBUG_INDEX                                       0x474e
7992  #define mmDMIFV_PG1_DPGV_TEST_DEBUG_INDEX                                       0x994e
7993  #define mmDPGV_TEST_DEBUG_DATA                                                  0x474f
7994  #define mmDMIFV_PG0_DPGV_TEST_DEBUG_DATA                                        0x474f
7995  #define mmDMIFV_PG1_DPGV_TEST_DEBUG_DATA                                        0x994f
7996  #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                       0x18
7997  #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                        0x18
7998  #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0xf00
7999  #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                            0xf02
8000  #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                 0xf04
8001  #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT             0x1f04
8002  #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x1f05
8003  #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x1f0a
8004  #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x1f0b
8005  #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x1f0f
8006  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1705
8007  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                0x17ff
8008  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1720
8009  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2              0x1721
8010  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3              0x1722
8011  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4              0x1723
8012  #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1770
8013  #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                   0x1828
8014  #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                            0x1829
8015  #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                 0x182a
8016  #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                   0x182b
8017  #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                         0x182c
8018  #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES               0x182d
8019  #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                     0x182e
8020  #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                       0x182f
8021  #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                          0x1830
8022  #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                0x1831
8023  #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                0x1832
8024  #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION            0x1833
8025  #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                     0x1834
8026  #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                               0x1835
8027  #define mmAZALIA_F0_CODEC_DEBUG                                                 0x1836
8028  #define mmAZALIA_F0_GTC_GROUP_OFFSET0                                           0x1837
8029  #define mmAZALIA_F0_GTC_GROUP_OFFSET1                                           0x1838
8030  #define mmAZALIA_F0_GTC_GROUP_OFFSET2                                           0x1839
8031  #define mmAZALIA_F0_GTC_GROUP_OFFSET3                                           0x183a
8032  #define mmAZALIA_F0_GTC_GROUP_OFFSET4                                           0x183b
8033  #define mmAZALIA_F0_GTC_GROUP_OFFSET5                                           0x183c
8034  #define mmAZALIA_F0_GTC_GROUP_OFFSET6                                           0x183d
8035  #define mmGLOBAL_CAPABILITIES                                                   0x0
8036  #define mmMINOR_VERSION                                                         0x0
8037  #define mmMAJOR_VERSION                                                         0x0
8038  #define mmOUTPUT_PAYLOAD_CAPABILITY                                             0x1
8039  #define mmINPUT_PAYLOAD_CAPABILITY                                              0x1
8040  #define mmGLOBAL_CONTROL                                                        0x2
8041  #define mmWAKE_ENABLE                                                           0x3
8042  #define mmSTATE_CHANGE_STATUS                                                   0x3
8043  #define mmGLOBAL_STATUS                                                         0x4
8044  #define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY                                      0x6
8045  #define mmINPUT_STREAM_PAYLOAD_CAPABILITY                                       0x6
8046  #define mmINTERRUPT_CONTROL                                                     0x8
8047  #define mmINTERRUPT_STATUS                                                      0x9
8048  #define mmWALL_CLOCK_COUNTER                                                    0xc
8049  #define mmSTREAM_SYNCHRONIZATION                                                0xe
8050  #define mmCORB_LOWER_BASE_ADDRESS                                               0x10
8051  #define mmCORB_UPPER_BASE_ADDRESS                                               0x11
8052  #define mmCORB_WRITE_POINTER                                                    0x12
8053  #define mmCORB_READ_POINTER                                                     0x12
8054  #define mmCORB_CONTROL                                                          0x13
8055  #define mmCORB_STATUS                                                           0x13
8056  #define mmCORB_SIZE                                                             0x13
8057  #define mmRIRB_LOWER_BASE_ADDRESS                                               0x14
8058  #define mmRIRB_UPPER_BASE_ADDRESS                                               0x15
8059  #define mmRIRB_WRITE_POINTER                                                    0x16
8060  #define mmRESPONSE_INTERRUPT_COUNT                                              0x16
8061  #define mmRIRB_CONTROL                                                          0x17
8062  #define mmRIRB_STATUS                                                           0x17
8063  #define mmRIRB_SIZE                                                             0x17
8064  #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                    0x18
8065  #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x18
8066  #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x18
8067  #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                    0x19
8068  #define mmIMMEDIATE_COMMAND_STATUS                                              0x1a
8069  #define mmDMA_POSITION_LOWER_BASE_ADDRESS                                       0x1c
8070  #define mmDMA_POSITION_UPPER_BASE_ADDRESS                                       0x1d
8071  #define mmWALL_CLOCK_COUNTER_ALIAS                                              0x80c
8072  #define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                           0x20
8073  #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER              0x21
8074  #define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                         0x22
8075  #define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                             0x23
8076  #define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                    0x24
8077  #define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT                                       0x24
8078  #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS               0x26
8079  #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS               0x27
8080  #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS        0x821
8081  #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                   0x18
8082  #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                    0x18
8083  #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x2f09
8084  #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x2f0a
8085  #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x2f0b
8086  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2200
8087  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x2706
8088  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x270d
8089  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                 0x270e
8090  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                 0x273e
8091  #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                              0x2724
8092  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x2770
8093  #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x2771
8094  #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x3f09
8095  #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                            0x3f0c
8096  #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                  0x3f0e
8097  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY            0x3702
8098  #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x3707
8099  #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x3708
8100  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x3709
8101  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x371c
8102  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2          0x371d
8103  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3          0x371e
8104  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4          0x371f
8105  #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION               0x3770
8106  #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                        0x3771
8107  #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                             0x3772
8108  #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                          0x3776
8109  #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                     0x3776
8110  #define ixAUDIO_DESCRIPTOR0                                                     0x1
8111  #define ixAUDIO_DESCRIPTOR1                                                     0x2
8112  #define ixAUDIO_DESCRIPTOR2                                                     0x3
8113  #define ixAUDIO_DESCRIPTOR3                                                     0x4
8114  #define ixAUDIO_DESCRIPTOR4                                                     0x5
8115  #define ixAUDIO_DESCRIPTOR5                                                     0x6
8116  #define ixAUDIO_DESCRIPTOR6                                                     0x7
8117  #define ixAUDIO_DESCRIPTOR7                                                     0x8
8118  #define ixAUDIO_DESCRIPTOR8                                                     0x9
8119  #define ixAUDIO_DESCRIPTOR9                                                     0xa
8120  #define ixAUDIO_DESCRIPTOR10                                                    0xb
8121  #define ixAUDIO_DESCRIPTOR11                                                    0xc
8122  #define ixAUDIO_DESCRIPTOR12                                                    0xd
8123  #define ixAUDIO_DESCRIPTOR13                                                    0xe
8124  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                     0x3777
8125  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                     0x3778
8126  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                     0x3779
8127  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                     0x377a
8128  #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                   0x377b
8129  #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                       0x377c
8130  #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                     0x3780
8131  #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                      0x3781
8132  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                           0x0
8133  #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                0x1
8134  #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                      0x2
8135  #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                   0x3
8136  #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                   0x4
8137  #define ixSINK_DESCRIPTION0                                                     0x5
8138  #define ixSINK_DESCRIPTION1                                                     0x6
8139  #define ixSINK_DESCRIPTION2                                                     0x7
8140  #define ixSINK_DESCRIPTION3                                                     0x8
8141  #define ixSINK_DESCRIPTION4                                                     0x9
8142  #define ixSINK_DESCRIPTION5                                                     0xa
8143  #define ixSINK_DESCRIPTION6                                                     0xb
8144  #define ixSINK_DESCRIPTION7                                                     0xc
8145  #define ixSINK_DESCRIPTION8                                                     0xd
8146  #define ixSINK_DESCRIPTION9                                                     0xe
8147  #define ixSINK_DESCRIPTION10                                                    0xf
8148  #define ixSINK_DESCRIPTION11                                                    0x10
8149  #define ixSINK_DESCRIPTION12                                                    0x11
8150  #define ixSINK_DESCRIPTION13                                                    0x12
8151  #define ixSINK_DESCRIPTION14                                                    0x13
8152  #define ixSINK_DESCRIPTION15                                                    0x14
8153  #define ixSINK_DESCRIPTION16                                                    0x15
8154  #define ixSINK_DESCRIPTION17                                                    0x16
8155  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                      0x3785
8156  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                      0x3786
8157  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                      0x3787
8158  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                      0x3788
8159  #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x3789
8160  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x378a
8161  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x378b
8162  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x378c
8163  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x378d
8164  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x378e
8165  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x378f
8166  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x3790
8167  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x3791
8168  #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x3792
8169  #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                  0x3793
8170  #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x3797
8171  #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x3798
8172  #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                      0x3799
8173  #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x379a
8174  #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                               0x379b
8175  #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x379c
8176  #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x379d
8177  #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x379e
8178  #define mmAZALIA_CONTROLLER_CLOCK_GATING                                        0x17e4
8179  #define mmAZALIA_AUDIO_DTO                                                      0x17e5
8180  #define mmAZALIA_AUDIO_DTO_CONTROL                                              0x17e6
8181  #define mmAZALIA_SCLK_CONTROL                                                   0x17e7
8182  #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                        0x17e8
8183  #define mmAZALIA_DATA_DMA_CONTROL                                               0x17e9
8184  #define mmAZALIA_BDL_DMA_CONTROL                                                0x17ea
8185  #define mmAZALIA_RIRB_AND_DP_CONTROL                                            0x17eb
8186  #define mmAZALIA_CORB_DMA_CONTROL                                               0x17ec
8187  #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                          0x17f3
8188  #define mmAZALIA_CYCLIC_BUFFER_SYNC                                             0x17f4
8189  #define mmAZALIA_GLOBAL_CAPABILITIES                                            0x17f5
8190  #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                      0x17f6
8191  #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                  0x17f7
8192  #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                       0x17f8
8193  #define mmAZALIA_CONTROLLER_DEBUG                                               0x17f9
8194  #define mmAZALIA_MEM_PWR_CTRL                                                   0x1810
8195  #define mmAZALIA_MEM_PWR_STATUS                                                 0x1811
8196  #define mmDCI_PG_DEBUG_CONFIG                                                   0x1812
8197  #define mmAZALIA_INPUT_CRC0_CONTROL0                                            0x17fb
8198  #define mmAZALIA_INPUT_CRC0_CONTROL1                                            0x17fc
8199  #define mmAZALIA_INPUT_CRC0_CONTROL2                                            0x17fd
8200  #define mmAZALIA_INPUT_CRC0_CONTROL3                                            0x17fe
8201  #define mmAZALIA_INPUT_CRC0_RESULT                                              0x17ff
8202  #define ixAZALIA_INPUT_CRC0_CHANNEL0                                            0x0
8203  #define ixAZALIA_INPUT_CRC0_CHANNEL1                                            0x1
8204  #define ixAZALIA_INPUT_CRC0_CHANNEL2                                            0x2
8205  #define ixAZALIA_INPUT_CRC0_CHANNEL3                                            0x3
8206  #define ixAZALIA_INPUT_CRC0_CHANNEL4                                            0x4
8207  #define ixAZALIA_INPUT_CRC0_CHANNEL5                                            0x5
8208  #define ixAZALIA_INPUT_CRC0_CHANNEL6                                            0x6
8209  #define ixAZALIA_INPUT_CRC0_CHANNEL7                                            0x7
8210  #define mmAZALIA_INPUT_CRC1_CONTROL0                                            0x1800
8211  #define mmAZALIA_INPUT_CRC1_CONTROL1                                            0x1801
8212  #define mmAZALIA_INPUT_CRC1_CONTROL2                                            0x1802
8213  #define mmAZALIA_INPUT_CRC1_CONTROL3                                            0x1803
8214  #define mmAZALIA_INPUT_CRC1_RESULT                                              0x1804
8215  #define ixAZALIA_INPUT_CRC1_CHANNEL0                                            0x0
8216  #define ixAZALIA_INPUT_CRC1_CHANNEL1                                            0x1
8217  #define ixAZALIA_INPUT_CRC1_CHANNEL2                                            0x2
8218  #define ixAZALIA_INPUT_CRC1_CHANNEL3                                            0x3
8219  #define ixAZALIA_INPUT_CRC1_CHANNEL4                                            0x4
8220  #define ixAZALIA_INPUT_CRC1_CHANNEL5                                            0x5
8221  #define ixAZALIA_INPUT_CRC1_CHANNEL6                                            0x6
8222  #define ixAZALIA_INPUT_CRC1_CHANNEL7                                            0x7
8223  #define mmAZALIA_CRC0_CONTROL0                                                  0x1805
8224  #define mmAZALIA_CRC0_CONTROL1                                                  0x1806
8225  #define mmAZALIA_CRC0_CONTROL2                                                  0x1807
8226  #define mmAZALIA_CRC0_CONTROL3                                                  0x1808
8227  #define mmAZALIA_CRC0_RESULT                                                    0x1809
8228  #define ixAZALIA_CRC0_CHANNEL0                                                  0x0
8229  #define ixAZALIA_CRC0_CHANNEL1                                                  0x1
8230  #define ixAZALIA_CRC0_CHANNEL2                                                  0x2
8231  #define ixAZALIA_CRC0_CHANNEL3                                                  0x3
8232  #define ixAZALIA_CRC0_CHANNEL4                                                  0x4
8233  #define ixAZALIA_CRC0_CHANNEL5                                                  0x5
8234  #define ixAZALIA_CRC0_CHANNEL6                                                  0x6
8235  #define ixAZALIA_CRC0_CHANNEL7                                                  0x7
8236  #define mmAZALIA_CRC1_CONTROL0                                                  0x180a
8237  #define mmAZALIA_CRC1_CONTROL1                                                  0x180b
8238  #define mmAZALIA_CRC1_CONTROL2                                                  0x180c
8239  #define mmAZALIA_CRC1_CONTROL3                                                  0x180d
8240  #define mmAZALIA_CRC1_RESULT                                                    0x180e
8241  #define ixAZALIA_CRC1_CHANNEL0                                                  0x0
8242  #define ixAZALIA_CRC1_CHANNEL1                                                  0x1
8243  #define ixAZALIA_CRC1_CHANNEL2                                                  0x2
8244  #define ixAZALIA_CRC1_CHANNEL3                                                  0x3
8245  #define ixAZALIA_CRC1_CHANNEL4                                                  0x4
8246  #define ixAZALIA_CRC1_CHANNEL5                                                  0x5
8247  #define ixAZALIA_CRC1_CHANNEL6                                                  0x6
8248  #define ixAZALIA_CRC1_CHANNEL7                                                  0x7
8249  #define mmAZ_TEST_DEBUG_INDEX                                                   0x181f
8250  #define mmAZ_TEST_DEBUG_DATA                                                    0x1820
8251  #define mmAZALIA_STREAM_INDEX                                                   0x1780
8252  #define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                       0x1780
8253  #define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                       0x1782
8254  #define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                       0x1784
8255  #define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                       0x1786
8256  #define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                       0x1788
8257  #define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                       0x178a
8258  #define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                       0x178c
8259  #define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                       0x178e
8260  #define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                       0x59c0
8261  #define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                       0x59c2
8262  #define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                      0x59c4
8263  #define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                      0x59c6
8264  #define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                      0x59c8
8265  #define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                      0x59ca
8266  #define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                      0x59cc
8267  #define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                      0x59ce
8268  #define mmAZALIA_STREAM_DATA                                                    0x1781
8269  #define mmAZF0STREAM0_AZALIA_STREAM_DATA                                        0x1781
8270  #define mmAZF0STREAM1_AZALIA_STREAM_DATA                                        0x1783
8271  #define mmAZF0STREAM2_AZALIA_STREAM_DATA                                        0x1785
8272  #define mmAZF0STREAM3_AZALIA_STREAM_DATA                                        0x1787
8273  #define mmAZF0STREAM4_AZALIA_STREAM_DATA                                        0x1789
8274  #define mmAZF0STREAM5_AZALIA_STREAM_DATA                                        0x178b
8275  #define mmAZF0STREAM6_AZALIA_STREAM_DATA                                        0x178d
8276  #define mmAZF0STREAM7_AZALIA_STREAM_DATA                                        0x178f
8277  #define mmAZF0STREAM8_AZALIA_STREAM_DATA                                        0x59c1
8278  #define mmAZF0STREAM9_AZALIA_STREAM_DATA                                        0x59c3
8279  #define mmAZF0STREAM10_AZALIA_STREAM_DATA                                       0x59c5
8280  #define mmAZF0STREAM11_AZALIA_STREAM_DATA                                       0x59c7
8281  #define mmAZF0STREAM12_AZALIA_STREAM_DATA                                       0x59c9
8282  #define mmAZF0STREAM13_AZALIA_STREAM_DATA                                       0x59cb
8283  #define mmAZF0STREAM14_AZALIA_STREAM_DATA                                       0x59cd
8284  #define mmAZF0STREAM15_AZALIA_STREAM_DATA                                       0x59cf
8285  #define ixAZALIA_FIFO_SIZE_CONTROL                                              0x0
8286  #define ixAZALIA_LATENCY_COUNTER_CONTROL                                        0x1
8287  #define ixAZALIA_WORSTCASE_LATENCY_COUNT                                        0x2
8288  #define ixAZALIA_CUMULATIVE_LATENCY_COUNT                                       0x3
8289  #define ixAZALIA_CUMULATIVE_REQUEST_COUNT                                       0x4
8290  #define ixAZALIA_STREAM_DEBUG                                                   0x5
8291  #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX                                        0x17a8
8292  #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17a8
8293  #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17ac
8294  #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b0
8295  #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b4
8296  #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17b8
8297  #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17bc
8298  #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c0
8299  #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                          0x17c4
8300  #define mmAZALIA_F0_CODEC_ENDPOINT_DATA                                         0x17a9
8301  #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17a9
8302  #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17ad
8303  #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b1
8304  #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b5
8305  #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17b9
8306  #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17bd
8307  #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c1
8308  #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                           0x17c5
8309  #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG                                   0x0
8310  #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x1
8311  #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                    0x2
8312  #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                   0x3
8313  #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                   0x4
8314  #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                    0x5
8315  #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES              0x6
8316  #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                              0x7
8317  #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                           0x8
8318  #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                       0x9
8319  #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG                    0xa
8320  #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                           0xc
8321  #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                       0xd
8322  #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                       0xe
8323  #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES               0x20
8324  #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                            0x21
8325  #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                      0x22
8326  #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                        0x23
8327  #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                            0x24
8328  #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                           0x25
8329  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                         0x28
8330  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                         0x29
8331  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                         0x2a
8332  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                         0x2b
8333  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                         0x2c
8334  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                         0x2d
8335  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                         0x2e
8336  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                         0x2f
8337  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                         0x30
8338  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                         0x31
8339  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                        0x32
8340  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                        0x33
8341  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                        0x34
8342  #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                        0x35
8343  #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                       0x36
8344  #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                      0x57
8345  #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                         0x58
8346  #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                          0x37
8347  #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                              0x38
8348  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                0x3a
8349  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                0x3b
8350  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                0x3c
8351  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                0x3d
8352  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                0x3e
8353  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                0x3f
8354  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                0x40
8355  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                0x41
8356  #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                0x42
8357  #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                          0x54
8358  #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                0x55
8359  #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT            0x56
8360  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                             0x59
8361  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                             0x5a
8362  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                             0x5b
8363  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                             0x5c
8364  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                             0x5d
8365  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                             0x5e
8366  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                             0x5f
8367  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                             0x60
8368  #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                             0x61
8369  #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                  0x62
8370  #define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                     0x63
8371  #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                     0x64
8372  #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB                                      0x65
8373  #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                       0x66
8374  #define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                               0x67
8375  #define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                            0x68
8376  #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION           0x69
8377  #define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                          0x6a
8378  #define ixAZALIA_F0_AUDIO_ENABLE_STATUS                                         0x6b
8379  #define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS                                    0x6c
8380  #define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS                                   0x6d
8381  #define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                             0x6e
8382  #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                  0x59d4
8383  #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d4
8384  #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59d8
8385  #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59dc
8386  #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e0
8387  #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e4
8388  #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59e8
8389  #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59ec
8390  #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX               0x59f0
8391  #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                   0x59d5
8392  #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d5
8393  #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59d9
8394  #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59dd
8395  #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e1
8396  #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e5
8397  #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59e9
8398  #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59ed
8399  #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                0x59f1
8400  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG                             0x0
8401  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x1
8402  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x2
8403  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x3
8404  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x4
8405  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x5
8406  #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6
8407  #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x20
8408  #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x21
8409  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x22
8410  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE            0x23
8411  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x24
8412  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                 0x36
8413  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                0x37
8414  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                        0x38
8415  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x53
8416  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                    0x54
8417  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE          0x55
8418  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x56
8419  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x67
8420  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x68
8421  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x64
8422  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                0x65
8423  #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x66
8424  #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                    0x18
8425  #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                     0x18
8426  #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES   0x6f09
8427  #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES        0x6f0a
8428  #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS              0x6f0b
8429  #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT              0x6200
8430  #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID             0x6706
8431  #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER             0x670d
8432  #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES         0x7f09
8433  #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                      0x7f0c
8434  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                      0x7707
8435  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                0x7708
8436  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                  0x7709
8437  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT      0x771c
8438  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2    0x771d
8439  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3    0x771e
8440  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4    0x771f
8441  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                0x7777
8442  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                0x7785
8443  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                0x7778
8444  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                0x7786
8445  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                 0x777c
8446  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                0x7779
8447  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                0x7787
8448  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                0x777a
8449  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                0x7788
8450  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                  0x7771
8451  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                0x779b
8452  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                           0x779c
8453  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                    0x779d
8454  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                    0x779e
8455  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL               0x7798
8456  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                0x7799
8457  #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                 0x779a
8458  #define mmBLND_CONTROL                                                          0x1b6d
8459  #define mmBLND0_BLND_CONTROL                                                    0x1b6d
8460  #define mmBLND1_BLND_CONTROL                                                    0x1d6d
8461  #define mmBLND2_BLND_CONTROL                                                    0x1f6d
8462  #define mmBLND3_BLND_CONTROL                                                    0x416d
8463  #define mmBLND4_BLND_CONTROL                                                    0x436d
8464  #define mmBLND5_BLND_CONTROL                                                    0x456d
8465  #define mmBLND_SM_CONTROL2                                                      0x1b6e
8466  #define mmBLND0_BLND_SM_CONTROL2                                                0x1b6e
8467  #define mmBLND1_BLND_SM_CONTROL2                                                0x1d6e
8468  #define mmBLND2_BLND_SM_CONTROL2                                                0x1f6e
8469  #define mmBLND3_BLND_SM_CONTROL2                                                0x416e
8470  #define mmBLND4_BLND_SM_CONTROL2                                                0x436e
8471  #define mmBLND5_BLND_SM_CONTROL2                                                0x456e
8472  #define mmBLND_CONTROL2                                                         0x1b6f
8473  #define mmBLND0_BLND_CONTROL2                                                   0x1b6f
8474  #define mmBLND1_BLND_CONTROL2                                                   0x1d6f
8475  #define mmBLND2_BLND_CONTROL2                                                   0x1f6f
8476  #define mmBLND3_BLND_CONTROL2                                                   0x416f
8477  #define mmBLND4_BLND_CONTROL2                                                   0x436f
8478  #define mmBLND5_BLND_CONTROL2                                                   0x456f
8479  #define mmBLND_UPDATE                                                           0x1b70
8480  #define mmBLND0_BLND_UPDATE                                                     0x1b70
8481  #define mmBLND1_BLND_UPDATE                                                     0x1d70
8482  #define mmBLND2_BLND_UPDATE                                                     0x1f70
8483  #define mmBLND3_BLND_UPDATE                                                     0x4170
8484  #define mmBLND4_BLND_UPDATE                                                     0x4370
8485  #define mmBLND5_BLND_UPDATE                                                     0x4570
8486  #define mmBLND_UNDERFLOW_INTERRUPT                                              0x1b71
8487  #define mmBLND0_BLND_UNDERFLOW_INTERRUPT                                        0x1b71
8488  #define mmBLND1_BLND_UNDERFLOW_INTERRUPT                                        0x1d71
8489  #define mmBLND2_BLND_UNDERFLOW_INTERRUPT                                        0x1f71
8490  #define mmBLND3_BLND_UNDERFLOW_INTERRUPT                                        0x4171
8491  #define mmBLND4_BLND_UNDERFLOW_INTERRUPT                                        0x4371
8492  #define mmBLND5_BLND_UNDERFLOW_INTERRUPT                                        0x4571
8493  #define mmBLND_V_UPDATE_LOCK                                                    0x1b73
8494  #define mmBLND0_BLND_V_UPDATE_LOCK                                              0x1b73
8495  #define mmBLND1_BLND_V_UPDATE_LOCK                                              0x1d73
8496  #define mmBLND2_BLND_V_UPDATE_LOCK                                              0x1f73
8497  #define mmBLND3_BLND_V_UPDATE_LOCK                                              0x4173
8498  #define mmBLND4_BLND_V_UPDATE_LOCK                                              0x4373
8499  #define mmBLND5_BLND_V_UPDATE_LOCK                                              0x4573
8500  #define mmBLND_REG_UPDATE_STATUS                                                0x1b77
8501  #define mmBLND0_BLND_REG_UPDATE_STATUS                                          0x1b77
8502  #define mmBLND1_BLND_REG_UPDATE_STATUS                                          0x1d77
8503  #define mmBLND2_BLND_REG_UPDATE_STATUS                                          0x1f77
8504  #define mmBLND3_BLND_REG_UPDATE_STATUS                                          0x4177
8505  #define mmBLND4_BLND_REG_UPDATE_STATUS                                          0x4377
8506  #define mmBLND5_BLND_REG_UPDATE_STATUS                                          0x4577
8507  #define mmBLND_DEBUG                                                            0x1b74
8508  #define mmBLND0_BLND_DEBUG                                                      0x1b74
8509  #define mmBLND1_BLND_DEBUG                                                      0x1d74
8510  #define mmBLND2_BLND_DEBUG                                                      0x1f74
8511  #define mmBLND3_BLND_DEBUG                                                      0x4174
8512  #define mmBLND4_BLND_DEBUG                                                      0x4374
8513  #define mmBLND5_BLND_DEBUG                                                      0x4574
8514  #define mmBLND_TEST_DEBUG_INDEX                                                 0x1b75
8515  #define mmBLND0_BLND_TEST_DEBUG_INDEX                                           0x1b75
8516  #define mmBLND1_BLND_TEST_DEBUG_INDEX                                           0x1d75
8517  #define mmBLND2_BLND_TEST_DEBUG_INDEX                                           0x1f75
8518  #define mmBLND3_BLND_TEST_DEBUG_INDEX                                           0x4175
8519  #define mmBLND4_BLND_TEST_DEBUG_INDEX                                           0x4375
8520  #define mmBLND5_BLND_TEST_DEBUG_INDEX                                           0x4575
8521  #define mmBLND_TEST_DEBUG_DATA                                                  0x1b76
8522  #define mmBLND0_BLND_TEST_DEBUG_DATA                                            0x1b76
8523  #define mmBLND1_BLND_TEST_DEBUG_DATA                                            0x1d76
8524  #define mmBLND2_BLND_TEST_DEBUG_DATA                                            0x1f76
8525  #define mmBLND3_BLND_TEST_DEBUG_DATA                                            0x4176
8526  #define mmBLND4_BLND_TEST_DEBUG_DATA                                            0x4376
8527  #define mmBLND5_BLND_TEST_DEBUG_DATA                                            0x4576
8528  #define mmWB_ENABLE                                                             0x5e18
8529  #define mmWB_EC_CONFIG                                                          0x5e19
8530  #define mmCNV_MODE                                                              0x5e1a
8531  #define mmCNV_WINDOW_START                                                      0x5e1b
8532  #define mmCNV_WINDOW_SIZE                                                       0x5e1c
8533  #define mmCNV_UPDATE                                                            0x5e1d
8534  #define mmCNV_SOURCE_SIZE                                                       0x5e1e
8535  #define mmCNV_CSC_CONTROL                                                       0x5e1f
8536  #define mmCNV_CSC_C11_C12                                                       0x5e20
8537  #define mmCNV_CSC_C13_C14                                                       0x5e21
8538  #define mmCNV_CSC_C21_C22                                                       0x5e22
8539  #define mmCNV_CSC_C23_C24                                                       0x5e23
8540  #define mmCNV_CSC_C31_C32                                                       0x5e24
8541  #define mmCNV_CSC_C33_C34                                                       0x5e25
8542  #define mmCNV_CSC_ROUND_OFFSET_R                                                0x5e26
8543  #define mmCNV_CSC_ROUND_OFFSET_G                                                0x5e27
8544  #define mmCNV_CSC_ROUND_OFFSET_B                                                0x5e28
8545  #define mmCNV_CSC_CLAMP_R                                                       0x5e29
8546  #define mmCNV_CSC_CLAMP_G                                                       0x5e2a
8547  #define mmCNV_CSC_CLAMP_B                                                       0x5e2b
8548  #define mmCNV_TEST_CNTL                                                         0x5e2c
8549  #define mmCNV_TEST_CRC_RED                                                      0x5e2d
8550  #define mmCNV_TEST_CRC_GREEN                                                    0x5e2e
8551  #define mmCNV_TEST_CRC_BLUE                                                     0x5e2f
8552  #define mmWB_DEBUG_CTRL                                                         0x5e30
8553  #define mmWB_DBG_MODE                                                           0x5e31
8554  #define mmWB_HW_DEBUG                                                           0x5e32
8555  #define mmCNV_INPUT_SELECT                                                      0x5e33
8556  #define mmWB_SOFT_RESET                                                         0x5e36
8557  #define mmWB_WARM_UP_MODE_CTL1                                                  0x5e37
8558  #define mmWB_WARM_UP_MODE_CTL2                                                  0x5e38
8559  #define mmCNV_TEST_DEBUG_INDEX                                                  0x5e34
8560  #define mmCNV_TEST_DEBUG_DATA                                                   0x5e35
8561  #define mmDCFE_CLOCK_CONTROL                                                    0x1b00
8562  #define mmDCFE0_DCFE_CLOCK_CONTROL                                              0x1b00
8563  #define mmDCFE1_DCFE_CLOCK_CONTROL                                              0x1d00
8564  #define mmDCFE2_DCFE_CLOCK_CONTROL                                              0x1f00
8565  #define mmDCFE3_DCFE_CLOCK_CONTROL                                              0x4100
8566  #define mmDCFE4_DCFE_CLOCK_CONTROL                                              0x4300
8567  #define mmDCFE5_DCFE_CLOCK_CONTROL                                              0x4500
8568  #define mmDCFE_SOFT_RESET                                                       0x1b01
8569  #define mmDCFE0_DCFE_SOFT_RESET                                                 0x1b01
8570  #define mmDCFE1_DCFE_SOFT_RESET                                                 0x1d01
8571  #define mmDCFE2_DCFE_SOFT_RESET                                                 0x1f01
8572  #define mmDCFE3_DCFE_SOFT_RESET                                                 0x4101
8573  #define mmDCFE4_DCFE_SOFT_RESET                                                 0x4301
8574  #define mmDCFE5_DCFE_SOFT_RESET                                                 0x4501
8575  #define mmDCFE_DBG_CONFIG                                                       0x1b02
8576  #define mmDCFE0_DCFE_DBG_CONFIG                                                 0x1b02
8577  #define mmDCFE1_DCFE_DBG_CONFIG                                                 0x1d02
8578  #define mmDCFE2_DCFE_DBG_CONFIG                                                 0x1f02
8579  #define mmDCFE3_DCFE_DBG_CONFIG                                                 0x4102
8580  #define mmDCFE4_DCFE_DBG_CONFIG                                                 0x4302
8581  #define mmDCFE5_DCFE_DBG_CONFIG                                                 0x4502
8582  #define mmDCFE_MEM_PWR_CTRL                                                     0x1b03
8583  #define mmDCFE0_DCFE_MEM_PWR_CTRL                                               0x1b03
8584  #define mmDCFE1_DCFE_MEM_PWR_CTRL                                               0x1d03
8585  #define mmDCFE2_DCFE_MEM_PWR_CTRL                                               0x1f03
8586  #define mmDCFE3_DCFE_MEM_PWR_CTRL                                               0x4103
8587  #define mmDCFE4_DCFE_MEM_PWR_CTRL                                               0x4303
8588  #define mmDCFE5_DCFE_MEM_PWR_CTRL                                               0x4503
8589  #define mmDCFE_MEM_PWR_CTRL2                                                    0x1b04
8590  #define mmDCFE0_DCFE_MEM_PWR_CTRL2                                              0x1b04
8591  #define mmDCFE1_DCFE_MEM_PWR_CTRL2                                              0x1d04
8592  #define mmDCFE2_DCFE_MEM_PWR_CTRL2                                              0x1f04
8593  #define mmDCFE3_DCFE_MEM_PWR_CTRL2                                              0x4104
8594  #define mmDCFE4_DCFE_MEM_PWR_CTRL2                                              0x4304
8595  #define mmDCFE5_DCFE_MEM_PWR_CTRL2                                              0x4504
8596  #define mmDCFE_MEM_PWR_STATUS                                                   0x1b05
8597  #define mmDCFE0_DCFE_MEM_PWR_STATUS                                             0x1b05
8598  #define mmDCFE1_DCFE_MEM_PWR_STATUS                                             0x1d05
8599  #define mmDCFE2_DCFE_MEM_PWR_STATUS                                             0x1f05
8600  #define mmDCFE3_DCFE_MEM_PWR_STATUS                                             0x4105
8601  #define mmDCFE4_DCFE_MEM_PWR_STATUS                                             0x4305
8602  #define mmDCFE5_DCFE_MEM_PWR_STATUS                                             0x4505
8603  #define mmDCFE_MISC                                                             0x1b06
8604  #define mmDCFE0_DCFE_MISC                                                       0x1b06
8605  #define mmDCFE1_DCFE_MISC                                                       0x1d06
8606  #define mmDCFE2_DCFE_MISC                                                       0x1f06
8607  #define mmDCFE3_DCFE_MISC                                                       0x4106
8608  #define mmDCFE4_DCFE_MISC                                                       0x4306
8609  #define mmDCFE5_DCFE_MISC                                                       0x4506
8610  #define mmDCFE_FLUSH                                                            0x1b07
8611  #define mmDCFE0_DCFE_FLUSH                                                      0x1b07
8612  #define mmDCFE1_DCFE_FLUSH                                                      0x1d07
8613  #define mmDCFE2_DCFE_FLUSH                                                      0x1f07
8614  #define mmDCFE3_DCFE_FLUSH                                                      0x4107
8615  #define mmDCFE4_DCFE_FLUSH                                                      0x4307
8616  #define mmDCFE5_DCFE_FLUSH                                                      0x4507
8617  #define mmDCFEV_CLOCK_CONTROL                                                   0x46f4
8618  #define mmDCFEV0_DCFEV_CLOCK_CONTROL                                            0x46f4
8619  #define mmDCFEV1_DCFEV_CLOCK_CONTROL                                            0x98f4
8620  #define mmDCFEV_SOFT_RESET                                                      0x46f5
8621  #define mmDCFEV0_DCFEV_SOFT_RESET                                               0x46f5
8622  #define mmDCFEV1_DCFEV_SOFT_RESET                                               0x98f5
8623  #define mmDCFEV_DMIFV_CLOCK_CONTROL                                             0x46f6
8624  #define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL                                      0x46f6
8625  #define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL                                      0x98f6
8626  #define mmDCFEV_DBG_CONFIG                                                      0x46f7
8627  #define mmDCFEV0_DCFEV_DBG_CONFIG                                               0x46f7
8628  #define mmDCFEV1_DCFEV_DBG_CONFIG                                               0x98f7
8629  #define mmDCFEV_DMIFV_MEM_PWR_CTRL                                              0x46f8
8630  #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL                                       0x46f8
8631  #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL                                       0x98f8
8632  #define mmDCFEV_DMIFV_MEM_PWR_STATUS                                            0x46f9
8633  #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS                                     0x46f9
8634  #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS                                     0x98f9
8635  #define mmDCFEV_MEM_PWR_CTRL                                                    0x46fa
8636  #define mmDCFEV0_DCFEV_MEM_PWR_CTRL                                             0x46fa
8637  #define mmDCFEV1_DCFEV_MEM_PWR_CTRL                                             0x98fa
8638  #define mmDCFEV_MEM_PWR_CTRL2                                                   0x46fb
8639  #define mmDCFEV0_DCFEV_MEM_PWR_CTRL2                                            0x46fb
8640  #define mmDCFEV1_DCFEV_MEM_PWR_CTRL2                                            0x98fb
8641  #define mmDCFEV_MEM_PWR_STATUS                                                  0x46fc
8642  #define mmDCFEV0_DCFEV_MEM_PWR_STATUS                                           0x46fc
8643  #define mmDCFEV1_DCFEV_MEM_PWR_STATUS                                           0x98fc
8644  #define mmDCFEV_L_FLUSH                                                         0x46ff
8645  #define mmDCFEV0_DCFEV_L_FLUSH                                                  0x46ff
8646  #define mmDCFEV1_DCFEV_L_FLUSH                                                  0x98ff
8647  #define mmDCFEV_C_FLUSH                                                         0x4700
8648  #define mmDCFEV0_DCFEV_C_FLUSH                                                  0x4700
8649  #define mmDCFEV1_DCFEV_C_FLUSH                                                  0x9900
8650  #define mmDCFEV_DMIFV_DEBUG                                                     0x46fd
8651  #define mmDCFEV0_DCFEV_DMIFV_DEBUG                                              0x46fd
8652  #define mmDCFEV1_DCFEV_DMIFV_DEBUG                                              0x98fd
8653  #define mmDCFEV_MISC                                                            0x46fe
8654  #define mmDCFEV0_DCFEV_MISC                                                     0x46fe
8655  #define mmDCFEV1_DCFEV_MISC                                                     0x98fe
8656  #define mmDC_HPD_INT_STATUS                                                     0x1898
8657  #define mmHPD0_DC_HPD_INT_STATUS                                                0x1898
8658  #define mmHPD1_DC_HPD_INT_STATUS                                                0x18a0
8659  #define mmHPD2_DC_HPD_INT_STATUS                                                0x18a8
8660  #define mmHPD3_DC_HPD_INT_STATUS                                                0x18b0
8661  #define mmHPD4_DC_HPD_INT_STATUS                                                0x18b8
8662  #define mmHPD5_DC_HPD_INT_STATUS                                                0x18c0
8663  #define mmDC_HPD_INT_CONTROL                                                    0x1899
8664  #define mmHPD0_DC_HPD_INT_CONTROL                                               0x1899
8665  #define mmHPD1_DC_HPD_INT_CONTROL                                               0x18a1
8666  #define mmHPD2_DC_HPD_INT_CONTROL                                               0x18a9
8667  #define mmHPD3_DC_HPD_INT_CONTROL                                               0x18b1
8668  #define mmHPD4_DC_HPD_INT_CONTROL                                               0x18b9
8669  #define mmHPD5_DC_HPD_INT_CONTROL                                               0x18c1
8670  #define mmDC_HPD_CONTROL                                                        0x189a
8671  #define mmHPD0_DC_HPD_CONTROL                                                   0x189a
8672  #define mmHPD1_DC_HPD_CONTROL                                                   0x18a2
8673  #define mmHPD2_DC_HPD_CONTROL                                                   0x18aa
8674  #define mmHPD3_DC_HPD_CONTROL                                                   0x18b2
8675  #define mmHPD4_DC_HPD_CONTROL                                                   0x18ba
8676  #define mmHPD5_DC_HPD_CONTROL                                                   0x18c2
8677  #define mmDC_HPD_FAST_TRAIN_CNTL                                                0x189b
8678  #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                           0x189b
8679  #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                           0x18a3
8680  #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                           0x18ab
8681  #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                           0x18b3
8682  #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                           0x18bb
8683  #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL                                           0x18c3
8684  #define mmDC_HPD_TOGGLE_FILT_CNTL                                               0x189c
8685  #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                          0x189c
8686  #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                          0x18a4
8687  #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                          0x18ac
8688  #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                          0x18b4
8689  #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                          0x18bc
8690  #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL                                          0x18c4
8691  #define mmDCO_SCRATCH0                                                          0x184e
8692  #define mmDCO_SCRATCH1                                                          0x184f
8693  #define mmDCO_SCRATCH2                                                          0x1850
8694  #define mmDCO_SCRATCH3                                                          0x1851
8695  #define mmDCO_SCRATCH4                                                          0x1852
8696  #define mmDCO_SCRATCH5                                                          0x1853
8697  #define mmDCO_SCRATCH6                                                          0x1854
8698  #define mmDCO_SCRATCH7                                                          0x1855
8699  #define mmDCE_VCE_CONTROL                                                       0x1856
8700  #define mmDISP_INTERRUPT_STATUS                                                 0x1857
8701  #define mmDISP_INTERRUPT_STATUS_CONTINUE                                        0x1858
8702  #define mmDISP_INTERRUPT_STATUS_CONTINUE2                                       0x1859
8703  #define mmDISP_INTERRUPT_STATUS_CONTINUE3                                       0x185a
8704  #define mmDISP_INTERRUPT_STATUS_CONTINUE4                                       0x185b
8705  #define mmDISP_INTERRUPT_STATUS_CONTINUE5                                       0x185c
8706  #define mmDISP_INTERRUPT_STATUS_CONTINUE6                                       0x185d
8707  #define mmDISP_INTERRUPT_STATUS_CONTINUE7                                       0x185e
8708  #define mmDISP_INTERRUPT_STATUS_CONTINUE8                                       0x185f
8709  #define mmDISP_INTERRUPT_STATUS_CONTINUE9                                       0x1860
8710  #define mmDISP_INTERRUPT_STATUS_CONTINUE10                                      0x1875
8711  #define mmDCO_MEM_PWR_STATUS                                                    0x1861
8712  #define mmDCO_MEM_PWR_STATUS1                                                   0x1874
8713  #define mmDCO_MEM_PWR_CTRL                                                      0x1862
8714  #define mmDCO_MEM_PWR_CTRL2                                                     0x1863
8715  #define mmFMT_MEMORY0_CONTROL                                                   0x1888
8716  #define mmFMT_MEMORY1_CONTROL                                                   0x1889
8717  #define mmFMT_MEMORY2_CONTROL                                                   0x188a
8718  #define mmFMT_MEMORY3_CONTROL                                                   0x188b
8719  #define mmFMT_MEMORY4_CONTROL                                                   0x188c
8720  #define mmFMT_MEMORY5_CONTROL                                                   0x188d
8721  #define mmDCO_CLK_CNTL                                                          0x1864
8722  #define mmDCO_CLK_CNTL2                                                         0x1876
8723  #define mmDCO_CLK_CNTL3                                                         0x1877
8724  #define mmDPDBG_CNTL                                                            0x1866
8725  #define mmDPDBG_INTERRUPT                                                       0x1867
8726  #define mmDCO_POWER_MANAGEMENT_CNTL                                             0x1868
8727  #define mmDCO_SOFT_RESET                                                        0x1871
8728  #define mmDIG_SOFT_RESET                                                        0x1872
8729  #define mmDIG_SOFT_RESET_2                                                      0x186a
8730  #define mmDCO_STEREOSYNC_SEL                                                    0x186e
8731  #define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL                                       0x1883
8732  #define mmDCO_PSP_INTERRUPT_STATUS                                              0x1884
8733  #define mmDCO_PSP_INTERRUPT_CLEAR                                               0x1885
8734  #define mmDCO_GENERIC_INTERRUPT_MESSAGE                                         0x1886
8735  #define mmDCO_GENERIC_INTERRUPT_CLEAR                                           0x1887
8736  #define mmDCO_TEST_DEBUG_INDEX                                                  0x186f
8737  #define mmDCO_TEST_DEBUG_DATA                                                   0x1870
8738  #define mmDC_I2C_CONTROL                                                        0x16d4
8739  #define mmDC_I2C_ARBITRATION                                                    0x16d5
8740  #define mmDC_I2C_INTERRUPT_CONTROL                                              0x16d6
8741  #define mmDC_I2C_SW_STATUS                                                      0x16d7
8742  #define mmDC_I2C_DDC1_HW_STATUS                                                 0x16d8
8743  #define mmDC_I2C_DDC2_HW_STATUS                                                 0x16d9
8744  #define mmDC_I2C_DDC3_HW_STATUS                                                 0x16da
8745  #define mmDC_I2C_DDC4_HW_STATUS                                                 0x16db
8746  #define mmDC_I2C_DDC5_HW_STATUS                                                 0x16dc
8747  #define mmDC_I2C_DDC6_HW_STATUS                                                 0x16dd
8748  #define mmDC_I2C_DDC1_SPEED                                                     0x16de
8749  #define mmDC_I2C_DDC1_SETUP                                                     0x16df
8750  #define mmDC_I2C_DDC2_SPEED                                                     0x16e0
8751  #define mmDC_I2C_DDC2_SETUP                                                     0x16e1
8752  #define mmDC_I2C_DDC3_SPEED                                                     0x16e2
8753  #define mmDC_I2C_DDC3_SETUP                                                     0x16e3
8754  #define mmDC_I2C_DDC4_SPEED                                                     0x16e4
8755  #define mmDC_I2C_DDC4_SETUP                                                     0x16e5
8756  #define mmDC_I2C_DDC5_SPEED                                                     0x16e6
8757  #define mmDC_I2C_DDC5_SETUP                                                     0x16e7
8758  #define mmDC_I2C_DDC6_SPEED                                                     0x16e8
8759  #define mmDC_I2C_DDC6_SETUP                                                     0x16e9
8760  #define mmDC_I2C_TRANSACTION0                                                   0x16ea
8761  #define mmDC_I2C_TRANSACTION1                                                   0x16eb
8762  #define mmDC_I2C_TRANSACTION2                                                   0x16ec
8763  #define mmDC_I2C_TRANSACTION3                                                   0x16ed
8764  #define mmDC_I2C_DATA                                                           0x16ee
8765  #define mmDC_I2C_DDCVGA_HW_STATUS                                               0x16ef
8766  #define mmDC_I2C_DDCVGA_SPEED                                                   0x16f0
8767  #define mmDC_I2C_DDCVGA_SETUP                                                   0x16f1
8768  #define mmDC_I2C_EDID_DETECT_CTRL                                               0x16f2
8769  #define mmDC_I2C_READ_REQUEST_INTERRUPT                                         0x16f3
8770  #define mmGENERIC_I2C_CONTROL                                                   0x16f4
8771  #define mmGENERIC_I2C_INTERRUPT_CONTROL                                         0x16f5
8772  #define mmGENERIC_I2C_STATUS                                                    0x16f6
8773  #define mmGENERIC_I2C_SPEED                                                     0x16f7
8774  #define mmGENERIC_I2C_SETUP                                                     0x16f8
8775  #define mmGENERIC_I2C_TRANSACTION                                               0x16f9
8776  #define mmGENERIC_I2C_DATA                                                      0x16fa
8777  #define mmGENERIC_I2C_PIN_SELECTION                                             0x16fb
8778  #define mmGENERIC_I2C_PIN_DEBUG                                                 0x16fc
8779  #define mmBLNDV_CONTROL                                                         0x476d
8780  #define mmBLNDV0_BLNDV_CONTROL                                                  0x476d
8781  #define mmBLNDV1_BLNDV_CONTROL                                                  0x996d
8782  #define mmBLNDV_SM_CONTROL2                                                     0x476e
8783  #define mmBLNDV0_BLNDV_SM_CONTROL2                                              0x476e
8784  #define mmBLNDV1_BLNDV_SM_CONTROL2                                              0x996e
8785  #define mmBLNDV_CONTROL2                                                        0x476f
8786  #define mmBLNDV0_BLNDV_CONTROL2                                                 0x476f
8787  #define mmBLNDV1_BLNDV_CONTROL2                                                 0x996f
8788  #define mmBLNDV_UPDATE                                                          0x4770
8789  #define mmBLNDV0_BLNDV_UPDATE                                                   0x4770
8790  #define mmBLNDV1_BLNDV_UPDATE                                                   0x9970
8791  #define mmBLNDV_UNDERFLOW_INTERRUPT                                             0x4771
8792  #define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT                                      0x4771
8793  #define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT                                      0x9971
8794  #define mmBLNDV_V_UPDATE_LOCK                                                   0x4773
8795  #define mmBLNDV0_BLNDV_V_UPDATE_LOCK                                            0x4773
8796  #define mmBLNDV1_BLNDV_V_UPDATE_LOCK                                            0x9973
8797  #define mmBLNDV_REG_UPDATE_STATUS                                               0x4777
8798  #define mmBLNDV0_BLNDV_REG_UPDATE_STATUS                                        0x4777
8799  #define mmBLNDV1_BLNDV_REG_UPDATE_STATUS                                        0x9977
8800  #define mmBLNDV_DEBUG                                                           0x4774
8801  #define mmBLNDV0_BLNDV_DEBUG                                                    0x4774
8802  #define mmBLNDV1_BLNDV_DEBUG                                                    0x9974
8803  #define mmBLNDV_TEST_DEBUG_INDEX                                                0x4775
8804  #define mmBLNDV0_BLNDV_TEST_DEBUG_INDEX                                         0x4775
8805  #define mmBLNDV1_BLNDV_TEST_DEBUG_INDEX                                         0x9975
8806  #define mmBLNDV_TEST_DEBUG_DATA                                                 0x4776
8807  #define mmBLNDV0_BLNDV_TEST_DEBUG_DATA                                          0x4776
8808  #define mmBLNDV1_BLNDV_TEST_DEBUG_DATA                                          0x9976
8809  #define mmCRTCV_H_TOTAL                                                         0x4780
8810  #define mmCRTCV0_CRTCV_H_TOTAL                                                  0x4780
8811  #define mmCRTCV1_CRTCV_H_TOTAL                                                  0x9980
8812  #define mmCRTCV_H_BLANK_START_END                                               0x4781
8813  #define mmCRTCV0_CRTCV_H_BLANK_START_END                                        0x4781
8814  #define mmCRTCV1_CRTCV_H_BLANK_START_END                                        0x9981
8815  #define mmCRTCV_H_SYNC_A                                                        0x4782
8816  #define mmCRTCV0_CRTCV_H_SYNC_A                                                 0x4782
8817  #define mmCRTCV1_CRTCV_H_SYNC_A                                                 0x9982
8818  #define mmCRTCV_V_TOTAL                                                         0x4787
8819  #define mmCRTCV0_CRTCV_V_TOTAL                                                  0x4787
8820  #define mmCRTCV1_CRTCV_V_TOTAL                                                  0x9987
8821  #define mmCRTCV_V_BLANK_START_END                                               0x478d
8822  #define mmCRTCV0_CRTCV_V_BLANK_START_END                                        0x478d
8823  #define mmCRTCV1_CRTCV_V_BLANK_START_END                                        0x998d
8824  #define mmCRTCV_V_SYNC_A                                                        0x478e
8825  #define mmCRTCV0_CRTCV_V_SYNC_A                                                 0x478e
8826  #define mmCRTCV1_CRTCV_V_SYNC_A                                                 0x998e
8827  #define mmCRTCV_CONTROL                                                         0x479c
8828  #define mmCRTCV0_CRTCV_CONTROL                                                  0x479c
8829  #define mmCRTCV1_CRTCV_CONTROL                                                  0x999c
8830  #define mmCRTCV_START_LINE_CONTROL                                              0x47b3
8831  #define mmCRTCV0_CRTCV_START_LINE_CONTROL                                       0x47b3
8832  #define mmCRTCV1_CRTCV_START_LINE_CONTROL                                       0x99b3
8833  #define mmCRTCV_OVERSCAN_COLOR                                                  0x47c8
8834  #define mmCRTCV0_CRTCV_OVERSCAN_COLOR                                           0x47c8
8835  #define mmCRTCV1_CRTCV_OVERSCAN_COLOR                                           0x99c8
8836  #define mmCRTCV_OVERSCAN_COLOR_EXT                                              0x47c9
8837  #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT                                       0x47c9
8838  #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT                                       0x99c9
8839  #define mmCRTCV_BLACK_COLOR                                                     0x47cc
8840  #define mmCRTCV0_CRTCV_BLACK_COLOR                                              0x47cc
8841  #define mmCRTCV1_CRTCV_BLACK_COLOR                                              0x99cc
8842  #define mmCRTCV_BLACK_COLOR_EXT                                                 0x47cd
8843  #define mmCRTCV0_CRTCV_BLACK_COLOR_EXT                                          0x47cd
8844  #define mmCRTCV1_CRTCV_BLACK_COLOR_EXT                                          0x99cd
8845  #define mmCRTCV_CRC_CNTL                                                        0x47d4
8846  #define mmCRTCV0_CRTCV_CRC_CNTL                                                 0x47d4
8847  #define mmCRTCV1_CRTCV_CRC_CNTL                                                 0x99d4
8848  #define mmCRTCV_CRC0_WINDOWA_X_CONTROL                                          0x47d5
8849  #define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL                                   0x47d5
8850  #define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL                                   0x99d5
8851  #define mmCRTCV_CRC0_WINDOWA_Y_CONTROL                                          0x47d6
8852  #define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL                                   0x47d6
8853  #define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL                                   0x99d6
8854  #define mmCRTCV_CRC0_WINDOWB_X_CONTROL                                          0x47d7
8855  #define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL                                   0x47d7
8856  #define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL                                   0x99d7
8857  #define mmCRTCV_CRC0_WINDOWB_Y_CONTROL                                          0x47d8
8858  #define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL                                   0x47d8
8859  #define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL                                   0x99d8
8860  #define mmCRTCV_CRC0_DATA_RG                                                    0x47d9
8861  #define mmCRTCV0_CRTCV_CRC0_DATA_RG                                             0x47d9
8862  #define mmCRTCV1_CRTCV_CRC0_DATA_RG                                             0x99d9
8863  #define mmCRTCV_CRC0_DATA_B                                                     0x47da
8864  #define mmCRTCV0_CRTCV_CRC0_DATA_B                                              0x47da
8865  #define mmCRTCV1_CRTCV_CRC0_DATA_B                                              0x99da
8866  #define mmCRTCV_CRC1_WINDOWA_X_CONTROL                                          0x47db
8867  #define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL                                   0x47db
8868  #define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL                                   0x99db
8869  #define mmCRTCV_CRC1_WINDOWA_Y_CONTROL                                          0x47dc
8870  #define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL                                   0x47dc
8871  #define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL                                   0x99dc
8872  #define mmCRTCV_CRC1_WINDOWB_X_CONTROL                                          0x47dd
8873  #define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL                                   0x47dd
8874  #define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL                                   0x99dd
8875  #define mmCRTCV_CRC1_WINDOWB_Y_CONTROL                                          0x47de
8876  #define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL                                   0x47de
8877  #define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL                                   0x99de
8878  #define mmCRTCV_CRC1_DATA_RG                                                    0x47df
8879  #define mmCRTCV0_CRTCV_CRC1_DATA_RG                                             0x47df
8880  #define mmCRTCV1_CRTCV_CRC1_DATA_RG                                             0x99df
8881  #define mmCRTCV_CRC1_DATA_B                                                     0x47e0
8882  #define mmCRTCV0_CRTCV_CRC1_DATA_B                                              0x47e0
8883  #define mmCRTCV1_CRTCV_CRC1_DATA_B                                              0x99e0
8884  #define mmCRTCV_TEST_DEBUG_INDEX                                                0x47c6
8885  #define mmCRTCV0_CRTCV_TEST_DEBUG_INDEX                                         0x47c6
8886  #define mmCRTCV1_CRTCV_TEST_DEBUG_INDEX                                         0x99c6
8887  #define mmCRTCV_TEST_DEBUG_DATA                                                 0x47c7
8888  #define mmCRTCV0_CRTCV_TEST_DEBUG_DATA                                          0x47c7
8889  #define mmCRTCV1_CRTCV_TEST_DEBUG_DATA                                          0x99c7
8890  #define mmXDMA_MC_PCIE_CLIENT_CONFIG                                            0x3e0
8891  #define mmXDMA_LOCAL_SURFACE_TILING1                                            0x3e1
8892  #define mmXDMA_LOCAL_SURFACE_TILING2                                            0x3e2
8893  #define mmXDMA_INTERRUPT                                                        0x3e3
8894  #define mmXDMA_CLOCK_GATING_CNTL                                                0x3e4
8895  #define mmXDMA_MEM_POWER_CNTL                                                   0x3e6
8896  #define mmXDMA_IF_BIF_STATUS                                                    0x3e7
8897  #define mmXDMA_PERF_MEAS_STATUS                                                 0x3e8
8898  #define mmXDMA_IF_STATUS                                                        0x3e9
8899  #define mmXDMA_TEST_DEBUG_INDEX                                                 0x3ea
8900  #define mmXDMA_TEST_DEBUG_DATA                                                  0x3eb
8901  #define mmXDMA_RBBMIF_RDWR_CNTL                                                 0x3f8
8902  #define mmXDMA_PG_CONTROL                                                       0x3f9
8903  #define mmXDMA_PG_WDATA                                                         0x3fa
8904  #define mmXDMA_PG_STATUS                                                        0x3fb
8905  #define mmXDMA_AON_TEST_DEBUG_INDEX                                             0x3fc
8906  #define mmXDMA_AON_TEST_DEBUG_DATA                                              0x3fd
8907  #define mmXDMA_MSTR_CNTL                                                        0x3ec
8908  #define mmXDMA_MSTR_STATUS                                                      0x3ed
8909  #define mmXDMA_MSTR_MEM_CLIENT_CONFIG                                           0x3ee
8910  #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR                                     0x3ef
8911  #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH                                0x3f0
8912  #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH                                         0x3f1
8913  #define mmXDMA_MSTR_CMD_URGENT_CNTL                                             0x3f2
8914  #define mmXDMA_MSTR_MEM_URGENT_CNTL                                             0x3f3
8915  #define mmXDMA_MSTR_PCIE_NACK_STATUS                                            0x3f5
8916  #define mmXDMA_MSTR_MEM_NACK_STATUS                                             0x3f6
8917  #define mmXDMA_MSTR_VSYNC_GSL_CHECK                                             0x3f7
8918  #define mmXDMA_MSTR_PIPE_CNTL                                                   0x400
8919  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL                                   0x400
8920  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL                                   0x410
8921  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL                                   0x420
8922  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL                                   0x430
8923  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL                                   0x440
8924  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL                                   0x450
8925  #define mmXDMA_MSTR_READ_COMMAND                                                0x401
8926  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND                                0x401
8927  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND                                0x411
8928  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND                                0x421
8929  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND                                0x431
8930  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND                                0x441
8931  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND                                0x451
8932  #define mmXDMA_MSTR_CHANNEL_DIM                                                 0x402
8933  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM                                 0x402
8934  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM                                 0x412
8935  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM                                 0x422
8936  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM                                 0x432
8937  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM                                 0x442
8938  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM                                 0x452
8939  #define mmXDMA_MSTR_HEIGHT                                                      0x403
8940  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT                                      0x403
8941  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT                                      0x413
8942  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT                                      0x423
8943  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT                                      0x433
8944  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT                                      0x443
8945  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT                                      0x453
8946  #define mmXDMA_MSTR_REMOTE_SURFACE_BASE                                         0x404
8947  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x404
8948  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x414
8949  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x424
8950  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x434
8951  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x444
8952  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE                         0x454
8953  #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                                    0x405
8954  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x405
8955  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x415
8956  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x425
8957  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x435
8958  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x445
8959  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH                    0x455
8960  #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS                                          0x406
8961  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x406
8962  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x416
8963  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x426
8964  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x436
8965  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x446
8966  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS                          0x456
8967  #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                                     0x407
8968  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x407
8969  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x417
8970  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x427
8971  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x437
8972  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x447
8973  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH                     0x457
8974  #define mmXDMA_MSTR_CACHE_BASE_ADDR                                             0x408
8975  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR                             0x408
8976  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR                             0x418
8977  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR                             0x428
8978  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR                             0x438
8979  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR                             0x448
8980  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR                             0x458
8981  #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH                                        0x409
8982  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x409
8983  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x419
8984  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x429
8985  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x439
8986  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x449
8987  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH                        0x459
8988  #define mmXDMA_MSTR_CACHE                                                       0x40a
8989  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE                                       0x40a
8990  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE                                       0x41a
8991  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE                                       0x42a
8992  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE                                       0x43a
8993  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE                                       0x44a
8994  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE                                       0x45a
8995  #define mmXDMA_MSTR_CHANNEL_START                                               0x40b
8996  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START                               0x40b
8997  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START                               0x41b
8998  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START                               0x42b
8999  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START                               0x43b
9000  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START                               0x44b
9001  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START                               0x45b
9002  #define mmXDMA_MSTR_PERFMEAS_STATUS                                             0x40e
9003  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS                             0x40e
9004  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS                             0x41e
9005  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS                             0x42e
9006  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS                             0x43e
9007  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS                             0x44e
9008  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS                             0x45e
9009  #define mmXDMA_MSTR_PERFMEAS_CNTL                                               0x40f
9010  #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL                               0x40f
9011  #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL                               0x41f
9012  #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL                               0x42f
9013  #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL                               0x43f
9014  #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL                               0x44f
9015  #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL                               0x45f
9016  #define mmXDMA_SLV_CNTL                                                         0x460
9017  #define mmXDMA_SLV_MEM_CLIENT_CONFIG                                            0x461
9018  #define mmXDMA_SLV_SLS_PITCH                                                    0x462
9019  #define mmXDMA_SLV_READ_URGENT_CNTL                                             0x463
9020  #define mmXDMA_SLV_WRITE_URGENT_CNTL                                            0x464
9021  #define mmXDMA_SLV_WB_RATE_CNTL                                                 0x465
9022  #define mmXDMA_SLV_READ_LATENCY_MINMAX                                          0x466
9023  #define mmXDMA_SLV_READ_LATENCY_AVE                                             0x467
9024  #define mmXDMA_SLV_PCIE_NACK_STATUS                                             0x468
9025  #define mmXDMA_SLV_MEM_NACK_STATUS                                              0x469
9026  #define mmXDMA_SLV_RDRET_BUF_STATUS                                             0x46a
9027  #define mmXDMA_SLV_READ_LATENCY_TIMER                                           0x46b
9028  #define mmXDMA_SLV_FLIP_PENDING                                                 0x46c
9029  #define mmXDMA_SLV_CHANNEL_CNTL                                                 0x470
9030  #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL                               0x470
9031  #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL                               0x478
9032  #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL                               0x480
9033  #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL                               0x488
9034  #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL                               0x490
9035  #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL                               0x498
9036  #define mmXDMA_SLV_REMOTE_GPU_ADDRESS                                           0x471
9037  #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x471
9038  #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x479
9039  #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x481
9040  #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x489
9041  #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x491
9042  #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS                         0x499
9043  #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                                      0x472
9044  #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x472
9045  #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x47a
9046  #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x482
9047  #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x48a
9048  #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x492
9049  #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH                    0x49a
9050  #define mmCMD_BUS_TX_CONTROL_LANE0                                              0x48e0
9051  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0                           0x48e0
9052  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0                           0x4980
9053  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0                           0x9a20
9054  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0                           0x9ac0
9055  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0                           0x9b60
9056  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0                           0x9c00
9057  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0                           0x9ca0
9058  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE0                           0x9d40
9059  #define mmCMD_BUS_TX_CONTROL_LANE1                                              0x48f0
9060  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1                           0x48f0
9061  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1                           0x4990
9062  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1                           0x9a30
9063  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1                           0x9ad0
9064  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1                           0x9b70
9065  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1                           0x9c10
9066  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1                           0x9cb0
9067  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE1                           0x9d50
9068  #define mmCMD_BUS_TX_CONTROL_LANE2                                              0x4900
9069  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2                           0x4900
9070  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2                           0x49a0
9071  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2                           0x9a40
9072  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2                           0x9ae0
9073  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2                           0x9b80
9074  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2                           0x9c20
9075  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2                           0x9cc0
9076  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE2                           0x9d60
9077  #define mmCMD_BUS_TX_CONTROL_LANE3                                              0x4910
9078  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3                           0x4910
9079  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3                           0x49b0
9080  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3                           0x9a50
9081  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3                           0x9af0
9082  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3                           0x9b90
9083  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3                           0x9c30
9084  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3                           0x9cd0
9085  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE3                           0x9d70
9086  #define mmMARGIN_DEEMPH_LANE0                                                   0x48e1
9087  #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0                                0x48e1
9088  #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0                                0x4981
9089  #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0                                0x9a21
9090  #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0                                0x9ac1
9091  #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0                                0x9b61
9092  #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0                                0x9c01
9093  #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0                                0x9ca1
9094  #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE0                                0x9d41
9095  #define mmMARGIN_DEEMPH_LANE1                                                   0x48f1
9096  #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1                                0x48f1
9097  #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1                                0x4991
9098  #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1                                0x9a31
9099  #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1                                0x9ad1
9100  #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1                                0x9b71
9101  #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1                                0x9c11
9102  #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1                                0x9cb1
9103  #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE1                                0x9d51
9104  #define mmMARGIN_DEEMPH_LANE2                                                   0x4901
9105  #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2                                0x4901
9106  #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2                                0x49a1
9107  #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2                                0x9a41
9108  #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2                                0x9ae1
9109  #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2                                0x9b81
9110  #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2                                0x9c21
9111  #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2                                0x9cc1
9112  #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE2                                0x9d61
9113  #define mmMARGIN_DEEMPH_LANE3                                                   0x4911
9114  #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3                                0x4911
9115  #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3                                0x49b1
9116  #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3                                0x9a51
9117  #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3                                0x9af1
9118  #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3                                0x9b91
9119  #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3                                0x9c31
9120  #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3                                0x9cd1
9121  #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE3                                0x9d71
9122  #define mmCMD_BUS_GLOBAL_FOR_TX_LANE0                                           0x48e2
9123  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x48e2
9124  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x4982
9125  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9a22
9126  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9ac2
9127  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9b62
9128  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9c02
9129  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9ca2
9130  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE0                        0x9d42
9131  #define mmCMD_BUS_GLOBAL_FOR_TX_LANE1                                           0x48f2
9132  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x48f2
9133  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x4992
9134  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9a32
9135  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9ad2
9136  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9b72
9137  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9c12
9138  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9cb2
9139  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE1                        0x9d52
9140  #define mmCMD_BUS_GLOBAL_FOR_TX_LANE2                                           0x4902
9141  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x4902
9142  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x49a2
9143  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9a42
9144  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9ae2
9145  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9b82
9146  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9c22
9147  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9cc2
9148  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE2                        0x9d62
9149  #define mmCMD_BUS_GLOBAL_FOR_TX_LANE3                                           0x4912
9150  #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x4912
9151  #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x49b2
9152  #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9a52
9153  #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9af2
9154  #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9b92
9155  #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9c32
9156  #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9cd2
9157  #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE3                        0x9d72
9158  #define mmTX_DISP_RFU0_LANE0                                                    0x48e3
9159  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0                                 0x48e3
9160  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0                                 0x4983
9161  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0                                 0x9a23
9162  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0                                 0x9ac3
9163  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0                                 0x9b63
9164  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0                                 0x9c03
9165  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0                                 0x9ca3
9166  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE0                                 0x9d43
9167  #define mmTX_DISP_RFU0_LANE1                                                    0x48f3
9168  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1                                 0x48f3
9169  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1                                 0x4993
9170  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1                                 0x9a33
9171  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1                                 0x9ad3
9172  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1                                 0x9b73
9173  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1                                 0x9c13
9174  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1                                 0x9cb3
9175  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE1                                 0x9d53
9176  #define mmTX_DISP_RFU0_LANE2                                                    0x4903
9177  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2                                 0x4903
9178  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2                                 0x49a3
9179  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2                                 0x9a43
9180  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2                                 0x9ae3
9181  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2                                 0x9b83
9182  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2                                 0x9c23
9183  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2                                 0x9cc3
9184  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE2                                 0x9d63
9185  #define mmTX_DISP_RFU0_LANE3                                                    0x4913
9186  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3                                 0x4913
9187  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3                                 0x49b3
9188  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3                                 0x9a53
9189  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3                                 0x9af3
9190  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3                                 0x9b93
9191  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3                                 0x9c33
9192  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3                                 0x9cd3
9193  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE3                                 0x9d73
9194  #define mmTX_DISP_RFU1_LANE0                                                    0x48e4
9195  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0                                 0x48e4
9196  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0                                 0x4984
9197  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0                                 0x9a24
9198  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0                                 0x9ac4
9199  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0                                 0x9b64
9200  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0                                 0x9c04
9201  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0                                 0x9ca4
9202  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE0                                 0x9d44
9203  #define mmTX_DISP_RFU1_LANE1                                                    0x48f4
9204  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1                                 0x48f4
9205  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1                                 0x4994
9206  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1                                 0x9a34
9207  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1                                 0x9ad4
9208  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1                                 0x9b74
9209  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1                                 0x9c14
9210  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1                                 0x9cb4
9211  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE1                                 0x9d54
9212  #define mmTX_DISP_RFU1_LANE2                                                    0x4904
9213  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2                                 0x4904
9214  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2                                 0x49a4
9215  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2                                 0x9a44
9216  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2                                 0x9ae4
9217  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2                                 0x9b84
9218  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2                                 0x9c24
9219  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2                                 0x9cc4
9220  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE2                                 0x9d64
9221  #define mmTX_DISP_RFU1_LANE3                                                    0x4914
9222  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3                                 0x4914
9223  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3                                 0x49b4
9224  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3                                 0x9a54
9225  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3                                 0x9af4
9226  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3                                 0x9b94
9227  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3                                 0x9c34
9228  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3                                 0x9cd4
9229  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE3                                 0x9d74
9230  #define mmTX_DISP_RFU2_LANE0                                                    0x48e5
9231  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0                                 0x48e5
9232  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0                                 0x4985
9233  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0                                 0x9a25
9234  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0                                 0x9ac5
9235  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0                                 0x9b65
9236  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0                                 0x9c05
9237  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0                                 0x9ca5
9238  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE0                                 0x9d45
9239  #define mmTX_DISP_RFU2_LANE1                                                    0x48f5
9240  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1                                 0x48f5
9241  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1                                 0x4995
9242  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1                                 0x9a35
9243  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1                                 0x9ad5
9244  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1                                 0x9b75
9245  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1                                 0x9c15
9246  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1                                 0x9cb5
9247  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE1                                 0x9d55
9248  #define mmTX_DISP_RFU2_LANE2                                                    0x4905
9249  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2                                 0x4905
9250  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2                                 0x49a5
9251  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2                                 0x9a45
9252  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2                                 0x9ae5
9253  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2                                 0x9b85
9254  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2                                 0x9c25
9255  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2                                 0x9cc5
9256  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE2                                 0x9d65
9257  #define mmTX_DISP_RFU2_LANE3                                                    0x4915
9258  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3                                 0x4915
9259  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3                                 0x49b5
9260  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3                                 0x9a55
9261  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3                                 0x9af5
9262  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3                                 0x9b95
9263  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3                                 0x9c35
9264  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3                                 0x9cd5
9265  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE3                                 0x9d75
9266  #define mmTX_DISP_RFU3_LANE0                                                    0x48e6
9267  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0                                 0x48e6
9268  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0                                 0x4986
9269  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0                                 0x9a26
9270  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0                                 0x9ac6
9271  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0                                 0x9b66
9272  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0                                 0x9c06
9273  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0                                 0x9ca6
9274  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE0                                 0x9d46
9275  #define mmTX_DISP_RFU3_LANE1                                                    0x48f6
9276  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1                                 0x48f6
9277  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1                                 0x4996
9278  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1                                 0x9a36
9279  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1                                 0x9ad6
9280  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1                                 0x9b76
9281  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1                                 0x9c16
9282  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1                                 0x9cb6
9283  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE1                                 0x9d56
9284  #define mmTX_DISP_RFU3_LANE2                                                    0x4906
9285  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2                                 0x4906
9286  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2                                 0x49a6
9287  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2                                 0x9a46
9288  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2                                 0x9ae6
9289  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2                                 0x9b86
9290  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2                                 0x9c26
9291  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2                                 0x9cc6
9292  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE2                                 0x9d66
9293  #define mmTX_DISP_RFU3_LANE3                                                    0x4916
9294  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3                                 0x4916
9295  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3                                 0x49b6
9296  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3                                 0x9a56
9297  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3                                 0x9af6
9298  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3                                 0x9b96
9299  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3                                 0x9c36
9300  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3                                 0x9cd6
9301  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE3                                 0x9d76
9302  #define mmTX_DISP_RFU4_LANE0                                                    0x48e7
9303  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0                                 0x48e7
9304  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0                                 0x4987
9305  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0                                 0x9a27
9306  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0                                 0x9ac7
9307  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0                                 0x9b67
9308  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0                                 0x9c07
9309  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0                                 0x9ca7
9310  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE0                                 0x9d47
9311  #define mmTX_DISP_RFU4_LANE1                                                    0x48f7
9312  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1                                 0x48f7
9313  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1                                 0x4997
9314  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1                                 0x9a37
9315  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1                                 0x9ad7
9316  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1                                 0x9b77
9317  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1                                 0x9c17
9318  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1                                 0x9cb7
9319  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE1                                 0x9d57
9320  #define mmTX_DISP_RFU4_LANE2                                                    0x4907
9321  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2                                 0x4907
9322  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2                                 0x49a7
9323  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2                                 0x9a47
9324  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2                                 0x9ae7
9325  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2                                 0x9b87
9326  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2                                 0x9c27
9327  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2                                 0x9cc7
9328  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE2                                 0x9d67
9329  #define mmTX_DISP_RFU4_LANE3                                                    0x4917
9330  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3                                 0x4917
9331  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3                                 0x49b7
9332  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3                                 0x9a57
9333  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3                                 0x9af7
9334  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3                                 0x9b97
9335  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3                                 0x9c37
9336  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3                                 0x9cd7
9337  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE3                                 0x9d77
9338  #define mmTX_DISP_RFU5_LANE0                                                    0x48e8
9339  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0                                 0x48e8
9340  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0                                 0x4988
9341  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0                                 0x9a28
9342  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0                                 0x9ac8
9343  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0                                 0x9b68
9344  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0                                 0x9c08
9345  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0                                 0x9ca8
9346  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE0                                 0x9d48
9347  #define mmTX_DISP_RFU5_LANE1                                                    0x48f8
9348  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1                                 0x48f8
9349  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1                                 0x4998
9350  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1                                 0x9a38
9351  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1                                 0x9ad8
9352  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1                                 0x9b78
9353  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1                                 0x9c18
9354  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1                                 0x9cb8
9355  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE1                                 0x9d58
9356  #define mmTX_DISP_RFU5_LANE2                                                    0x4908
9357  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2                                 0x4908
9358  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2                                 0x49a8
9359  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2                                 0x9a48
9360  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2                                 0x9ae8
9361  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2                                 0x9b88
9362  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2                                 0x9c28
9363  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2                                 0x9cc8
9364  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE2                                 0x9d68
9365  #define mmTX_DISP_RFU5_LANE3                                                    0x4918
9366  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3                                 0x4918
9367  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3                                 0x49b8
9368  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3                                 0x9a58
9369  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3                                 0x9af8
9370  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3                                 0x9b98
9371  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3                                 0x9c38
9372  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3                                 0x9cd8
9373  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE3                                 0x9d78
9374  #define mmTX_DISP_RFU6_LANE0                                                    0x48e9
9375  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0                                 0x48e9
9376  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0                                 0x4989
9377  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0                                 0x9a29
9378  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0                                 0x9ac9
9379  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0                                 0x9b69
9380  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0                                 0x9c09
9381  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0                                 0x9ca9
9382  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE0                                 0x9d49
9383  #define mmTX_DISP_RFU6_LANE1                                                    0x48f9
9384  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1                                 0x48f9
9385  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1                                 0x4999
9386  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1                                 0x9a39
9387  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1                                 0x9ad9
9388  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1                                 0x9b79
9389  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1                                 0x9c19
9390  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1                                 0x9cb9
9391  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE1                                 0x9d59
9392  #define mmTX_DISP_RFU6_LANE2                                                    0x4909
9393  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2                                 0x4909
9394  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2                                 0x49a9
9395  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2                                 0x9a49
9396  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2                                 0x9ae9
9397  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2                                 0x9b89
9398  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2                                 0x9c29
9399  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2                                 0x9cc9
9400  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE2                                 0x9d69
9401  #define mmTX_DISP_RFU6_LANE3                                                    0x4919
9402  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3                                 0x4919
9403  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3                                 0x49b9
9404  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3                                 0x9a59
9405  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3                                 0x9af9
9406  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3                                 0x9b99
9407  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3                                 0x9c39
9408  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3                                 0x9cd9
9409  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE3                                 0x9d79
9410  #define mmTX_DISP_RFU7_LANE0                                                    0x48ea
9411  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0                                 0x48ea
9412  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0                                 0x498a
9413  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0                                 0x9a2a
9414  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0                                 0x9aca
9415  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0                                 0x9b6a
9416  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0                                 0x9c0a
9417  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0                                 0x9caa
9418  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE0                                 0x9d4a
9419  #define mmTX_DISP_RFU7_LANE1                                                    0x48fa
9420  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1                                 0x48fa
9421  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1                                 0x499a
9422  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1                                 0x9a3a
9423  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1                                 0x9ada
9424  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1                                 0x9b7a
9425  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1                                 0x9c1a
9426  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1                                 0x9cba
9427  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE1                                 0x9d5a
9428  #define mmTX_DISP_RFU7_LANE2                                                    0x490a
9429  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2                                 0x490a
9430  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2                                 0x49aa
9431  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2                                 0x9a4a
9432  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2                                 0x9aea
9433  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2                                 0x9b8a
9434  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2                                 0x9c2a
9435  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2                                 0x9cca
9436  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE2                                 0x9d6a
9437  #define mmTX_DISP_RFU7_LANE3                                                    0x491a
9438  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3                                 0x491a
9439  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3                                 0x49ba
9440  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3                                 0x9a5a
9441  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3                                 0x9afa
9442  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3                                 0x9b9a
9443  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3                                 0x9c3a
9444  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3                                 0x9cda
9445  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE3                                 0x9d7a
9446  #define mmTX_DISP_RFU8_LANE0                                                    0x48eb
9447  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0                                 0x48eb
9448  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0                                 0x498b
9449  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0                                 0x9a2b
9450  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0                                 0x9acb
9451  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0                                 0x9b6b
9452  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0                                 0x9c0b
9453  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0                                 0x9cab
9454  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE0                                 0x9d4b
9455  #define mmTX_DISP_RFU8_LANE1                                                    0x48fb
9456  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1                                 0x48fb
9457  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1                                 0x499b
9458  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1                                 0x9a3b
9459  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1                                 0x9adb
9460  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1                                 0x9b7b
9461  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1                                 0x9c1b
9462  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1                                 0x9cbb
9463  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE1                                 0x9d5b
9464  #define mmTX_DISP_RFU8_LANE2                                                    0x490b
9465  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2                                 0x490b
9466  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2                                 0x49ab
9467  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2                                 0x9a4b
9468  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2                                 0x9aeb
9469  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2                                 0x9b8b
9470  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2                                 0x9c2b
9471  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2                                 0x9ccb
9472  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE2                                 0x9d6b
9473  #define mmTX_DISP_RFU8_LANE3                                                    0x491b
9474  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3                                 0x491b
9475  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3                                 0x49bb
9476  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3                                 0x9a5b
9477  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3                                 0x9afb
9478  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3                                 0x9b9b
9479  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3                                 0x9c3b
9480  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3                                 0x9cdb
9481  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE3                                 0x9d7b
9482  #define mmTX_DISP_RFU9_LANE0                                                    0x48ec
9483  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0                                 0x48ec
9484  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0                                 0x498c
9485  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0                                 0x9a2c
9486  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0                                 0x9acc
9487  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0                                 0x9b6c
9488  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0                                 0x9c0c
9489  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0                                 0x9cac
9490  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE0                                 0x9d4c
9491  #define mmTX_DISP_RFU9_LANE1                                                    0x48fc
9492  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1                                 0x48fc
9493  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1                                 0x499c
9494  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1                                 0x9a3c
9495  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1                                 0x9adc
9496  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1                                 0x9b7c
9497  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1                                 0x9c1c
9498  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1                                 0x9cbc
9499  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE1                                 0x9d5c
9500  #define mmTX_DISP_RFU9_LANE2                                                    0x490c
9501  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2                                 0x490c
9502  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2                                 0x49ac
9503  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2                                 0x9a4c
9504  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2                                 0x9aec
9505  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2                                 0x9b8c
9506  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2                                 0x9c2c
9507  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2                                 0x9ccc
9508  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE2                                 0x9d6c
9509  #define mmTX_DISP_RFU9_LANE3                                                    0x491c
9510  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3                                 0x491c
9511  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3                                 0x49bc
9512  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3                                 0x9a5c
9513  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3                                 0x9afc
9514  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3                                 0x9b9c
9515  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3                                 0x9c3c
9516  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3                                 0x9cdc
9517  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE3                                 0x9d7c
9518  #define mmTX_DISP_RFU10_LANE0                                                   0x48ed
9519  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0                                0x48ed
9520  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0                                0x498d
9521  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0                                0x9a2d
9522  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0                                0x9acd
9523  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0                                0x9b6d
9524  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0                                0x9c0d
9525  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0                                0x9cad
9526  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE0                                0x9d4d
9527  #define mmTX_DISP_RFU10_LANE1                                                   0x48fd
9528  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1                                0x48fd
9529  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1                                0x499d
9530  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1                                0x9a3d
9531  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1                                0x9add
9532  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1                                0x9b7d
9533  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1                                0x9c1d
9534  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1                                0x9cbd
9535  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE1                                0x9d5d
9536  #define mmTX_DISP_RFU10_LANE2                                                   0x490d
9537  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2                                0x490d
9538  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2                                0x49ad
9539  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2                                0x9a4d
9540  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2                                0x9aed
9541  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2                                0x9b8d
9542  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2                                0x9c2d
9543  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2                                0x9ccd
9544  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE2                                0x9d6d
9545  #define mmTX_DISP_RFU10_LANE3                                                   0x491d
9546  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3                                0x491d
9547  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3                                0x49bd
9548  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3                                0x9a5d
9549  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3                                0x9afd
9550  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3                                0x9b9d
9551  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3                                0x9c3d
9552  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3                                0x9cdd
9553  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE3                                0x9d7d
9554  #define mmTX_DISP_RFU11_LANE0                                                   0x48ee
9555  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0                                0x48ee
9556  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0                                0x498e
9557  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0                                0x9a2e
9558  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0                                0x9ace
9559  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0                                0x9b6e
9560  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0                                0x9c0e
9561  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0                                0x9cae
9562  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE0                                0x9d4e
9563  #define mmTX_DISP_RFU11_LANE1                                                   0x48fe
9564  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1                                0x48fe
9565  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1                                0x499e
9566  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1                                0x9a3e
9567  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1                                0x9ade
9568  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1                                0x9b7e
9569  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1                                0x9c1e
9570  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1                                0x9cbe
9571  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE1                                0x9d5e
9572  #define mmTX_DISP_RFU11_LANE2                                                   0x490e
9573  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2                                0x490e
9574  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2                                0x49ae
9575  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2                                0x9a4e
9576  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2                                0x9aee
9577  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2                                0x9b8e
9578  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2                                0x9c2e
9579  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2                                0x9cce
9580  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE2                                0x9d6e
9581  #define mmTX_DISP_RFU11_LANE3                                                   0x491e
9582  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3                                0x491e
9583  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3                                0x49be
9584  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3                                0x9a5e
9585  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3                                0x9afe
9586  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3                                0x9b9e
9587  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3                                0x9c3e
9588  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3                                0x9cde
9589  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE3                                0x9d7e
9590  #define mmTX_DISP_RFU12_LANE0                                                   0x48ef
9591  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0                                0x48ef
9592  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0                                0x498f
9593  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0                                0x9a2f
9594  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0                                0x9acf
9595  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0                                0x9b6f
9596  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0                                0x9c0f
9597  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0                                0x9caf
9598  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE0                                0x9d4f
9599  #define mmTX_DISP_RFU12_LANE1                                                   0x48ff
9600  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1                                0x48ff
9601  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1                                0x499f
9602  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1                                0x9a3f
9603  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1                                0x9adf
9604  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1                                0x9b7f
9605  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1                                0x9c1f
9606  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1                                0x9cbf
9607  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE1                                0x9d5f
9608  #define mmTX_DISP_RFU12_LANE2                                                   0x490f
9609  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2                                0x490f
9610  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2                                0x49af
9611  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2                                0x9a4f
9612  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2                                0x9aef
9613  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2                                0x9b8f
9614  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2                                0x9c2f
9615  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2                                0x9ccf
9616  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE2                                0x9d6f
9617  #define mmTX_DISP_RFU12_LANE3                                                   0x491f
9618  #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3                                0x491f
9619  #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3                                0x49bf
9620  #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3                                0x9a5f
9621  #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3                                0x9aff
9622  #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3                                0x9b9f
9623  #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3                                0x9c3f
9624  #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3                                0x9cdf
9625  #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE3                                0x9d7f
9626  #define mmCOMMON_MAR_DEEMPH_NOM                                                 0x48c3
9627  #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM                              0x48c3
9628  #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM                              0x4963
9629  #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM                              0x9a03
9630  #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM                              0x9aa3
9631  #define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM                              0x9b43
9632  #define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM                              0x9be3
9633  #define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM                              0x9c83
9634  #define mmDC_COMBOPHYCMREGS7_COMMON_MAR_DEEMPH_NOM                              0x9d23
9635  #define mmCOMMON_LANE_PWRMGMT                                                   0x48c4
9636  #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT                                0x48c4
9637  #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT                                0x4964
9638  #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT                                0x9a04
9639  #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT                                0x9aa4
9640  #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT                                0x9b44
9641  #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT                                0x9be4
9642  #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT                                0x9c84
9643  #define mmDC_COMBOPHYCMREGS7_COMMON_LANE_PWRMGMT                                0x9d24
9644  #define mmCOMMON_TXCNTRL                                                        0x48c5
9645  #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL                                     0x48c5
9646  #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL                                     0x4965
9647  #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL                                     0x9a05
9648  #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL                                     0x9aa5
9649  #define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL                                     0x9b45
9650  #define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL                                     0x9be5
9651  #define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL                                     0x9c85
9652  #define mmDC_COMBOPHYCMREGS7_COMMON_TXCNTRL                                     0x9d25
9653  #define mmCOMMON_TMDP                                                           0x48c6
9654  #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP                                        0x48c6
9655  #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP                                        0x4966
9656  #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP                                        0x9a06
9657  #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP                                        0x9aa6
9658  #define mmDC_COMBOPHYCMREGS4_COMMON_TMDP                                        0x9b46
9659  #define mmDC_COMBOPHYCMREGS5_COMMON_TMDP                                        0x9be6
9660  #define mmDC_COMBOPHYCMREGS6_COMMON_TMDP                                        0x9c86
9661  #define mmDC_COMBOPHYCMREGS7_COMMON_TMDP                                        0x9d26
9662  #define mmCOMMON_LANE_RESETS                                                    0x48c7
9663  #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS                                 0x48c7
9664  #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS                                 0x4967
9665  #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS                                 0x9a07
9666  #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS                                 0x9aa7
9667  #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS                                 0x9b47
9668  #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS                                 0x9be7
9669  #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS                                 0x9c87
9670  #define mmDC_COMBOPHYCMREGS7_COMMON_LANE_RESETS                                 0x9d27
9671  #define mmCOMMON_ZCALCODE_CTRL                                                  0x48c8
9672  #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL                               0x48c8
9673  #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL                               0x4968
9674  #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL                               0x9a08
9675  #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL                               0x9aa8
9676  #define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL                               0x9b48
9677  #define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL                               0x9be8
9678  #define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL                               0x9c88
9679  #define mmDC_COMBOPHYCMREGS7_COMMON_ZCALCODE_CTRL                               0x9d28
9680  #define mmCOMMON_DISP_RFU1                                                      0x48c9
9681  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1                                   0x48c9
9682  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1                                   0x4969
9683  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1                                   0x9a09
9684  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1                                   0x9aa9
9685  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1                                   0x9b49
9686  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1                                   0x9be9
9687  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1                                   0x9c89
9688  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU1                                   0x9d29
9689  #define mmCOMMON_DISP_RFU2                                                      0x48ca
9690  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2                                   0x48ca
9691  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2                                   0x496a
9692  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2                                   0x9a0a
9693  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2                                   0x9aaa
9694  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2                                   0x9b4a
9695  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2                                   0x9bea
9696  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2                                   0x9c8a
9697  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU2                                   0x9d2a
9698  #define mmCOMMON_DISP_RFU3                                                      0x48cb
9699  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3                                   0x48cb
9700  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3                                   0x496b
9701  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3                                   0x9a0b
9702  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3                                   0x9aab
9703  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3                                   0x9b4b
9704  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3                                   0x9beb
9705  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3                                   0x9c8b
9706  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU3                                   0x9d2b
9707  #define mmCOMMON_DISP_RFU4                                                      0x48cc
9708  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4                                   0x48cc
9709  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4                                   0x496c
9710  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4                                   0x9a0c
9711  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4                                   0x9aac
9712  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4                                   0x9b4c
9713  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4                                   0x9bec
9714  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4                                   0x9c8c
9715  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU4                                   0x9d2c
9716  #define mmCOMMON_DISP_RFU5                                                      0x48cd
9717  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5                                   0x48cd
9718  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5                                   0x496d
9719  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5                                   0x9a0d
9720  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5                                   0x9aad
9721  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5                                   0x9b4d
9722  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5                                   0x9bed
9723  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5                                   0x9c8d
9724  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU5                                   0x9d2d
9725  #define mmCOMMON_DISP_RFU6                                                      0x48ce
9726  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6                                   0x48ce
9727  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6                                   0x496e
9728  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6                                   0x9a0e
9729  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6                                   0x9aae
9730  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6                                   0x9b4e
9731  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6                                   0x9bee
9732  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6                                   0x9c8e
9733  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU6                                   0x9d2e
9734  #define mmCOMMON_DISP_RFU7                                                      0x48cf
9735  #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7                                   0x48cf
9736  #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7                                   0x496f
9737  #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7                                   0x9a0f
9738  #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7                                   0x9aaf
9739  #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7                                   0x9b4f
9740  #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7                                   0x9bef
9741  #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7                                   0x9c8f
9742  #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU7                                   0x9d2f
9743  #define mmFREQ_CTRL0                                                            0x4920
9744  #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0                                        0x4920
9745  #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0                                        0x49c0
9746  #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0                                        0x9a60
9747  #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0                                        0x9b00
9748  #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0                                        0x9ba0
9749  #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0                                        0x9c40
9750  #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0                                        0x9ce0
9751  #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL0                                        0x9d80
9752  #define mmFREQ_CTRL1                                                            0x4921
9753  #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1                                        0x4921
9754  #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1                                        0x49c1
9755  #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1                                        0x9a61
9756  #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1                                        0x9b01
9757  #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1                                        0x9ba1
9758  #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1                                        0x9c41
9759  #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1                                        0x9ce1
9760  #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL1                                        0x9d81
9761  #define mmFREQ_CTRL2                                                            0x4922
9762  #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2                                        0x4922
9763  #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2                                        0x49c2
9764  #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2                                        0x9a62
9765  #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2                                        0x9b02
9766  #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2                                        0x9ba2
9767  #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2                                        0x9c42
9768  #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2                                        0x9ce2
9769  #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL2                                        0x9d82
9770  #define mmFREQ_CTRL3                                                            0x4923
9771  #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3                                        0x4923
9772  #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3                                        0x49c3
9773  #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3                                        0x9a63
9774  #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3                                        0x9b03
9775  #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3                                        0x9ba3
9776  #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3                                        0x9c43
9777  #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3                                        0x9ce3
9778  #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL3                                        0x9d83
9779  #define mmBW_CTRL_COARSE                                                        0x4924
9780  #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE                                    0x4924
9781  #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE                                    0x49c4
9782  #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE                                    0x9a64
9783  #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE                                    0x9b04
9784  #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE                                    0x9ba4
9785  #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE                                    0x9c44
9786  #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE                                    0x9ce4
9787  #define mmDC_COMBOPHYPLLREGS7_BW_CTRL_COARSE                                    0x9d84
9788  #define mmBW_CTRL_FINE                                                          0x4925
9789  #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE                                      0x4925
9790  #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE                                      0x49c5
9791  #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE                                      0x9a65
9792  #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE                                      0x9b05
9793  #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE                                      0x9ba5
9794  #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE                                      0x9c45
9795  #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE                                      0x9ce5
9796  #define mmDC_COMBOPHYPLLREGS7_BW_CTRL_FINE                                      0x9d85
9797  #define mmCAL_CTRL                                                              0x4926
9798  #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL                                          0x4926
9799  #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL                                          0x49c6
9800  #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL                                          0x9a66
9801  #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL                                          0x9b06
9802  #define mmDC_COMBOPHYPLLREGS4_CAL_CTRL                                          0x9ba6
9803  #define mmDC_COMBOPHYPLLREGS5_CAL_CTRL                                          0x9c46
9804  #define mmDC_COMBOPHYPLLREGS6_CAL_CTRL                                          0x9ce6
9805  #define mmDC_COMBOPHYPLLREGS7_CAL_CTRL                                          0x9d86
9806  #define mmLOOP_CTRL                                                             0x4927
9807  #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL                                         0x4927
9808  #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL                                         0x49c7
9809  #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL                                         0x9a67
9810  #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL                                         0x9b07
9811  #define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL                                         0x9ba7
9812  #define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL                                         0x9c47
9813  #define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL                                         0x9ce7
9814  #define mmDC_COMBOPHYPLLREGS7_LOOP_CTRL                                         0x9d87
9815  #define mmDEBUG0                                                                0x4928
9816  #define mmDC_COMBOPHYPLLREGS0_DEBUG0                                            0x4928
9817  #define mmDC_COMBOPHYPLLREGS1_DEBUG0                                            0x49c8
9818  #define mmDC_COMBOPHYPLLREGS2_DEBUG0                                            0x9a68
9819  #define mmDC_COMBOPHYPLLREGS3_DEBUG0                                            0x9b08
9820  #define mmDC_COMBOPHYPLLREGS4_DEBUG0                                            0x9ba8
9821  #define mmDC_COMBOPHYPLLREGS5_DEBUG0                                            0x9c48
9822  #define mmDC_COMBOPHYPLLREGS6_DEBUG0                                            0x9ce8
9823  #define mmDC_COMBOPHYPLLREGS7_DEBUG0                                            0x9d88
9824  #define mmVREG_CFG                                                              0x4929
9825  #define mmDC_COMBOPHYPLLREGS0_VREG_CFG                                          0x4929
9826  #define mmDC_COMBOPHYPLLREGS1_VREG_CFG                                          0x49c9
9827  #define mmDC_COMBOPHYPLLREGS2_VREG_CFG                                          0x9a69
9828  #define mmDC_COMBOPHYPLLREGS3_VREG_CFG                                          0x9b09
9829  #define mmDC_COMBOPHYPLLREGS4_VREG_CFG                                          0x9ba9
9830  #define mmDC_COMBOPHYPLLREGS5_VREG_CFG                                          0x9c49
9831  #define mmDC_COMBOPHYPLLREGS6_VREG_CFG                                          0x9ce9
9832  #define mmDC_COMBOPHYPLLREGS7_VREG_CFG                                          0x9d89
9833  #define mmOBSERVE0                                                              0x492a
9834  #define mmDC_COMBOPHYPLLREGS0_OBSERVE0                                          0x492a
9835  #define mmDC_COMBOPHYPLLREGS1_OBSERVE0                                          0x49ca
9836  #define mmDC_COMBOPHYPLLREGS2_OBSERVE0                                          0x9a6a
9837  #define mmDC_COMBOPHYPLLREGS3_OBSERVE0                                          0x9b0a
9838  #define mmDC_COMBOPHYPLLREGS4_OBSERVE0                                          0x9baa
9839  #define mmDC_COMBOPHYPLLREGS5_OBSERVE0                                          0x9c4a
9840  #define mmDC_COMBOPHYPLLREGS6_OBSERVE0                                          0x9cea
9841  #define mmDC_COMBOPHYPLLREGS7_OBSERVE0                                          0x9d8a
9842  #define mmOBSERVE1                                                              0x492b
9843  #define mmDC_COMBOPHYPLLREGS0_OBSERVE1                                          0x492b
9844  #define mmDC_COMBOPHYPLLREGS1_OBSERVE1                                          0x49cb
9845  #define mmDC_COMBOPHYPLLREGS2_OBSERVE1                                          0x9a6b
9846  #define mmDC_COMBOPHYPLLREGS3_OBSERVE1                                          0x9b0b
9847  #define mmDC_COMBOPHYPLLREGS4_OBSERVE1                                          0x9bab
9848  #define mmDC_COMBOPHYPLLREGS5_OBSERVE1                                          0x9c4b
9849  #define mmDC_COMBOPHYPLLREGS6_OBSERVE1                                          0x9ceb
9850  #define mmDC_COMBOPHYPLLREGS7_OBSERVE1                                          0x9d8b
9851  #define mmDFT_OUT                                                               0x492c
9852  #define mmDC_COMBOPHYPLLREGS0_DFT_OUT                                           0x492c
9853  #define mmDC_COMBOPHYPLLREGS1_DFT_OUT                                           0x49cc
9854  #define mmDC_COMBOPHYPLLREGS2_DFT_OUT                                           0x9a6c
9855  #define mmDC_COMBOPHYPLLREGS3_DFT_OUT                                           0x9b0c
9856  #define mmDC_COMBOPHYPLLREGS4_DFT_OUT                                           0x9bac
9857  #define mmDC_COMBOPHYPLLREGS5_DFT_OUT                                           0x9c4c
9858  #define mmDC_COMBOPHYPLLREGS6_DFT_OUT                                           0x9cec
9859  #define mmDC_COMBOPHYPLLREGS7_DFT_OUT                                           0x9d8c
9860  #define mmPLL_WRAP_CNTRL1                                                       0x495e
9861  #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1                                   0x495e
9862  #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1                                   0x49fe
9863  #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1                                   0x9a9e
9864  #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1                                   0x9b3e
9865  #define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL1                                   0x9bde
9866  #define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL1                                   0x9c7e
9867  #define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL1                                   0x9d1e
9868  #define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL1                                   0x9dbe
9869  #define mmPLL_WRAP_CNTRL                                                        0x495f
9870  #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL                                    0x495f
9871  #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL                                    0x49ff
9872  #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL                                    0x9a9f
9873  #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL                                    0x9b3f
9874  #define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL                                    0x9bdf
9875  #define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL                                    0x9c7f
9876  #define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL                                    0x9d1f
9877  #define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL                                    0x9dbf
9878  #define mmPPLL_VREG_CFG                                                         0x1700
9879  #define mmDC_DISPLAYPLLREGS0_PPLL_VREG_CFG                                      0x1700
9880  #define mmDC_DISPLAYPLLREGS1_PPLL_VREG_CFG                                      0x172a
9881  #define mmDC_DISPLAYPLLREGS2_PPLL_VREG_CFG                                      0x1754
9882  #define mmPPLL_MODE_CNTL                                                        0x1701
9883  #define mmDC_DISPLAYPLLREGS0_PPLL_MODE_CNTL                                     0x1701
9884  #define mmDC_DISPLAYPLLREGS1_PPLL_MODE_CNTL                                     0x172b
9885  #define mmDC_DISPLAYPLLREGS2_PPLL_MODE_CNTL                                     0x1755
9886  #define mmPPLL_FREQ_CTRL0                                                       0x1702
9887  #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL0                                    0x1702
9888  #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL0                                    0x172c
9889  #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL0                                    0x1756
9890  #define mmPPLL_FREQ_CTRL1                                                       0x1703
9891  #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL1                                    0x1703
9892  #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL1                                    0x172d
9893  #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL1                                    0x1757
9894  #define mmPPLL_FREQ_CTRL2                                                       0x1704
9895  #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL2                                    0x1704
9896  #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL2                                    0x172e
9897  #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL2                                    0x1758
9898  #define mmPPLL_FREQ_CTRL3                                                       0x1705
9899  #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL3                                    0x1705
9900  #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL3                                    0x172f
9901  #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL3                                    0x1759
9902  #define mmPPLL_BW_CTRL_COARSE                                                   0x1706
9903  #define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_COARSE                                0x1706
9904  #define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_COARSE                                0x1730
9905  #define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_COARSE                                0x175a
9906  #define mmPPLL_BW_CTRL_FINE                                                     0x1708
9907  #define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_FINE                                  0x1708
9908  #define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_FINE                                  0x1732
9909  #define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_FINE                                  0x175c
9910  #define mmPPLL_CAL_CTRL                                                         0x1709
9911  #define mmDC_DISPLAYPLLREGS0_PPLL_CAL_CTRL                                      0x1709
9912  #define mmDC_DISPLAYPLLREGS1_PPLL_CAL_CTRL                                      0x1733
9913  #define mmDC_DISPLAYPLLREGS2_PPLL_CAL_CTRL                                      0x175d
9914  #define mmPPLL_LOOP_CTRL                                                        0x170a
9915  #define mmDC_DISPLAYPLLREGS0_PPLL_LOOP_CTRL                                     0x170a
9916  #define mmDC_DISPLAYPLLREGS1_PPLL_LOOP_CTRL                                     0x1734
9917  #define mmDC_DISPLAYPLLREGS2_PPLL_LOOP_CTRL                                     0x175e
9918  #define mmPPLL_REFCLK_CNTL                                                      0x1718
9919  #define mmDC_DISPLAYPLLREGS0_PPLL_REFCLK_CNTL                                   0x1718
9920  #define mmDC_DISPLAYPLLREGS1_PPLL_REFCLK_CNTL                                   0x1742
9921  #define mmDC_DISPLAYPLLREGS2_PPLL_REFCLK_CNTL                                   0x176c
9922  #define mmPPLL_CLKOUT_CNTL                                                      0x1719
9923  #define mmDC_DISPLAYPLLREGS0_PPLL_CLKOUT_CNTL                                   0x1719
9924  #define mmDC_DISPLAYPLLREGS1_PPLL_CLKOUT_CNTL                                   0x1743
9925  #define mmDC_DISPLAYPLLREGS2_PPLL_CLKOUT_CNTL                                   0x176d
9926  #define mmPPLL_DFT_CNTL                                                         0x171a
9927  #define mmDC_DISPLAYPLLREGS0_PPLL_DFT_CNTL                                      0x171a
9928  #define mmDC_DISPLAYPLLREGS1_PPLL_DFT_CNTL                                      0x1744
9929  #define mmDC_DISPLAYPLLREGS2_PPLL_DFT_CNTL                                      0x176e
9930  #define mmPPLL_ANALOG_CNTL                                                      0x171b
9931  #define mmDC_DISPLAYPLLREGS0_PPLL_ANALOG_CNTL                                   0x171b
9932  #define mmDC_DISPLAYPLLREGS1_PPLL_ANALOG_CNTL                                   0x1745
9933  #define mmDC_DISPLAYPLLREGS2_PPLL_ANALOG_CNTL                                   0x176f
9934  #define mmPPLL_POSTDIV                                                          0x171c
9935  #define mmDC_DISPLAYPLLREGS0_PPLL_POSTDIV                                       0x171c
9936  #define mmDC_DISPLAYPLLREGS1_PPLL_POSTDIV                                       0x1746
9937  #define mmDC_DISPLAYPLLREGS2_PPLL_POSTDIV                                       0x1770
9938  #define mmPPLL_DEBUG0                                                           0x1720
9939  #define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG0                                        0x1720
9940  #define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG0                                        0x174a
9941  #define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG0                                        0x1774
9942  #define mmPPLL_OBSERVE0                                                         0x1721
9943  #define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0                                      0x1721
9944  #define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0                                      0x174b
9945  #define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0                                      0x1775
9946  #define mmPPLL_OBSERVE1                                                         0x1722
9947  #define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE1                                      0x1722
9948  #define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE1                                      0x174c
9949  #define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE1                                      0x1776
9950  #define mmPPLL_UPDATE_CNTL                                                      0x1724
9951  #define mmDC_DISPLAYPLLREGS0_PPLL_UPDATE_CNTL                                   0x1724
9952  #define mmDC_DISPLAYPLLREGS1_PPLL_UPDATE_CNTL                                   0x174e
9953  #define mmDC_DISPLAYPLLREGS2_PPLL_UPDATE_CNTL                                   0x1778
9954  #define mmPPLL_OBSERVE0_OUT                                                     0x1725
9955  #define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0_OUT                                  0x1725
9956  #define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0_OUT                                  0x174f
9957  #define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0_OUT                                  0x1779
9958  #define mmPPLL_STATUS_DEBUG1                                                    0x1726
9959  #define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG1                                 0x1726
9960  #define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG1                                 0x1750
9961  #define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG1                                 0x177a
9962  #define mmPPLL_DEBUG_MUX_CNTL                                                   0x1727
9963  #define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG_MUX_CNTL                                0x1727
9964  #define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG_MUX_CNTL                                0x1751
9965  #define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG_MUX_CNTL                                0x177b
9966  #define mmPPLL_DIV_UPDATE_DEBUG                                                 0x1728
9967  #define mmDC_DISPLAYPLLREGS0_PPLL_DIV_UPDATE_DEBUG                              0x1728
9968  #define mmDC_DISPLAYPLLREGS1_PPLL_DIV_UPDATE_DEBUG                              0x1752
9969  #define mmDC_DISPLAYPLLREGS2_PPLL_DIV_UPDATE_DEBUG                              0x177c
9970  #define mmPPLL_STATUS_DEBUG0                                                    0x1729
9971  #define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG0                                 0x1729
9972  #define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG0                                 0x1753
9973  #define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG0                                 0x177d
9974  #define mmCOMP_EN_CTL                                                           0x9dc0
9975  #define mmDPCSTX_PHY_CNTL                                                       0x48d0
9976  #define mmDPCSTX0_DPCSTX_PHY_CNTL                                               0x48d0
9977  #define mmDPCSTX1_DPCSTX_PHY_CNTL                                               0x4970
9978  #define mmDPCSTX2_DPCSTX_PHY_CNTL                                               0x9a10
9979  #define mmDPCSTX3_DPCSTX_PHY_CNTL                                               0x9ab0
9980  #define mmDPCSTX4_DPCSTX_PHY_CNTL                                               0x9b50
9981  #define mmDPCSTX5_DPCSTX_PHY_CNTL                                               0x9bf0
9982  #define mmDPCSTX6_DPCSTX_PHY_CNTL                                               0x9c90
9983  #define mmDPCSTX7_DPCSTX_PHY_CNTL                                               0x9d30
9984  #define mmDPCSTX_TX_CLOCK_CNTL                                                  0x48d1
9985  #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                          0x48d1
9986  #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                          0x4971
9987  #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                          0x9a11
9988  #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                          0x9ab1
9989  #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                          0x9b51
9990  #define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL                                          0x9bf1
9991  #define mmDPCSTX6_DPCSTX_TX_CLOCK_CNTL                                          0x9c91
9992  #define mmDPCSTX7_DPCSTX_TX_CLOCK_CNTL                                          0x9d31
9993  #define mmDPCSTX_TX_CNTL                                                        0x48d3
9994  #define mmDPCSTX0_DPCSTX_TX_CNTL                                                0x48d3
9995  #define mmDPCSTX1_DPCSTX_TX_CNTL                                                0x4973
9996  #define mmDPCSTX2_DPCSTX_TX_CNTL                                                0x9a13
9997  #define mmDPCSTX3_DPCSTX_TX_CNTL                                                0x9ab3
9998  #define mmDPCSTX4_DPCSTX_TX_CNTL                                                0x9b53
9999  #define mmDPCSTX5_DPCSTX_TX_CNTL                                                0x9bf3
10000  #define mmDPCSTX6_DPCSTX_TX_CNTL                                                0x9c93
10001  #define mmDPCSTX7_DPCSTX_TX_CNTL                                                0x9d33
10002  #define mmDPCSTX_CBUS_CNTL                                                      0x48d5
10003  #define mmDPCSTX0_DPCSTX_CBUS_CNTL                                              0x48d5
10004  #define mmDPCSTX1_DPCSTX_CBUS_CNTL                                              0x4975
10005  #define mmDPCSTX2_DPCSTX_CBUS_CNTL                                              0x9a15
10006  #define mmDPCSTX3_DPCSTX_CBUS_CNTL                                              0x9ab5
10007  #define mmDPCSTX4_DPCSTX_CBUS_CNTL                                              0x9b55
10008  #define mmDPCSTX5_DPCSTX_CBUS_CNTL                                              0x9bf5
10009  #define mmDPCSTX6_DPCSTX_CBUS_CNTL                                              0x9c95
10010  #define mmDPCSTX7_DPCSTX_CBUS_CNTL                                              0x9d35
10011  #define mmDPCSTX_REG_ERROR_STATUS                                               0x48d6
10012  #define mmDPCSTX0_DPCSTX_REG_ERROR_STATUS                                       0x48d6
10013  #define mmDPCSTX1_DPCSTX_REG_ERROR_STATUS                                       0x4976
10014  #define mmDPCSTX2_DPCSTX_REG_ERROR_STATUS                                       0x9a16
10015  #define mmDPCSTX3_DPCSTX_REG_ERROR_STATUS                                       0x9ab6
10016  #define mmDPCSTX4_DPCSTX_REG_ERROR_STATUS                                       0x9b56
10017  #define mmDPCSTX5_DPCSTX_REG_ERROR_STATUS                                       0x9bf6
10018  #define mmDPCSTX6_DPCSTX_REG_ERROR_STATUS                                       0x9c96
10019  #define mmDPCSTX7_DPCSTX_REG_ERROR_STATUS                                       0x9d36
10020  #define mmDPCSTX_TX_ERROR_STATUS                                                0x48d7
10021  #define mmDPCSTX0_DPCSTX_TX_ERROR_STATUS                                        0x48d7
10022  #define mmDPCSTX1_DPCSTX_TX_ERROR_STATUS                                        0x4977
10023  #define mmDPCSTX2_DPCSTX_TX_ERROR_STATUS                                        0x9a17
10024  #define mmDPCSTX3_DPCSTX_TX_ERROR_STATUS                                        0x9ab7
10025  #define mmDPCSTX4_DPCSTX_TX_ERROR_STATUS                                        0x9b57
10026  #define mmDPCSTX5_DPCSTX_TX_ERROR_STATUS                                        0x9bf7
10027  #define mmDPCSTX6_DPCSTX_TX_ERROR_STATUS                                        0x9c97
10028  #define mmDPCSTX7_DPCSTX_TX_ERROR_STATUS                                        0x9d37
10029  #define mmDPCSTX_PLL_UPDATE_ADDR                                                0x48d8
10030  #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                        0x48d8
10031  #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                        0x4978
10032  #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                        0x9a18
10033  #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                        0x9ab8
10034  #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                        0x9b58
10035  #define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR                                        0x9bf8
10036  #define mmDPCSTX6_DPCSTX_PLL_UPDATE_ADDR                                        0x9c98
10037  #define mmDPCSTX7_DPCSTX_PLL_UPDATE_ADDR                                        0x9d38
10038  #define mmDPCSTX_PLL_UPDATE_DATA                                                0x48d9
10039  #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                        0x48d9
10040  #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                        0x4979
10041  #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                        0x9a19
10042  #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                        0x9ab9
10043  #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                        0x9b59
10044  #define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA                                        0x9bf9
10045  #define mmDPCSTX6_DPCSTX_PLL_UPDATE_DATA                                        0x9c99
10046  #define mmDPCSTX7_DPCSTX_PLL_UPDATE_DATA                                        0x9d39
10047  #define mmDPCSTX_INDEX_MODE_ADDR                                                0x48da
10048  #define mmDPCSTX0_DPCSTX_INDEX_MODE_ADDR                                        0x48da
10049  #define mmDPCSTX1_DPCSTX_INDEX_MODE_ADDR                                        0x497a
10050  #define mmDPCSTX2_DPCSTX_INDEX_MODE_ADDR                                        0x9a1a
10051  #define mmDPCSTX3_DPCSTX_INDEX_MODE_ADDR                                        0x9aba
10052  #define mmDPCSTX4_DPCSTX_INDEX_MODE_ADDR                                        0x9b5a
10053  #define mmDPCSTX5_DPCSTX_INDEX_MODE_ADDR                                        0x9bfa
10054  #define mmDPCSTX6_DPCSTX_INDEX_MODE_ADDR                                        0x9c9a
10055  #define mmDPCSTX7_DPCSTX_INDEX_MODE_ADDR                                        0x9d3a
10056  #define mmDPCSTX_INDEX_MODE_DATA                                                0x48db
10057  #define mmDPCSTX0_DPCSTX_INDEX_MODE_DATA                                        0x48db
10058  #define mmDPCSTX1_DPCSTX_INDEX_MODE_DATA                                        0x497b
10059  #define mmDPCSTX2_DPCSTX_INDEX_MODE_DATA                                        0x9a1b
10060  #define mmDPCSTX3_DPCSTX_INDEX_MODE_DATA                                        0x9abb
10061  #define mmDPCSTX4_DPCSTX_INDEX_MODE_DATA                                        0x9b5b
10062  #define mmDPCSTX5_DPCSTX_INDEX_MODE_DATA                                        0x9bfb
10063  #define mmDPCSTX6_DPCSTX_INDEX_MODE_DATA                                        0x9c9b
10064  #define mmDPCSTX7_DPCSTX_INDEX_MODE_DATA                                        0x9d3b
10065  #define mmDPCSTX_DEBUG_CONFIG                                                   0x48dc
10066  #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                           0x48dc
10067  #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                           0x497c
10068  #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                           0x9a1c
10069  #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                           0x9abc
10070  #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                           0x9b5c
10071  #define mmDPCSTX5_DPCSTX_DEBUG_CONFIG                                           0x9bfc
10072  #define mmDPCSTX6_DPCSTX_DEBUG_CONFIG                                           0x9c9c
10073  #define mmDPCSTX7_DPCSTX_DEBUG_CONFIG                                           0x9d3c
10074  #define mmDPCSTX_TEST_DEBUG_DATA                                                0x48dd
10075  #define mmDPCSTX0_DPCSTX_TEST_DEBUG_DATA                                        0x48dd
10076  #define mmDPCSTX1_DPCSTX_TEST_DEBUG_DATA                                        0x497d
10077  #define mmDPCSTX2_DPCSTX_TEST_DEBUG_DATA                                        0x9a1d
10078  #define mmDPCSTX3_DPCSTX_TEST_DEBUG_DATA                                        0x9abd
10079  #define mmDPCSTX4_DPCSTX_TEST_DEBUG_DATA                                        0x9b5d
10080  #define mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA                                        0x9bfd
10081  #define mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA                                        0x9c9d
10082  #define mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA                                        0x9d3d
10083  
10084  #endif /* DCE_11_2_D_H */
10085