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Searched refs:ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h13157 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR macro
Ddcn_1_0_offset.h13410 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR macro
Ddcn_2_0_0_offset.h16830 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h17223 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR macro