Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance
90 } interrupt_status_offsets[6] = { { variable3025 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()3031 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()3042 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()3146 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()3147 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
93 } interrupt_status_offsets[6] = { { variable2933 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()2939 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()2950 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()3054 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()3055 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
90 } interrupt_status_offsets[] = { { variable3214 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()3219 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()3231 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()3260 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()3261 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
92 } interrupt_status_offsets[] = { { variable3340 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()3346 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()3358 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()3387 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()3388 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
