Searched refs:int_sel (Results 1 – 13 of 13) sorted by relevance
148 enum _RELEASE_MEM_int_sel_enum int_sel:3;
474 enum RELEASE_MEM_int_sel_enum int_sel:3;
534 enum mec_release_mem_int_sel_enum int_sel:3;
321 packet->bitfields3.int_sel = in pm_release_mem_v10()
349 packet->bitfields3.int_sel = in pm_release_mem_vi()
362 packet->bitfields3.int_sel = in pm_release_mem_v9()
146 rm_packet->bitfields3.int_sel = in dbgdev_diq_submit_ib()
180 u32 msr, isr, int_sel, service; in pcap_isr_work() local189 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); in pcap_isr_work()190 isr &= ~int_sel; in pcap_isr_work()
2186 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_gfx() local2209 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()2228 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_compute() local2236 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
6185 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_gfx() local6196 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()6362 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_compute() local6371 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
1839 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v6_0_ring_emit_fence() local1858 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); in gfx_v6_0_ring_emit_fence()
4489 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v10_0_ring_emit_fence() local4493 int_sel = false; in gfx_v10_0_ring_emit_fence()4505 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v10_0_ring_emit_fence()
5088 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_0_ring_emit_fence() local5101 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
