Searched refs:initial_offset (Results 1 – 9 of 9) sorted by relevance
176 pps_payload->initial_offset = in drm_dsc_pps_payload_pack()177 cpu_to_be16(dsc_cfg->initial_offset); in drm_dsc_pps_payload_pack()350 vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()384 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
56 to->initial_offset = from->initial_offset; in copy_pps_fields()81 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
172 u16 initial_offset; member444 __be16 initial_offset; member
44 u16 initial_offset; member413 vdsc_cfg->initial_offset = in intel_dp_compute_dsc_params()414 rc_params[row_index][column_index].initial_offset; in intel_dp_compute_dsc_params()454 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dp_compute_dsc_params()670 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_configure_pps_for_dsc_encoder()
276 nd_btt->initial_offset = 0; in nd_btt_version()291 nd_btt->initial_offset = SZ_4K; in nd_btt_version()
189 int initial_offset; member
34 return offset + nd_btt->initial_offset; in adjust_initial_offset()1696 rawsize = nvdimm_namespace_capacity(ndns) - nd_btt->initial_offset; in nvdimm_namespace_attach_btt()1700 ARENA_MIN_SIZE + nd_btt->initial_offset); in nvdimm_namespace_attach_btt()
280 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); in dsc_log_pps()486 reg_vals->pps.initial_offset = 6144; in dsc_init_reg_values()603 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()
11371 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) argument
