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Searched refs:ih_rb_cntl (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c49 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_enable_interrupts() local
51 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in vega10_ih_enable_interrupts()
52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts()
54 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { in vega10_ih_enable_interrupts()
59 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_enable_interrupts()
64 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in vega10_ih_enable_interrupts()
69 ih_rb_cntl)) { in vega10_ih_enable_interrupts()
74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_enable_interrupts()
80 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_enable_interrupts()
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Dnavi10_ih.c47 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_enable_interrupts() local
49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in navi10_ih_enable_interrupts()
50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in navi10_ih_enable_interrupts()
51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_enable_interrupts()
64 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_disable_interrupts() local
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in navi10_ih_disable_interrupts()
67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in navi10_ih_disable_interrupts()
68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_disable_interrupts()
76 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in navi10_ih_rb_cntl() argument
80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
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Dtonga_ih.c62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts() local
64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts() local
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
83 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_disable_interrupts()
104 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; in tonga_ih_irq_init() local
126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
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Dcz_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts() local
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts() local
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_disable_interrupts()
109 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cz_ih_irq_init() local
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
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Diceland_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts() local
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts() local
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in iceland_ih_irq_init() local
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
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Dcik_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts() local
66 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK; in cik_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts() local
84 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK; in cik_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_disable_interrupts()
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_ih_irq_init() local
129 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK | in cik_ih_irq_init()
133 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; in cik_ih_irq_init()
139 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_irq_init()
Dsi_ih.c36 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts() local
39 ih_rb_cntl |= IH_RB_ENABLE; in si_ih_enable_interrupts()
41 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts()
47 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts() local
50 ih_rb_cntl &= ~IH_RB_ENABLE; in si_ih_disable_interrupts()
52 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts()
64 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_ih_irq_init() local
76 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE | in si_ih_irq_init()
83 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_irq_init()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dr600.c3596 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts() local
3599 ih_rb_cntl |= IH_RB_ENABLE; in r600_enable_interrupts()
3601 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3607 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts() local
3610 ih_rb_cntl &= ~IH_RB_ENABLE; in r600_disable_interrupts()
3612 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3678 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in r600_irq_init() local
3713 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in r600_irq_init()
3718 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in r600_irq_init()
3724 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
Dsi.c5923 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts() local
5926 ih_rb_cntl |= IH_RB_ENABLE; in si_enable_interrupts()
5928 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5934 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts() local
5937 ih_rb_cntl &= ~IH_RB_ENABLE; in si_disable_interrupts()
5939 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
5982 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_irq_init() local
6014 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in si_irq_init()
6019 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in si_irq_init()
6025 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
Dcik.c6830 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts() local
6833 ih_rb_cntl |= IH_RB_ENABLE; in cik_enable_interrupts()
6835 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6848 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts() local
6851 ih_rb_cntl &= ~IH_RB_ENABLE; in cik_disable_interrupts()
6853 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6954 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_irq_init() local
6986 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in cik_irq_init()
6991 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in cik_irq_init()
6997 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()