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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 28) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dinterrupt.c154 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
329 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
331 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
357 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
363 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
365 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
411 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
469 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
480 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
486 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
Dedid.c377 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
379 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
405 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
407 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
409 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
411 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
Dscheduler.c91 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
92 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
95 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
96 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
97 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
113 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
219 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
221 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
[all …]
Dmmio_context.c220 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
251 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
278 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
533 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
Dgvt.h446 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
450 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
Dhandlers.c167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
526 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { in force_nonpriv_write()
545 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
627 end = i915_mmio_reg_offset(i915_end); in calc_index()
1654 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || in mmio_read_from_hw()
1655 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { in mmio_read_from_hw()
1811 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
3298 if (offset >= i915_mmio_reg_offset(block->offset) && in find_mmio_block()
3299 offset < i915_mmio_reg_offset(block->offset) + block->size) in find_mmio_block()
[all …]
Dcmd_parser.c852 nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); in force_nonpriv_reg_handler()
911 if (offset == i915_mmio_reg_offset(DERRMR) || in cmd_reg_handler()
912 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { in cmd_reg_handler()
982 cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR)) in cmd_handler_lri()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c84 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
110 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
112 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
119 i915_mmio_reg_offset(wa_->reg), in _wa_add()
138 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
139 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
140 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
141 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
638 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
955 name, from, i915_mmio_reg_offset(wa->reg), in wa_verify()
[all …]
Dintel_lrc.c831 i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base)); in virtual_update_register_offsets()
832 regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base)); in virtual_update_register_offsets()
833 regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base)); in virtual_update_register_offsets()
834 regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base)); in virtual_update_register_offsets()
835 regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base)); in virtual_update_register_offsets()
837 regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base)); in virtual_update_register_offsets()
838 regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base)); in virtual_update_register_offsets()
839 regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base)); in virtual_update_register_offsets()
841 i915_mmio_reg_offset(RING_SBBADDR_UDW(base)); in virtual_update_register_offsets()
842 regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base)); in virtual_update_register_offsets()
[all …]
Dselftest_workarounds.c135 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
162 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
428 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
482 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
787 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
828 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
878 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
882 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
906 i915_mmio_reg_offset(reg), a, b); in result_eq()
928 i915_mmio_reg_offset(reg), a); in result_neq()
[all …]
Dintel_mocs.c456 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); in emit_mocs_control_table()
462 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); in emit_mocs_control_table()
515 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); in emit_mocs_l3cc_table()
523 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); in emit_mocs_l3cc_table()
530 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); in emit_mocs_l3cc_table()
Dintel_lrc_reg.h45 (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \
Dintel_ringbuffer.c1538 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
1542 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
1561 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in flush_pd_dir()
1616 *cs++ = i915_mmio_reg_offset( in mi_set_context()
1671 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
1678 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
1712 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_perf.c1649 u32 mmio = i915_mmio_reg_offset(reg); in oa_config_flex_reg()
1661 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio) in oa_config_flex_reg()
1756 *cs++ = i915_mmio_reg_offset(flex->reg); in gen8_load_flex()
3140 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr) in gen8_is_valid_flex_addr()
3148 return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) && in gen7_is_valid_b_counter_addr()
3149 addr <= i915_mmio_reg_offset(OASTARTTRIG8)) || in gen7_is_valid_b_counter_addr()
3150 (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) && in gen7_is_valid_b_counter_addr()
3151 addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) || in gen7_is_valid_b_counter_addr()
3152 (addr >= i915_mmio_reg_offset(OACEC0_0) && in gen7_is_valid_b_counter_addr()
3153 addr <= i915_mmio_reg_offset(OACEC7_1)); in gen7_is_valid_b_counter_addr()
[all …]
Dintel_uncore.h264 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
271 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
413 readl(base + i915_mmio_reg_offset(reg))
415 writel(value, base + i915_mmio_reg_offset(reg))
Dintel_uncore.c940 u32 offset = i915_mmio_reg_offset(*reg); in mmio_reg_cmp()
1101 i915_mmio_reg_offset(reg))) in __unclaimed_reg_debug()
1168 u32 offset = i915_mmio_reg_offset(reg); \
1223 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1276 u32 offset = i915_mmio_reg_offset(reg); \
1315 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1379 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); in __fw_domain_init()
1380 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); in __fw_domain_init()
1829 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
Di915_cmd_parser.c829 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); in check_sorted()
1103 int ret = addr - i915_mmio_reg_offset(table[mid].addr); in __find_reg()
Di915_trace.h883 __entry->reg = i915_mmio_reg_offset(reg);
Di915_irq.c218 i915_mmio_reg_offset(reg), val); in gen3_assert_iir_is_zero()
233 i915_mmio_reg_offset(GEN2_IIR), val); in gen2_assert_iir_is_zero()
/Linux-v5.4/drivers/gpu/drm/i915/gt/uc/
Dintel_uc.c394 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET), in uc_init_wopcm()
397 i915_mmio_reg_offset(GUC_WOPCM_SIZE), in uc_init_wopcm()
Dintel_guc.c43 i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); in intel_guc_init_send_regs()
46 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); in intel_guc_init_send_regs()
/Linux-v5.4/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c78 u32 offset = i915_mmio_reg_offset(*reg); in intel_shadow_table_check()
/Linux-v5.4/drivers/gpu/drm/i915/gem/
Di915_gem_context.c1002 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); in emit_ppgtt_update()
1004 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); in emit_ppgtt_update()
1020 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); in emit_ppgtt_update()
1022 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); in emit_ppgtt_update()
Di915_gem_execbuffer.c1951 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); in i915_reset_gen7_sol_offsets()
/Linux-v5.4/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_context.c599 *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); in rpcs_query_batch()

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