1 /******************************************************************************* 2 * 3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenFabrics.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 * 33 *******************************************************************************/ 34 35 #ifndef I40IW_USER_H 36 #define I40IW_USER_H 37 38 enum i40iw_device_capabilities_const { 39 I40IW_WQE_SIZE = 4, 40 I40IW_CQP_WQE_SIZE = 8, 41 I40IW_CQE_SIZE = 4, 42 I40IW_EXTENDED_CQE_SIZE = 8, 43 I40IW_AEQE_SIZE = 2, 44 I40IW_CEQE_SIZE = 1, 45 I40IW_CQP_CTX_SIZE = 8, 46 I40IW_SHADOW_AREA_SIZE = 8, 47 I40IW_CEQ_MAX_COUNT = 256, 48 I40IW_QUERY_FPM_BUF_SIZE = 128, 49 I40IW_COMMIT_FPM_BUF_SIZE = 128, 50 I40IW_MIN_IW_QP_ID = 1, 51 I40IW_MAX_IW_QP_ID = 262143, 52 I40IW_MIN_CEQID = 0, 53 I40IW_MAX_CEQID = 256, 54 I40IW_MIN_CQID = 0, 55 I40IW_MAX_CQID = 131071, 56 I40IW_MIN_AEQ_ENTRIES = 1, 57 I40IW_MAX_AEQ_ENTRIES = 524287, 58 I40IW_MIN_CEQ_ENTRIES = 1, 59 I40IW_MAX_CEQ_ENTRIES = 131071, 60 I40IW_MIN_CQ_SIZE = 1, 61 I40IW_MAX_CQ_SIZE = 1048575, 62 I40IW_DB_ID_ZERO = 0, 63 I40IW_MAX_WQ_FRAGMENT_COUNT = 3, 64 I40IW_MAX_SGE_RD = 1, 65 I40IW_MAX_OUTBOUND_MESSAGE_SIZE = 2147483647, 66 I40IW_MAX_INBOUND_MESSAGE_SIZE = 2147483647, 67 I40IW_MAX_PUSH_PAGE_COUNT = 4096, 68 I40IW_MAX_PE_ENABLED_VF_COUNT = 32, 69 I40IW_MAX_VF_FPM_ID = 47, 70 I40IW_MAX_VF_PER_PF = 127, 71 I40IW_MAX_SQ_PAYLOAD_SIZE = 2145386496, 72 I40IW_MAX_INLINE_DATA_SIZE = 48, 73 I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE = 48, 74 I40IW_MAX_IRD_SIZE = 64, 75 I40IW_MAX_ORD_SIZE = 127, 76 I40IW_MAX_WQ_ENTRIES = 2048, 77 I40IW_Q2_BUFFER_SIZE = (248 + 100), 78 I40IW_MAX_WQE_SIZE_RQ = 128, 79 I40IW_QP_CTX_SIZE = 248, 80 I40IW_MAX_PDS = 32768 81 }; 82 83 #define i40iw_handle void * 84 #define i40iw_adapter_handle i40iw_handle 85 #define i40iw_qp_handle i40iw_handle 86 #define i40iw_cq_handle i40iw_handle 87 #define i40iw_srq_handle i40iw_handle 88 #define i40iw_pd_id i40iw_handle 89 #define i40iw_stag_handle i40iw_handle 90 #define i40iw_stag_index u32 91 #define i40iw_stag u32 92 #define i40iw_stag_key u8 93 94 #define i40iw_tagged_offset u64 95 #define i40iw_access_privileges u32 96 #define i40iw_physical_fragment u64 97 #define i40iw_address_list u64 * 98 99 #define I40IW_MAX_MR_SIZE 0x10000000000L 100 #define I40IW_MAX_RQ_WQE_SHIFT 2 101 102 struct i40iw_qp_uk; 103 struct i40iw_cq_uk; 104 struct i40iw_srq_uk; 105 struct i40iw_qp_uk_init_info; 106 struct i40iw_cq_uk_init_info; 107 struct i40iw_srq_uk_init_info; 108 109 struct i40iw_sge { 110 i40iw_tagged_offset tag_off; 111 u32 len; 112 i40iw_stag stag; 113 }; 114 115 #define i40iw_sgl struct i40iw_sge * 116 117 struct i40iw_ring { 118 u32 head; 119 u32 tail; 120 u32 size; 121 }; 122 123 struct i40iw_cqe { 124 u64 buf[I40IW_CQE_SIZE]; 125 }; 126 127 struct i40iw_extended_cqe { 128 u64 buf[I40IW_EXTENDED_CQE_SIZE]; 129 }; 130 131 struct i40iw_wqe { 132 u64 buf[I40IW_WQE_SIZE]; 133 }; 134 135 struct i40iw_qp_uk_ops; 136 137 enum i40iw_addressing_type { 138 I40IW_ADDR_TYPE_ZERO_BASED = 0, 139 I40IW_ADDR_TYPE_VA_BASED = 1, 140 }; 141 142 #define I40IW_ACCESS_FLAGS_LOCALREAD 0x01 143 #define I40IW_ACCESS_FLAGS_LOCALWRITE 0x02 144 #define I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04 145 #define I40IW_ACCESS_FLAGS_REMOTEREAD 0x05 146 #define I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08 147 #define I40IW_ACCESS_FLAGS_REMOTEWRITE 0x0a 148 #define I40IW_ACCESS_FLAGS_BIND_WINDOW 0x10 149 #define I40IW_ACCESS_FLAGS_ALL 0x1F 150 151 #define I40IW_OP_TYPE_RDMA_WRITE 0 152 #define I40IW_OP_TYPE_RDMA_READ 1 153 #define I40IW_OP_TYPE_SEND 3 154 #define I40IW_OP_TYPE_SEND_INV 4 155 #define I40IW_OP_TYPE_SEND_SOL 5 156 #define I40IW_OP_TYPE_SEND_SOL_INV 6 157 #define I40IW_OP_TYPE_REC 7 158 #define I40IW_OP_TYPE_BIND_MW 8 159 #define I40IW_OP_TYPE_FAST_REG_NSMR 9 160 #define I40IW_OP_TYPE_INV_STAG 10 161 #define I40IW_OP_TYPE_RDMA_READ_INV_STAG 11 162 #define I40IW_OP_TYPE_NOP 12 163 164 enum i40iw_completion_status { 165 I40IW_COMPL_STATUS_SUCCESS = 0, 166 I40IW_COMPL_STATUS_FLUSHED, 167 I40IW_COMPL_STATUS_INVALID_WQE, 168 I40IW_COMPL_STATUS_QP_CATASTROPHIC, 169 I40IW_COMPL_STATUS_REMOTE_TERMINATION, 170 I40IW_COMPL_STATUS_INVALID_STAG, 171 I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION, 172 I40IW_COMPL_STATUS_ACCESS_VIOLATION, 173 I40IW_COMPL_STATUS_INVALID_PD_ID, 174 I40IW_COMPL_STATUS_WRAP_ERROR, 175 I40IW_COMPL_STATUS_STAG_INVALID_PDID, 176 I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD, 177 I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED, 178 I40IW_COMPL_STATUS_STAG_NOT_INVALID, 179 I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE, 180 I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY, 181 I40IW_COMPL_STATUS_INVALID_FBO, 182 I40IW_COMPL_STATUS_INVALID_LENGTH, 183 I40IW_COMPL_STATUS_INVALID_ACCESS, 184 I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG, 185 I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS, 186 I40IW_COMPL_STATUS_INVALID_REGION, 187 I40IW_COMPL_STATUS_INVALID_WINDOW, 188 I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH 189 }; 190 191 enum i40iw_completion_notify { 192 IW_CQ_COMPL_EVENT = 0, 193 IW_CQ_COMPL_SOLICITED = 1 194 }; 195 196 struct i40iw_post_send { 197 i40iw_sgl sg_list; 198 u32 num_sges; 199 }; 200 201 struct i40iw_post_inline_send { 202 void *data; 203 u32 len; 204 }; 205 206 struct i40iw_rdma_write { 207 i40iw_sgl lo_sg_list; 208 u32 num_lo_sges; 209 struct i40iw_sge rem_addr; 210 }; 211 212 struct i40iw_inline_rdma_write { 213 void *data; 214 u32 len; 215 struct i40iw_sge rem_addr; 216 }; 217 218 struct i40iw_rdma_read { 219 struct i40iw_sge lo_addr; 220 struct i40iw_sge rem_addr; 221 }; 222 223 struct i40iw_bind_window { 224 i40iw_stag mr_stag; 225 u64 bind_length; 226 void *va; 227 enum i40iw_addressing_type addressing_type; 228 bool enable_reads; 229 bool enable_writes; 230 i40iw_stag mw_stag; 231 }; 232 233 struct i40iw_inv_local_stag { 234 i40iw_stag target_stag; 235 }; 236 237 struct i40iw_post_sq_info { 238 u64 wr_id; 239 u8 op_type; 240 bool signaled; 241 bool read_fence; 242 bool local_fence; 243 bool inline_data; 244 bool defer_flag; 245 union { 246 struct i40iw_post_send send; 247 struct i40iw_rdma_write rdma_write; 248 struct i40iw_rdma_read rdma_read; 249 struct i40iw_rdma_read rdma_read_inv; 250 struct i40iw_bind_window bind_window; 251 struct i40iw_inv_local_stag inv_local_stag; 252 struct i40iw_inline_rdma_write inline_rdma_write; 253 struct i40iw_post_inline_send inline_send; 254 } op; 255 }; 256 257 struct i40iw_post_rq_info { 258 u64 wr_id; 259 i40iw_sgl sg_list; 260 u32 num_sges; 261 }; 262 263 struct i40iw_cq_poll_info { 264 u64 wr_id; 265 i40iw_qp_handle qp_handle; 266 u32 bytes_xfered; 267 u32 tcp_seq_num; 268 u32 qp_id; 269 i40iw_stag inv_stag; 270 enum i40iw_completion_status comp_status; 271 u16 major_err; 272 u16 minor_err; 273 u8 op_type; 274 bool stag_invalid_set; 275 bool push_dropped; 276 bool error; 277 bool is_srq; 278 bool solicited_event; 279 }; 280 281 struct i40iw_qp_uk_ops { 282 void (*iw_qp_post_wr)(struct i40iw_qp_uk *); 283 void (*iw_qp_ring_push_db)(struct i40iw_qp_uk *, u32); 284 enum i40iw_status_code (*iw_rdma_write)(struct i40iw_qp_uk *, 285 struct i40iw_post_sq_info *, bool); 286 enum i40iw_status_code (*iw_rdma_read)(struct i40iw_qp_uk *, 287 struct i40iw_post_sq_info *, bool, bool); 288 enum i40iw_status_code (*iw_send)(struct i40iw_qp_uk *, 289 struct i40iw_post_sq_info *, u32, bool); 290 enum i40iw_status_code (*iw_inline_rdma_write)(struct i40iw_qp_uk *, 291 struct i40iw_post_sq_info *, bool); 292 enum i40iw_status_code (*iw_inline_send)(struct i40iw_qp_uk *, 293 struct i40iw_post_sq_info *, u32, bool); 294 enum i40iw_status_code (*iw_stag_local_invalidate)(struct i40iw_qp_uk *, 295 struct i40iw_post_sq_info *, bool); 296 enum i40iw_status_code (*iw_mw_bind)(struct i40iw_qp_uk *, 297 struct i40iw_post_sq_info *, bool); 298 enum i40iw_status_code (*iw_post_receive)(struct i40iw_qp_uk *, 299 struct i40iw_post_rq_info *); 300 enum i40iw_status_code (*iw_post_nop)(struct i40iw_qp_uk *, u64, bool, bool); 301 }; 302 303 struct i40iw_cq_ops { 304 void (*iw_cq_request_notification)(struct i40iw_cq_uk *, 305 enum i40iw_completion_notify); 306 enum i40iw_status_code (*iw_cq_poll_completion)(struct i40iw_cq_uk *, 307 struct i40iw_cq_poll_info *); 308 enum i40iw_status_code (*iw_cq_post_entries)(struct i40iw_cq_uk *, u8 count); 309 void (*iw_cq_clean)(void *, struct i40iw_cq_uk *); 310 }; 311 312 struct i40iw_dev_uk; 313 314 struct i40iw_device_uk_ops { 315 enum i40iw_status_code (*iwarp_cq_uk_init)(struct i40iw_cq_uk *, 316 struct i40iw_cq_uk_init_info *); 317 enum i40iw_status_code (*iwarp_qp_uk_init)(struct i40iw_qp_uk *, 318 struct i40iw_qp_uk_init_info *); 319 }; 320 321 struct i40iw_dev_uk { 322 struct i40iw_device_uk_ops ops_uk; 323 }; 324 325 struct i40iw_sq_uk_wr_trk_info { 326 u64 wrid; 327 u32 wr_len; 328 u8 wqe_size; 329 u8 reserved[3]; 330 }; 331 332 struct i40iw_qp_quanta { 333 u64 elem[I40IW_WQE_SIZE]; 334 }; 335 336 struct i40iw_qp_uk { 337 struct i40iw_qp_quanta *sq_base; 338 struct i40iw_qp_quanta *rq_base; 339 u32 __iomem *wqe_alloc_reg; 340 struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array; 341 u64 *rq_wrid_array; 342 u64 *shadow_area; 343 u32 *push_db; 344 u64 *push_wqe; 345 struct i40iw_ring sq_ring; 346 struct i40iw_ring rq_ring; 347 struct i40iw_ring initial_ring; 348 u32 qp_id; 349 u32 sq_size; 350 u32 rq_size; 351 u32 max_sq_frag_cnt; 352 u32 max_rq_frag_cnt; 353 struct i40iw_qp_uk_ops ops; 354 bool use_srq; 355 u8 swqe_polarity; 356 u8 swqe_polarity_deferred; 357 u8 rwqe_polarity; 358 u8 rq_wqe_size; 359 u8 rq_wqe_size_multiplier; 360 bool first_sq_wq; 361 bool deferred_flag; 362 }; 363 364 struct i40iw_cq_uk { 365 struct i40iw_cqe *cq_base; 366 u32 __iomem *cqe_alloc_reg; 367 u64 *shadow_area; 368 u32 cq_id; 369 u32 cq_size; 370 struct i40iw_ring cq_ring; 371 u8 polarity; 372 bool avoid_mem_cflct; 373 374 struct i40iw_cq_ops ops; 375 }; 376 377 struct i40iw_qp_uk_init_info { 378 struct i40iw_qp_quanta *sq; 379 struct i40iw_qp_quanta *rq; 380 u32 __iomem *wqe_alloc_reg; 381 u64 *shadow_area; 382 struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array; 383 u64 *rq_wrid_array; 384 u32 *push_db; 385 u64 *push_wqe; 386 u32 qp_id; 387 u32 sq_size; 388 u32 rq_size; 389 u32 max_sq_frag_cnt; 390 u32 max_rq_frag_cnt; 391 u32 max_inline_data; 392 int abi_ver; 393 }; 394 395 struct i40iw_cq_uk_init_info { 396 u32 __iomem *cqe_alloc_reg; 397 struct i40iw_cqe *cq_base; 398 u64 *shadow_area; 399 u32 cq_size; 400 u32 cq_id; 401 bool avoid_mem_cflct; 402 }; 403 404 void i40iw_device_init_uk(struct i40iw_dev_uk *dev); 405 406 void i40iw_qp_post_wr(struct i40iw_qp_uk *qp); 407 u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx, 408 u8 wqe_size, 409 u32 total_size, 410 u64 wr_id 411 ); 412 u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx); 413 u64 *i40iw_qp_get_next_srq_wqe(struct i40iw_srq_uk *srq, u32 *wqe_idx); 414 415 enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq, 416 struct i40iw_cq_uk_init_info *info); 417 enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp, 418 struct i40iw_qp_uk_init_info *info); 419 420 void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq); 421 enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp, u64 wr_id, 422 bool signaled, bool post_sq); 423 enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size); 424 enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size); 425 enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size, 426 u8 *wqe_size); 427 void i40iw_get_wqe_shift(u32 sge, u32 inline_data, u8 *shift); 428 enum i40iw_status_code i40iw_get_sqdepth(u32 sq_size, u8 shift, u32 *sqdepth); 429 enum i40iw_status_code i40iw_get_rqdepth(u32 rq_size, u8 shift, u32 *rqdepth); 430 #endif 431
