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Searched refs:hccr (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/scsi/qla2xxx/
Dqla_dbg.c140 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); in qla27xx_dump_mpi_ram()
156 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
157 RD_REG_DWORD(&reg->hccr); in qla27xx_dump_mpi_ram()
163 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
164 RD_REG_DWORD(&reg->hccr); in qla27xx_dump_mpi_ram()
218 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); in qla24xx_dump_ram()
232 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
233 RD_REG_DWORD(&reg->hccr); in qla24xx_dump_ram()
239 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
240 RD_REG_DWORD(&reg->hccr); in qla24xx_dump_ram()
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Dqla_isr.c51 uint16_t hccr; in qla2100_intr_handler() local
70 hccr = RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
71 if (qla2x00_check_reg16_for_disconnect(vha, hccr)) in qla2100_intr_handler()
73 if (hccr & HCCR_RISC_PAUSE) { in qla2100_intr_handler()
82 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC); in qla2100_intr_handler()
83 RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
92 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
93 RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
117 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
118 RD_REG_WORD(&reg->hccr); in qla2100_intr_handler()
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Dqla_init.c2344 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); in qla2300_pci_config()
2346 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()
2367 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC); in qla2300_pci_config()
2369 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()
2532 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); in qla2x00_reset_chip()
2535 if ((RD_REG_WORD(&reg->hccr) & in qla2x00_reset_chip()
2541 RD_REG_WORD(&reg->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2583 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC); in qla2x00_reset_chip()
2584 RD_REG_WORD(&reg->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2587 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_chip()
[all …]
Dqla_dbg.h15 uint16_t hccr; member
39 uint16_t hccr; member
Dqla_mbx.c259 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
261 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
317 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
319 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
413 uint32_t ictrl, host_status, hccr; in qla2x00_mailbox_command() local
424 hccr = RD_REG_DWORD(&reg->isp24.hccr); in qla2x00_mailbox_command()
430 mb[7], host_status, hccr); in qla2x00_mailbox_command()
5282 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); in qla81xx_write_mpi_register()
5296 WRT_REG_DWORD(&reg->hccr, in qla81xx_write_mpi_register()
5298 RD_REG_DWORD(&reg->hccr); in qla81xx_write_mpi_register()
Dqla_sup.c2322 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); in qla2x00_suspend_hba()
2323 RD_REG_WORD(&reg->hccr); in qla2x00_suspend_hba()
2326 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0) in qla2x00_suspend_hba()
Dqla_fw.h1056 uint32_t hccr; /* Host command & control register. */ member
Dqla_def.h765 uint16_t hccr; /* Host command & control register. */ member
Dqla_iocb.c478 RD_REG_DWORD_RELAXED(&ha->iobase->isp24.hccr); in qla2x00_start_iocbs()
Dqla_os.c6956 stat = RD_REG_DWORD(&reg->hccr); in qla2xxx_pci_mmio_enabled()