Searched refs:hart (Results 1 – 5 of 5) sorted by relevance
| /Linux-v5.4/arch/riscv/kernel/ |
| D | smpboot.c | 63 int hart; in setup_smp() local
68 hart = riscv_of_processor_hartid(dn); in setup_smp()
69 if (hart < 0) in setup_smp()
72 if (hart == cpuid_to_hartid_map(0)) { in setup_smp()
79 cpuid, hart); in setup_smp()
83 cpuid_to_hartid_map(cpuid) = hart; in setup_smp()
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| D | cpu.c | 18 u32 hart; in riscv_of_processor_hartid() local
25 if (of_property_read_u32(node, "reg", &hart)) { in riscv_of_processor_hartid()
31 pr_info("CPU with hartid=%d is not available\n", hart); in riscv_of_processor_hartid()
36 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hartid()
40 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); in riscv_of_processor_hartid()
44 return hart; in riscv_of_processor_hartid()
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| /Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.txt | 7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
11 privilege modes per hart; machine mode and supervisor mode.
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| D | riscv,cpu-intc.txt | 7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
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| /Linux-v5.4/drivers/clocksource/ |
| D | Kconfig | 657 This enables the per-hart timer built into all RISC-V systems, which
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