Searched refs:gds (Results 1 – 9 of 9) sorted by relevance
577 struct amdgpu_bo *gds; in amdgpu_cs_parser_bos() local682 gds = p->bo_list->gds_obj; in amdgpu_cs_parser_bos()695 if (gds) { in amdgpu_cs_parser_bos()696 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT; in amdgpu_cs_parser_bos()697 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT; in amdgpu_cs_parser_bos()
575 gds_info.compute_partition_size = adev->gds.gds_size; in amdgpu_info_ioctl()576 gds_info.gds_total_size = adev->gds.gds_size; in amdgpu_info_ioctl()577 gds_info.gws_per_compute_partition = adev->gds.gws_size; in amdgpu_info_ioctl()578 gds_info.oa_per_compute_partition = adev->gds.oa_size; in amdgpu_info_ioctl()
2031 adev->gds.gds_size -= adev->gfx.ngg.gds_reserve_size; in gfx_v9_0_ngg_init()2139 (adev->gds.gds_size + in gfx_v9_0_ngg_en()4232 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()4244 adev->gds.gds_size); in gfx_v9_0_do_edc_gds_workarounds()5070 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v9_0_ring_emit_ib_compute()6388 adev->gds.gds_size = 0x10000; in gfx_v9_0_set_gds_init()6392 adev->gds.gds_size = 0x1000; in gfx_v9_0_set_gds_init()6395 adev->gds.gds_size = 0x10000; in gfx_v9_0_set_gds_init()6402 adev->gds.gds_compute_max_wave_id = 0x7ff; in gfx_v9_0_set_gds_init()6405 adev->gds.gds_compute_max_wave_id = 0x27f; in gfx_v9_0_set_gds_init()[all …]
597 return adev->gds.gws_size; in amdgpu_amdkfd_get_num_gws()
1811 adev->gds.gds_size); in amdgpu_ttm_init()1818 adev->gds.gws_size); in amdgpu_ttm_init()1825 adev->gds.oa_size); in amdgpu_ttm_init()
2310 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v7_0_ring_emit_ib_compute()5099 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()5100 adev->gds.gws_size = 64; in gfx_v7_0_set_gds_init()5101 adev->gds.oa_size = 16; in gfx_v7_0_set_gds_init()5102 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v7_0_set_gds_init()
4470 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v10_0_ring_emit_ib_compute()4718 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, in gfx_v10_0_ring_emit_de_meta()5338 adev->gds.gds_size = 0x10000; in gfx_v10_0_set_gds_init()5339 adev->gds.gds_compute_max_wave_id = 0x4ff; in gfx_v10_0_set_gds_init()5343 adev->gds.gws_size = 64; in gfx_v10_0_set_gds_init()5344 adev->gds.oa_size = 16; in gfx_v10_0_set_gds_init()
946 struct amdgpu_gds gds; member
6168 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); in gfx_v8_0_ring_emit_ib_compute()7080 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v8_0_set_gds_init()7081 adev->gds.gws_size = 64; in gfx_v8_0_set_gds_init()7082 adev->gds.oa_size = 16; in gfx_v8_0_set_gds_init()7083 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v8_0_set_gds_init()
