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Searched refs:gates (Results 1 – 25 of 38) sorted by relevance

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/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dsunxi.txt22 "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs
23 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
27 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
28 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
29 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
30 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
35 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
36 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
37 "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
38 "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
[all …]
Dst,nomadik.txt7 PLLs and clock gates.
34 HCLK nodes: these represent the clock gates on individual
Drenesas,cpg-mstp-clocks.txt3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
4 32 gates.
Dingenic,cgu.txt4 typically includes a variety of PLLs, multiplexers, dividers & gates in order
Dimx8qxp-lpcg.txt4 model to control the clock gates for the peripherals. An LPCG module
Dalphascale,acc.txt4 clock source, setting deviders and clock gates.
Dpistachio-clock.txt103 gates for the external clocks "audio_clk_in" and "enet_clk_in".
/Linux-v5.4/drivers/clk/mvebu/
Dcommon.c193 struct clk **gates; member
211 to_clk_gate(__clk_get_hw(ctrl->gates[n])); in clk_gating_get_src()
213 return ctrl->gates[n]; in clk_gating_get_src()
271 ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates), in mvebu_clk_gating_setup()
273 if (WARN_ON(!ctrl->gates)) in mvebu_clk_gating_setup()
279 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, in mvebu_clk_gating_setup()
282 WARN_ON(IS_ERR(ctrl->gates[n])); in mvebu_clk_gating_setup()
/Linux-v5.4/drivers/clk/sunxi/
DMakefile16 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-simple-gates.o
20 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-bus-gates.o
30 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0-gates.o
34 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun6i-apb0-gates.o
/Linux-v5.4/drivers/clk/
Dclk-oxnas.c30 struct clk_oxnas_gate **gates; member
192 .gates = ox810se_gates,
198 .gates = ox820_gates,
229 data->gates[i]->regmap = regmap; in oxnas_stdclk_probe()
/Linux-v5.4/net/nfc/nci/
Dhci.c705 struct nci_hci_gate *gates) in nci_hci_dev_connect_gates() argument
710 r = nci_hci_connect_gate(ndev, gates->dest_host, in nci_hci_dev_connect_gates()
711 gates->gate, gates->pipe); in nci_hci_dev_connect_gates()
714 gates++; in nci_hci_dev_connect_gates()
738 if (ndev->hci_dev->init_data.gates[0].gate != NCI_HCI_ADMIN_GATE) in nci_hci_dev_session_init()
742 ndev->hci_dev->init_data.gates[0].dest_host, in nci_hci_dev_session_init()
743 ndev->hci_dev->init_data.gates[0].gate, in nci_hci_dev_session_init()
744 ndev->hci_dev->init_data.gates[0].pipe); in nci_hci_dev_session_init()
766 ndev->hci_dev->init_data.gates); in nci_hci_dev_session_init()
/Linux-v5.4/Documentation/devicetree/bindings/i2c/
Di2c-gate.txt4 there are no competing masters to consider for gates and therefore there is
5 no arbitration happening for gates.
/Linux-v5.4/net/nfc/hci/
Dcore.c437 struct nfc_hci_gate *gates) in hci_dev_connect_gates() argument
442 gates->gate, gates->pipe); in hci_dev_connect_gates()
445 gates++; in hci_dev_connect_gates()
456 if (hdev->init_data.gates[0].gate != NFC_HCI_ADMIN_GATE) in hci_dev_session_init()
460 hdev->init_data.gates[0].gate, in hci_dev_session_init()
461 hdev->init_data.gates[0].pipe); in hci_dev_session_init()
486 hdev->init_data.gates); in hci_dev_session_init()
/Linux-v5.4/Documentation/driver-api/nfc/
Dnfc-hci.rst38 support proprietary gates. This is the reason why the driver will pass a list
39 of proprietary gates that must be part of the session. HCI will ensure all
40 those gates have pipes connected when the hci device is set up.
41 In case the chip supports pre-opened gates and pseudo-static pipes, the driver
49 implementation, pipes are totally hidden. The public API only knows gates.
50 This is consistent with the driver need to send commands to proprietary gates
96 mode. This must be implemented only if the hardware uses proprietary gates or a
/Linux-v5.4/security/safesetid/
DKconfig8 SafeSetID is an LSM module that gates the setid family of syscalls to
/Linux-v5.4/Documentation/devicetree/bindings/mfd/
Dsun6i-prcm.txt46 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
/Linux-v5.4/Documentation/driver-api/fpga/
Dintro.rst38 actual hard hardware that gates a bus to a CPU or a soft ("freeze")
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-rt5677.txt33 - nvidia,dmic-clk-en-gpios : The GPIO that gates DMIC clock signal
/Linux-v5.4/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt4 to the PLL itself, this controller also contains bypasses, gates, dividers,
Dda8xx-cfgchip.txt5 gates. This document describes the bindings for those clocks.
/Linux-v5.4/include/net/nfc/
Dhci.h81 struct nfc_hci_gate gates[NFC_HCI_MAX_CUSTOM_GATES]; member
Dnci_core.h172 struct nci_hci_gate gates[NCI_HCI_MAX_CUSTOM_GATES]; member
/Linux-v5.4/Documentation/devicetree/bindings/clock/ti/
Dgate.txt42 gates the clock and clearing the bit ungates the clock.
/Linux-v5.4/drivers/nfc/st-nci/
Dse.c226 ndev->hci_dev->init_data.gates[j].pipe = pipe_info[2]; in st_nci_hci_load_session()
562 memcpy(ndev->hci_dev->init_data.gates, st_nci_gates, in st_nci_hci_network_init()
/Linux-v5.4/drivers/nfc/st21nfca/
Dcore.c182 hdev->init_data.gates[j].pipe = pipe_info[2]; in st21nfca_hci_load_session()
962 memcpy(init_data.gates, st21nfca_gates, sizeof(st21nfca_gates)); in st21nfca_hci_probe()

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