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Searched refs:eq (Results 1 – 25 of 187) sorted by relevance

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/Linux-v5.4/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_eqs.c26 #define GET_EQ_NUM_PAGES(eq, pg_size) \ argument
27 (ALIGN((eq)->q_len * (eq)->elem_size, pg_size) / (pg_size))
29 #define GET_EQ_NUM_ELEMS_IN_PG(eq, pg_size) ((pg_size) / (eq)->elem_size) argument
31 #define EQ_CONS_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
32 HINIC_CSR_AEQ_CONS_IDX_ADDR((eq)->q_id) : \
33 HINIC_CSR_CEQ_CONS_IDX_ADDR((eq)->q_id))
35 #define EQ_PROD_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
36 HINIC_CSR_AEQ_PROD_IDX_ADDR((eq)->q_id) : \
37 HINIC_CSR_CEQ_PROD_IDX_ADDR((eq)->q_id))
39 #define EQ_HI_PHYS_ADDR_REG(eq, pg_num) (((eq)->type == HINIC_AEQ) ? \ argument
[all …]
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/
Deq.c114 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) in mlx5_eq_cq_get() argument
116 struct mlx5_cq_table *table = &eq->cq_table; in mlx5_eq_cq_get()
134 struct mlx5_eq *eq = &eq_comp->core; in mlx5_eq_comp_int() local
139 eqe = next_eqe_sw(eq); in mlx5_eq_comp_int()
153 cq = mlx5_eq_cq_get(eq, cqn); in mlx5_eq_comp_int()
159 mlx5_core_warn(eq->dev, "Completion event for bogus CQ 0x%x\n", cqn); in mlx5_eq_comp_int()
162 ++eq->cons_index; in mlx5_eq_comp_int()
164 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq))); in mlx5_eq_comp_int()
167 eq_update_ci(eq, 1); in mlx5_eq_comp_int()
180 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq_comp *eq) in mlx5_eq_poll_irq_disabled() argument
[all …]
Dcq.c96 struct mlx5_eq_comp *eq; in mlx5_core_create_cq() local
99 eq = mlx5_eqn2comp_eq(dev, eqn); in mlx5_core_create_cq()
100 if (IS_ERR(eq)) in mlx5_core_create_cq()
101 return PTR_ERR(eq); in mlx5_core_create_cq()
112 cq->eq = eq; in mlx5_core_create_cq()
119 cq->tasklet_ctx.priv = &eq->tasklet_ctx; in mlx5_core_create_cq()
123 err = mlx5_eq_add_cq(&eq->core, cq); in mlx5_core_create_cq()
143 mlx5_eq_del_cq(&eq->core, cq); in mlx5_core_create_cq()
162 mlx5_eq_del_cq(&cq->eq->core, cq); in mlx5_core_destroy_cq()
Ddebugfs.c287 static int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, in mlx5_core_eq_query() argument
293 MLX5_SET(query_eq_in, in, eq_number, eq->eqn); in mlx5_core_eq_query()
297 static u64 eq_read_field(struct mlx5_core_dev *dev, struct mlx5_eq *eq, in eq_read_field() argument
310 err = mlx5_core_eq_query(dev, eq, out, outlen); in eq_read_field()
474 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq) in mlx5_debug_eq_add() argument
482 &eq->dbg, eq->eqn, eq_fields, in mlx5_debug_eq_add()
483 ARRAY_SIZE(eq_fields), eq); in mlx5_debug_eq_add()
485 eq->dbg = NULL; in mlx5_debug_eq_add()
490 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq) in mlx5_debug_eq_remove() argument
495 if (eq->dbg) in mlx5_debug_eq_remove()
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/Linux-v5.4/sound/pci/au88x0/
Dau88x0_eq.c56 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftCoefs()
78 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightCoefs()
101 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftStates()
118 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightStates()
164 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetBypassGain()
211 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsTarget()
221 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsTarget()
231 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsCurrent()
241 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsCurrent()
252 eqhw_t *eqhw = &(vortex->eq.this04);
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/Linux-v5.4/drivers/infiniband/hw/mthca/
Dmthca_eq.c173 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in tavor_set_eq_ci() argument
184 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), in tavor_set_eq_ci()
189 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in arbel_set_eq_ci() argument
194 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); in arbel_set_eq_ci()
199 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in set_eq_ci() argument
202 arbel_set_eq_ci(dev, eq, ci); in set_eq_ci()
204 tavor_set_eq_ci(dev, eq, ci); in set_eq_ci()
228 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) in get_eqe() argument
230 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; in get_eqe()
231 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE; in get_eqe()
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/Linux-v5.4/drivers/net/ethernet/mellanox/mlx4/
Deq.c97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) in eq_set_ci() argument
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | in eq_set_ci()
101 eq->doorbell); in eq_set_ci()
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, in get_eqe() argument
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; in get_eqe()
118 …return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % … in get_eqe()
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) in next_eqe_sw() argument
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); in next_eqe_sw()
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; in mlx4_set_eq_affinity_hint() local
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/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/lib/
Deq.h50 static inline struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) in get_eqe() argument
52 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); in get_eqe()
55 static inline struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) in next_eqe_sw() argument
57 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); in next_eqe_sw()
59 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; in next_eqe_sw()
62 static inline void eq_update_ci(struct mlx5_eq *eq, int arm) in eq_update_ci() argument
64 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); in eq_update_ci()
65 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); in eq_update_ci()
77 int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq);
78 void mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq);
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/Linux-v5.4/arch/powerpc/kernel/
Dcpu_setup_6xx.S191 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
192 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
341 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
343 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
344 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
345 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
346 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
347 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
412 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
414 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
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/Linux-v5.4/drivers/pci/controller/
Dpcie-iproc-msi.c64 unsigned int eq; member
130 unsigned int eq) in iproc_msi_read_reg() argument
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
139 int eq, u32 val) in iproc_msi_write_reg() argument
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
160 static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq) in iproc_msi_eq_offset() argument
163 return eq * EQ_MEM_REGION_SIZE; in iproc_msi_eq_offset()
165 return eq * EQ_LEN * sizeof(u32); in iproc_msi_eq_offset()
294 static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) in decode_msi_hwirq() argument
299 offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32); in decode_msi_hwirq()
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/Linux-v5.4/drivers/infiniband/hw/hns/
Dhns_roce_hw_v2.c4933 struct hns_roce_eq *eq, in hns_roce_v2_init_irq_work() argument
4946 irq_work->event_type = eq->event_type; in hns_roce_v2_init_irq_work()
4947 irq_work->sub_type = eq->sub_type; in hns_roce_v2_init_irq_work()
4951 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) in set_eq_cons_index_v2() argument
4953 struct hns_roce_dev *hr_dev = eq->hr_dev; in set_eq_cons_index_v2()
4959 if (eq->type_flag == HNS_ROCE_AEQ) { in set_eq_cons_index_v2()
4962 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? in set_eq_cons_index_v2()
4967 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); in set_eq_cons_index_v2()
4971 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? in set_eq_cons_index_v2()
4978 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); in set_eq_cons_index_v2()
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/Linux-v5.4/include/linux/mlx5/
Deq.h24 mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
25 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
27 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
30 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
31 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
41 static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) in mlx5_eq_update_cc() argument
44 mlx5_eq_update_ci(eq, cc, 0); in mlx5_eq_update_cc()
/Linux-v5.4/drivers/net/ethernet/ibm/ehea/
Dehea_qmr.c236 struct ehea_eq *eq; in ehea_create_eq() local
238 eq = kzalloc(sizeof(*eq), GFP_KERNEL); in ehea_create_eq()
239 if (!eq) in ehea_create_eq()
242 eq->adapter = adapter; in ehea_create_eq()
243 eq->attr.type = type; in ehea_create_eq()
244 eq->attr.max_nr_of_eqes = max_nr_of_eqes; in ehea_create_eq()
245 eq->attr.eqe_gen = eqe_gen; in ehea_create_eq()
246 spin_lock_init(&eq->spinlock); in ehea_create_eq()
249 &eq->attr, &eq->fw_handle); in ehea_create_eq()
255 ret = hw_queue_ctor(&eq->hw_queue, eq->attr.nr_pages, in ehea_create_eq()
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/Linux-v5.4/arch/powerpc/kernel/vdso64/
Dgettimeofday.S62 cror cr0*4+eq,cr0*4+eq,cr1*4+eq
66 cror cr5*4+eq,cr5*4+eq,cr6*4+eq
68 cror cr0*4+eq,cr0*4+eq,cr5*4+eq
186 cror cr0*4+eq,cr0*4+eq,cr1*4+eq
/Linux-v5.4/arch/hexagon/lib/
Dmemset.S29 p0 = cmp.eq(r2, #0)
59 p1 = cmp.eq(r2, #1)
72 p1 = cmp.eq(r2, #2)
85 p1 = cmp.eq(r2, #4)
98 p1 = cmp.eq(r3, #1)
114 p1 = cmp.eq(r2, #8)
125 p1 = cmp.eq(r2, #4)
136 p1 = cmp.eq(r2, #2)
180 p1 = cmp.eq(r2, #1)
196 p0 = cmp.eq(r2, #2)
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/Linux-v5.4/drivers/infiniband/hw/mlx5/
Dodp.c76 struct mlx5_ib_pf_eq *eq; member
1355 struct mlx5_ib_pf_eq *eq = pfault->eq; in mlx5_ib_eqe_pf_action() local
1357 mlx5_ib_pfault(eq->dev, pfault); in mlx5_ib_eqe_pf_action()
1358 mempool_free(pfault, eq->pool); in mlx5_ib_eqe_pf_action()
1361 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq) in mlx5_ib_eq_pf_process() argument
1368 while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) { in mlx5_ib_eq_pf_process()
1369 pfault = mempool_alloc(eq->pool, GFP_ATOMIC); in mlx5_ib_eq_pf_process()
1371 schedule_work(&eq->work); in mlx5_ib_eq_pf_process()
1379 mlx5_ib_dbg(eq->dev, in mlx5_ib_eq_pf_process()
1399 mlx5_ib_dbg(eq->dev, in mlx5_ib_eq_pf_process()
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/Linux-v5.4/drivers/clk/spear/
Dspear1340_clock.c267 {.xscale = 5, .yscale = 122, .eq = 0},
269 {.xscale = 10, .yscale = 204, .eq = 0},
271 {.xscale = 4, .yscale = 25, .eq = 0},
273 {.xscale = 4, .yscale = 21, .eq = 0},
275 {.xscale = 5, .yscale = 18, .eq = 0},
277 {.xscale = 2, .yscale = 6, .eq = 0},
279 {.xscale = 5, .yscale = 12, .eq = 0},
281 {.xscale = 2, .yscale = 4, .eq = 0},
283 {.xscale = 5, .yscale = 18, .eq = 1},
285 {.xscale = 1, .yscale = 3, .eq = 1},
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/Linux-v5.4/arch/arm64/lib/
Dcrc32.S34 csel x3, x3, x4, eq
35 csel w0, w0, w8, eq
39 csel x3, x3, x4, eq
40 csel w0, w0, w8, eq
44 csel w3, w3, w4, eq
45 csel w0, w0, w8, eq
48 csel w0, w0, w8, eq
52 csel w0, w0, w8, eq
Dstrncmp.S86 ccmp endloop, #0, #0, eq
87 b.eq .Lloop_aligned
94 b.eq .Lnot_limit
165 b.eq .Ltinycmp
169 b.eq .Lstart_align /*the last bytes are equal....*/
179 b.eq .Lrecal_offset
194 ccmp endloop, #0, #0, eq /*has_null is ZERO: no null byte*/
216 csinv endloop, diff, xzr, eq
228 ccmp endloop, #0, #0, eq /*has_null is ZERO: no null byte*/
229 b.eq .Lloopcmp_proc
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/Linux-v5.4/arch/ia64/lib/
Dstrlen.S104 cmp.eq p6,p0=r0,r0 // sets p6 to true for cmp.and
119 cmp.eq.and p6,p0=8,val1 // p6 = p6 and val1==8
120 cmp.eq.and p6,p0=8,val2 // p6 = p6 and mask==8
130 cmp.eq p8,p9=8,val1 // p6 = val1 had zero (disambiguate)
137 cmp.eq.and p7,p0=8,val1// val1==8?
174 cmp.eq p0,p6=r0,r0 // nullify first ld8 in loop
184 cmp.eq p6,p0=8,val1 // val1==8 ?
/Linux-v5.4/drivers/misc/habanalabs/
Dirq.c153 struct hl_eq *eq = arg; in hl_irq_handler_eq() local
154 struct hl_device *hdev = eq->hdev; in hl_irq_handler_eq()
159 eq_base = (struct hl_eq_entry *) (uintptr_t) eq->kernel_address; in hl_irq_handler_eq()
163 ((le32_to_cpu(eq_base[eq->ci].hdr.ctl) & in hl_irq_handler_eq()
169 eq_entry = &eq_base[eq->ci]; in hl_irq_handler_eq()
200 eq->ci = hl_eq_inc_ptr(eq->ci); in hl_irq_handler_eq()
202 hdev->asic_funcs->update_eq_ci(hdev, eq->ci); in hl_irq_handler_eq()
/Linux-v5.4/arch/arm64/kernel/
Dentry.S218 b.eq 1f // TTBR0 access already disabled
316 b.eq 3f
584 b.eq el1_da
586 b.eq el1_ia
588 b.eq el1_undef
590 b.eq el1_pc
592 b.eq el1_undef
636 cinc x24, x24, eq // set bit '0'
720 b.eq el0_svc
722 b.eq el0_da
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/Linux-v5.4/arch/hexagon/mm/
Dstrnlen_user.S39 P0 = cmp.eq(mod8,#0);
50 P0 = cmp.eq(tmp1,#0);
57 P0 = cmp.eq(mod8,#0);
71 P0 = vcmpb.eq(dbuf,dcmp);
83 P0 = cmp.eq(tmp1,#32);
/Linux-v5.4/net/dns_resolver/
Ddns_key.c150 const char *eq; in dns_resolver_preparse() local
161 eq = memchr(opt, '=', opt_len); in dns_resolver_preparse()
162 if (eq) { in dns_resolver_preparse()
163 opt_nlen = eq - opt; in dns_resolver_preparse()
164 eq++; in dns_resolver_preparse()
165 memcpy(optval, eq, next_opt - eq); in dns_resolver_preparse()
166 optval[next_opt - eq] = '\0'; in dns_resolver_preparse()
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/en/
Dhealth.c178 int mlx5e_health_channel_eq_recover(struct mlx5_eq_comp *eq, struct mlx5e_channel *channel) in mlx5e_health_channel_eq_recover() argument
183 eq->core.eqn, eq->core.cons_index, eq->core.irqn); in mlx5e_health_channel_eq_recover()
185 eqe_count = mlx5_eq_poll_irq_disabled(eq); in mlx5e_health_channel_eq_recover()
190 eqe_count, eq->core.eqn); in mlx5e_health_channel_eq_recover()

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