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Searched refs:engine_mask (Results 1 – 21 of 21) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_reset.c146 intel_engine_mask_t engine_mask, in i915_do_reset() argument
175 intel_engine_mask_t engine_mask, in g33_do_reset() argument
185 intel_engine_mask_t engine_mask, in g4x_do_reset() argument
222 intel_engine_mask_t engine_mask, in ironlake_do_reset() argument
282 intel_engine_mask_t engine_mask, in gen6_reset_engines() argument
295 if (engine_mask == ALL_ENGINES) { in gen6_reset_engines()
301 for_each_engine_masked(engine, gt->i915, engine_mask, tmp) { in gen6_reset_engines()
406 intel_engine_mask_t engine_mask, in gen11_reset_engines() argument
424 if (engine_mask == ALL_ENGINES) { in gen11_reset_engines()
428 for_each_engine_masked(engine, gt->i915, engine_mask, tmp) { in gen11_reset_engines()
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Dintel_reset.h28 intel_engine_mask_t engine_mask,
48 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
Dintel_gt.h37 intel_engine_mask_t engine_mask);
Dintel_gt.c55 intel_engine_mask_t engine_mask) in intel_gt_clear_error_registers() argument
92 for_each_engine_masked(engine, i915, engine_mask, id) in intel_gt_clear_error_registers()
Dintel_engine_cs.c401 const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask; in intel_engines_init_mmio() local
406 WARN_ON(engine_mask == 0); in intel_engines_init_mmio()
407 WARN_ON(engine_mask & in intel_engines_init_mmio()
429 if (WARN_ON(mask != engine_mask)) in intel_engines_init_mmio()
430 device_info->engine_mask = mask; in intel_engines_init_mmio()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_pci.c158 .engine_mask = BIT(RCS0), \
175 .engine_mask = BIT(RCS0), \
209 .engine_mask = BIT(RCS0), \
294 .engine_mask = BIT(RCS0), \
324 .engine_mask = BIT(RCS0) | BIT(VCS0),
334 .engine_mask = BIT(RCS0) | BIT(VCS0),
342 .engine_mask = BIT(RCS0) | BIT(VCS0), \
369 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
417 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
483 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
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Di915_gpu_error.h203 intel_engine_mask_t engine_mask,
230 u32 engine_mask, in i915_capture_error_state() argument
Dintel_device_info.h153 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ member
Dintel_device_info.c1017 info->engine_mask &= ~BIT(_VCS(i)); in intel_device_info_init_mmio()
1039 info->engine_mask &= ~BIT(_VECS(i)); in intel_device_info_init_mmio()
Di915_drv.h1800 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2067 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2072 (INTEL_INFO(dev_priv)->engine_mask & \
Di915_gpu_error.c1735 intel_engine_mask_t engine_mask, in i915_capture_error_state() argument
1752 dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg)); in i915_capture_error_state()
/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dscheduler.h146 intel_engine_mask_t engine_mask);
151 intel_engine_mask_t engine_mask,
164 intel_engine_mask_t engine_mask);
Dexeclist.c530 intel_engine_mask_t engine_mask) in clean_execlist() argument
537 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { in clean_execlist()
545 intel_engine_mask_t engine_mask) in reset_execlist() argument
551 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) in reset_execlist()
556 intel_engine_mask_t engine_mask) in init_execlist() argument
558 reset_execlist(vgpu, engine_mask); in init_execlist()
Dvgpu.c527 intel_engine_mask_t engine_mask) in intel_gvt_reset_vgpu_locked() argument
531 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; in intel_gvt_reset_vgpu_locked()
535 vgpu->id, dmlr, engine_mask); in intel_gvt_reset_vgpu_locked()
552 if (engine_mask == ALL_ENGINES || dmlr) { in intel_gvt_reset_vgpu_locked()
Dgvt.h144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
488 intel_engine_mask_t engine_mask);
Dscheduler.c881 intel_engine_mask_t engine_mask) in intel_vgpu_clean_workloads() argument
890 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { in intel_vgpu_clean_workloads()
1191 intel_engine_mask_t engine_mask) in intel_vgpu_reset_submission() argument
1198 intel_vgpu_clean_workloads(vgpu, engine_mask); in intel_vgpu_reset_submission()
1199 s->ops->reset(vgpu, engine_mask); in intel_vgpu_reset_submission()
1326 intel_engine_mask_t engine_mask, in intel_vgpu_select_submission_ops() argument
1339 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES)) in intel_vgpu_select_submission_ops()
1343 s->ops->clean(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
1353 ret = ops[interface]->init(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
Dexeclist.h183 intel_engine_mask_t engine_mask);
Dhandlers.c314 intel_engine_mask_t engine_mask = 0; in gdrst_mmio_write() local
322 engine_mask = ALL_ENGINES; in gdrst_mmio_write()
326 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
330 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
334 engine_mask |= BIT(BCS0); in gdrst_mmio_write()
338 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
342 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
344 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask; in gdrst_mmio_write()
348 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); in gdrst_mmio_write()
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/
Dmt76x02_dfs.c616 u32 engine_mask; in mt76x02_dfs_tasklet() local
640 engine_mask = mt76_rr(dev, MT_BBP(DFS, 1)); in mt76x02_dfs_tasklet()
641 if (!(engine_mask & 0xf)) in mt76x02_dfs_tasklet()
647 if (!(engine_mask & (1 << i))) in mt76x02_dfs_tasklet()
/Linux-v5.4/drivers/gpu/drm/i915/selftests/
Dmock_gem_device.c203 mkwrite_device_info(i915)->engine_mask = BIT(0); in mock_gem_device()
/Linux-v5.4/drivers/gpu/drm/i915/gem/
Di915_gem_execbuffer.c2107 return hweight64(INTEL_INFO(i915)->engine_mask & in num_vcs_engines()