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Searched refs:enable_bit (Results 1 – 25 of 49) sorted by relevance

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/Linux-v5.4/drivers/clk/sirf/
Dclk-common.c42 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
50 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
539 .enable_bit = 0,
554 .enable_bit = 8,
569 .enable_bit = 9,
589 .enable_bit = 10,
604 .enable_bit = 11,
641 bit = clk->enable_bit % 32; in std_clk_is_enabled()
642 reg = clk->enable_bit / 32; in std_clk_is_enabled()
654 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); in std_clk_enable()
[all …]
Dclk-atlas6.c22 .enable_bit = 59,
30 .enable_bit = 60,
38 .enable_bit = 61,
53 .enable_bit = 34,
Dclk-prima2.c22 .enable_bit = 59,
30 .enable_bit = 60,
38 .enable_bit = 61,
52 .enable_bit = 34,
/Linux-v5.4/arch/arm/mach-omap1/
Dclock_data.c99 .enable_bit = EN_CKOUT_ARM,
111 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
133 .enable_bit = EN_PERCK,
152 .enable_bit = EN_GPIOCK,
163 .enable_bit = EN_XORPCK,
176 .enable_bit = EN_TIMCK,
189 .enable_bit = EN_WDTCK,
213 .enable_bit = EN_DSPCK,
235 .enable_bit = EN_PERCK,
247 .enable_bit = EN_XORPCK,
[all …]
Dclock.c44 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
333 val &= ~(1 << clk->enable_bit); in omap1_set_uart_rate()
335 val |= (1 << clk->enable_bit); in omap1_set_uart_rate()
462 regval32 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
466 regval16 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
483 regval32 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
487 regval16 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
599 if ((regval32 & (1 << clk->enable_bit)) == 0) in omap1_clk_disable_unused()
/Linux-v5.4/tools/power/cpupower/utils/idle_monitor/
Damd_fam14h_idle.c98 unsigned int *enable_bit, in amd_fam14h_get_pci_info() argument
103 *enable_bit = PCI_NON_PC0_ENABLE_BIT; in amd_fam14h_get_pci_info()
107 *enable_bit = PCI_PC1_ENABLE_BIT; in amd_fam14h_get_pci_info()
111 *enable_bit = PCI_PC6_ENABLE_BIT; in amd_fam14h_get_pci_info()
115 *enable_bit = PCI_NBP1_ENTERED_BIT; in amd_fam14h_get_pci_info()
126 int enable_bit, pci_offset, ret; in amd_fam14h_init() local
129 ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); in amd_fam14h_init()
136 val |= 1 << enable_bit; in amd_fam14h_init()
145 val |= 1 << enable_bit; in amd_fam14h_init()
149 state->name, PCI_MONITOR_ENABLE_REG, enable_bit, in amd_fam14h_init()
[all …]
/Linux-v5.4/drivers/clk/ti/
Dclkt_dflt.c154 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
180 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
230 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
232 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
260 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
262 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
287 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
289 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dinterface.c51 clk_hw->enable_bit = bit_idx; in _register_interface()
74 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
81 enable_bit = val; in _of_ti_interface_clk_setup()
90 enable_bit, ops); in _of_ti_interface_clk_setup()
Dclkt_iclk.c37 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
52 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
75 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dgate.c116 clk_hw->enable_bit = bit_idx; in _register_gate()
141 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
151 enable_bit = val; in _of_ti_gate_clk_setup()
168 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
190 gate->enable_bit = val; in _of_ti_composite_gate_clk_setup()
Dclk-3xxx.c161 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
184 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
185 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
187 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
Dclkctrl.c152 if (!clk->enable_bit) in _omap4_clkctrl_clk_enable()
158 val |= clk->enable_bit; in _omap4_clkctrl_clk_enable()
182 if (!clk->enable_bit) in _omap4_clkctrl_clk_disable()
215 if (val & clk->enable_bit) in _omap4_clkctrl_clk_is_enabled()
317 clk_hw->enable_bit = data->bit; in _ti_clkctrl_setup_gate()
596 hw->enable_bit = MODULEMODE_SWCTRL; in _ti_omap4_clkctrl_setup()
598 hw->enable_bit = MODULEMODE_HWCTRL; in _ti_omap4_clkctrl_setup()
/Linux-v5.4/drivers/clk/
Dclk-max9485.c73 u8 enable_bit; member
115 clk_hw->enable_bit, in max9485_clk_prepare()
116 clk_hw->enable_bit); in max9485_clk_prepare()
123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); in max9485_clk_unprepare()
206 u8 enable_bit; member
213 .enable_bit = MAX9485_MCLK_ENABLE,
231 .enable_bit = MAX9485_CLKOUT1_ENABLE,
240 .enable_bit = MAX9485_CLKOUT2_ENABLE,
322 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; in max9485_i2c_probe()
/Linux-v5.4/drivers/clk/renesas/
Dclk-sh73a0.c92 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
95 switch (enable_bit) { in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
114 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/Linux-v5.4/drivers/regulator/
Dtps6586x-regulator.c59 int enable_bit[2]; member
128 .enable_bit[0] = (ebit0), \
130 .enable_bit[1] = (ebit1),
153 .enable_bit[0] = (ebit0), \
155 .enable_bit[1] = (ebit1),
274 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
285 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
292 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
294 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
300 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx.h16 int enable_bit; member
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dmc13xxx-regulator-core.c36 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
37 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
49 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
63 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c330 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
355 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
380 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x.c82 int enable_bit; member
141 1 << info->enable_bit); in da903x_enable()
150 1 << info->enable_bit); in da903x_disable()
164 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
326 .enable_bit = (ebit), \
348 .enable_bit = (ebit), \
Dmc13892-regulator.c337 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
338 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
362 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
364 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
386 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
/Linux-v5.4/include/linux/
Dsh_clk.h57 unsigned int enable_bit; member
121 .enable_bit = _enable_bit, \
155 .enable_bit = _shift, \
179 .enable_bit = 0, /* unused */ \
192 .enable_bit = 0, /* unused */ \
/Linux-v5.4/drivers/sh/clk/
Dcpg.c56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
71 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
85 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
155 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/Linux-v5.4/arch/arm/mach-omap2/
Dcm2xxx.c137 static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit) in _omap2xxx_apll_enable() argument
141 m = EN_APLL_LOCKED << enable_bit; in _omap2xxx_apll_enable()
160 static void _omap2xxx_apll_disable(u8 enable_bit) in _omap2xxx_apll_disable() argument
165 v &= ~(EN_APLL_LOCKED << enable_bit); in _omap2xxx_apll_disable()
/Linux-v5.4/arch/mips/pci/
Dpci-virtio-guest.c23 __BITFIELD_FIELD(unsigned enable_bit : 1, /* 31 */
51 pca.enable_bit = 1; in pci_virtio_guest_write_config_addr()
/Linux-v5.4/drivers/watchdog/
DiTCO_wdt.c154 u32 enable_bit; in no_reboot_bit() local
159 enable_bit = 0x00000010; in no_reboot_bit()
162 enable_bit = 0x00000020; in no_reboot_bit()
167 enable_bit = 0x00000002; in no_reboot_bit()
171 return enable_bit; in no_reboot_bit()

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