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/Linux-v5.4/drivers/dma/dw-edma/
Ddw-edma-v0-core.c26 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
28 return dw->rg_region.vaddr; in __dw_regs()
31 #define SET(dw, name, value) \ argument
32 writel(value, &(__dw_regs(dw)->name))
34 #define GET(dw, name) \ argument
35 readl(&(__dw_regs(dw)->name))
37 #define SET_RW(dw, dir, name, value) \ argument
40 SET(dw, wr_##name, value); \
42 SET(dw, rd_##name, value); \
45 #define GET_RW(dw, dir, name) \ argument
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Ddw-edma-pcie.c64 struct dw_edma *dw; in dw_edma_pcie_probe() local
114 dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL); in dw_edma_pcie_probe()
115 if (!dw) in dw_edma_pcie_probe()
128 chip->dw = dw; in dw_edma_pcie_probe()
133 dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar]; in dw_edma_pcie_probe()
134 dw->rg_region.vaddr += pdata->rg_off; in dw_edma_pcie_probe()
135 dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start; in dw_edma_pcie_probe()
136 dw->rg_region.paddr += pdata->rg_off; in dw_edma_pcie_probe()
137 dw->rg_region.sz = pdata->rg_sz; in dw_edma_pcie_probe()
139 dw->ll_region.vaddr = pcim_iomap_table(pdev)[pdata->ll_bar]; in dw_edma_pcie_probe()
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Ddw-edma-core.c67 struct dw_edma *dw = chan->chip->dw; in dw_edma_alloc_chunk() local
83 chunk->ll_region.paddr = dw->ll_region.paddr + chan->ll_off; in dw_edma_alloc_chunk()
84 chunk->ll_region.vaddr = dw->ll_region.vaddr + chan->ll_off; in dw_edma_alloc_chunk()
535 struct dw_edma *dw = dw_irq->dw; in dw_edma_interrupt() local
541 total = dw->wr_ch_cnt; in dw_edma_interrupt()
545 total = dw->rd_ch_cnt; in dw_edma_interrupt()
546 off = dw->wr_ch_cnt; in dw_edma_interrupt()
550 val = dw_edma_v0_core_status_done_int(dw, write ? in dw_edma_interrupt()
555 struct dw_edma_chan *chan = &dw->chan[pos + off]; in dw_edma_interrupt()
560 val = dw_edma_v0_core_status_abort_int(dw, write ? in dw_edma_interrupt()
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DMakefile3 obj-$(CONFIG_DW_EDMA) += dw-edma.o
4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
5 dw-edma-objs := dw-edma-core.o \
6 dw-edma-v0-core.o $(dw-edma-y)
7 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
Ddw-edma-v0-debugfs.c42 static struct dw_edma *dw; variable
58 if (dw->mode == EDMA_MODE_LEGACY && in dw_edma_debugfs_u32_get()
65 for (ch = 0; ch < dw->wr_ch_cnt; ch++) in dw_edma_debugfs_u32_get()
71 for (ch = 0; ch < dw->rd_ch_cnt; ch++) in dw_edma_debugfs_u32_get()
83 raw_spin_lock_irqsave(&dw->lock, flags); in dw_edma_debugfs_u32_get()
88 raw_spin_unlock_irqrestore(&dw->lock, flags); in dw_edma_debugfs_u32_get()
177 if (dw->mode == EDMA_MODE_UNROLL) { in dw_edma_debugfs_regs_wr()
183 for (i = 0; i < dw->wr_ch_cnt; i++) { in dw_edma_debugfs_regs_wr()
246 if (dw->mode == EDMA_MODE_UNROLL) { in dw_edma_debugfs_regs_rd()
252 for (i = 0; i < dw->rd_ch_cnt; i++) { in dw_edma_debugfs_regs_rd()
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/Linux-v5.4/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi-ahb-audio.c153 static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_iec958() argument
156 u32 *src = dw->buf_src + offset; in dw_hdmi_reformat_iec958()
157 u32 *dst = dw->buf_dst + offset; in dw_hdmi_reformat_iec958()
158 u32 *end = dw->buf_src + offset + bytes; in dw_hdmi_reformat_iec958()
181 static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw, in dw_hdmi_reformat_s24() argument
184 u32 *src = dw->buf_src + offset; in dw_hdmi_reformat_s24()
185 u32 *dst = dw->buf_dst + offset; in dw_hdmi_reformat_s24()
186 u32 *end = dw->buf_src + offset + bytes; in dw_hdmi_reformat_s24()
192 cs = dw->cs[dw->iec_offset++]; in dw_hdmi_reformat_s24()
193 if (dw->iec_offset >= 192) in dw_hdmi_reformat_s24()
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DMakefile2 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
3 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
4 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
5 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
7 obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
/Linux-v5.4/drivers/dma/dw/
Dcore.c82 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get() local
86 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); in dwc_desc_get()
101 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_put() local
109 dma_pool_free(dw->desc_pool, child, child->txd.phys); in dwc_desc_put()
113 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); in dwc_desc_put()
119 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_initialize() local
124 dw->initialize_chan(dwc); in dwc_initialize()
127 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
128 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
146 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) in dwc_chan_disable() argument
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Didma32.c89 static void idma32_set_device_name(struct dw_dma *dw, int id) in idma32_set_device_name() argument
91 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id); in idma32_set_device_name()
100 static void idma32_fifo_partition(struct dw_dma *dw) in idma32_fifo_partition() argument
113 idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); in idma32_fifo_partition()
114 idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); in idma32_fifo_partition()
117 static void idma32_disable(struct dw_dma *dw) in idma32_disable() argument
119 do_dw_dma_off(dw); in idma32_disable()
120 idma32_fifo_partition(dw); in idma32_disable()
123 static void idma32_enable(struct dw_dma *dw) in idma32_enable() argument
125 idma32_fifo_partition(dw); in idma32_enable()
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Ddw.c16 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dw_dma_initialize_chan() local
23 cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl); in dw_dma_initialize_chan()
92 static void dw_dma_set_device_name(struct dw_dma *dw, int id) in dw_dma_set_device_name() argument
94 snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", id); in dw_dma_set_device_name()
97 static void dw_dma_disable(struct dw_dma *dw) in dw_dma_disable() argument
99 do_dw_dma_off(dw); in dw_dma_disable()
102 static void dw_dma_enable(struct dw_dma *dw) in dw_dma_enable() argument
104 do_dw_dma_on(dw); in dw_dma_enable()
109 struct dw_dma *dw; in dw_dma_probe() local
111 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); in dw_dma_probe()
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Dinternal.h18 void do_dw_dma_on(struct dw_dma *dw);
19 void do_dw_dma_off(struct dw_dma *dw);
27 void dw_dma_acpi_controller_register(struct dw_dma *dw);
28 void dw_dma_acpi_controller_free(struct dw_dma *dw);
30 static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} in dw_dma_acpi_controller_register() argument
31 static inline void dw_dma_acpi_controller_free(struct dw_dma *dw) {} in dw_dma_acpi_controller_free() argument
38 void dw_dma_of_controller_register(struct dw_dma *dw);
39 void dw_dma_of_controller_free(struct dw_dma *dw);
45 static inline void dw_dma_of_controller_register(struct dw_dma *dw) {} in dw_dma_of_controller_register() argument
46 static inline void dw_dma_of_controller_free(struct dw_dma *dw) {} in dw_dma_of_controller_free() argument
Dregs.h333 void (*set_device_name)(struct dw_dma *dw, int id);
334 void (*disable)(struct dw_dma *dw);
335 void (*enable)(struct dw_dma *dw);
341 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) in __dw_regs() argument
343 return dw->regs; in __dw_regs()
346 #define dma_readl(dw, name) \ argument
347 readl(&(__dw_regs(dw)->name))
348 #define dma_writel(dw, name, val) \ argument
349 writel((val), &(__dw_regs(dw)->name))
351 #define idma32_readq(dw, name) \ argument
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Dof.c19 struct dw_dma *dw = ofdma->of_dma_data; in dw_dma_of_xlate() local
21 .dma_dev = dw->dma.dev, in dw_dma_of_xlate()
35 slave.m_master >= dw->pdata->nr_masters || in dw_dma_of_xlate()
36 slave.p_master >= dw->pdata->nr_masters)) in dw_dma_of_xlate()
110 void dw_dma_of_controller_register(struct dw_dma *dw) in dw_dma_of_controller_register() argument
112 struct device *dev = dw->dma.dev; in dw_dma_of_controller_register()
118 ret = of_dma_controller_register(dev->of_node, dw_dma_of_xlate, dw); in dw_dma_of_controller_register()
123 void dw_dma_of_controller_free(struct dw_dma *dw) in dw_dma_of_controller_free() argument
125 struct device *dev = dw->dma.dev; in dw_dma_of_controller_free()
/Linux-v5.4/Documentation/devicetree/bindings/mmc/
Drockchip-dw-mshc.txt6 differences between the core Synopsys dw mshc controller properties described
7 by synopsys-dw-mshc.txt and the properties used by the Rockchip specific
13 - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
15 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288
16 - "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
17 - "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip PX30
18 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
19 - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x
20 - "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
21 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
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Dexynos-dw-mshc.txt6 differences between the core Synopsys dw mshc controller properties described
7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
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Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
30 compatible = "hisilicon,hi4511-dw-mshc";
55 compatible = "hisilicon,hi6220-dw-mshc";
/Linux-v5.4/drivers/dma/dw-axi-dmac/
Ddw-axi-dmac-platform.c179 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { in axi_dma_hw_init()
180 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); in axi_dma_hw_init()
181 axi_chan_disable(&chip->dw->chan[i]); in axi_dma_hw_init()
188 u32 max_width = chan->chip->dw->hdata->m_data_width; in axi_chan_get_xfer_width()
200 struct dw_axi_dma *dw = chan->chip->dw; in axi_desc_get() local
204 desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys); in axi_desc_get()
222 struct dw_axi_dma *dw = chan->chip->dw; in axi_desc_put() local
228 dma_pool_free(dw->desc_pool, child, child->vd.tx.phys); in axi_desc_put()
232 dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys); in axi_desc_put()
275 u32 priority = chan->chip->dw->hdata->priority[chan->id]; in axi_chan_block_xfer_start()
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/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dnavi10_ih.c258 uint32_t dw[8]; in navi10_ih_decode_iv() local
260 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in navi10_ih_decode_iv()
261 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in navi10_ih_decode_iv()
262 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in navi10_ih_decode_iv()
263 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in navi10_ih_decode_iv()
264 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); in navi10_ih_decode_iv()
265 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); in navi10_ih_decode_iv()
266 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); in navi10_ih_decode_iv()
267 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); in navi10_ih_decode_iv()
269 entry->client_id = dw[0] & 0xff; in navi10_ih_decode_iv()
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Dvega10_ih.c441 uint32_t dw[8]; in vega10_ih_decode_iv() local
443 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in vega10_ih_decode_iv()
444 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in vega10_ih_decode_iv()
445 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in vega10_ih_decode_iv()
446 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in vega10_ih_decode_iv()
447 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); in vega10_ih_decode_iv()
448 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); in vega10_ih_decode_iv()
449 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); in vega10_ih_decode_iv()
450 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); in vega10_ih_decode_iv()
452 entry->client_id = dw[0] & 0xff; in vega10_ih_decode_iv()
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/Linux-v5.4/arch/arm/boot/dts/
Dberlin2cd.dtsi175 compatible = "snps,dw-apb-gpio";
181 compatible = "snps,dw-apb-gpio-port";
193 compatible = "snps,dw-apb-gpio";
199 compatible = "snps,dw-apb-gpio-port";
211 compatible = "snps,dw-apb-gpio";
217 compatible = "snps,dw-apb-gpio-port";
229 compatible = "snps,dw-apb-gpio";
235 compatible = "snps,dw-apb-gpio-port";
267 compatible = "snps,dw-apb-ssi";
277 compatible = "snps,dw-wdt";
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Dberlin2.dtsi185 compatible = "snps,dw-apb-gpio";
191 compatible = "snps,dw-apb-gpio-port";
203 compatible = "snps,dw-apb-gpio";
209 compatible = "snps,dw-apb-gpio-port";
221 compatible = "snps,dw-apb-gpio";
227 compatible = "snps,dw-apb-gpio-port";
239 compatible = "snps,dw-apb-gpio";
245 compatible = "snps,dw-apb-gpio-port";
257 compatible = "snps,dw-apb-timer";
266 compatible = "snps,dw-apb-timer";
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/Linux-v5.4/drivers/edac/
Di5100_edac.c486 u32 dw; in i5100_read_log() local
496 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); in i5100_read_log()
498 if (i5100_validlog_redmemvalid(dw)) { in i5100_read_log()
505 if (i5100_validlog_recmemvalid(dw)) { in i5100_read_log()
527 if (i5100_validlog_nrecmemvalid(dw)) { in i5100_read_log()
549 pci_write_config_dword(pdev, I5100_VALIDLOG, dw); in i5100_read_log()
555 u32 dw, dw2; in i5100_check_error() local
557 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); in i5100_check_error()
558 if (i5100_ferr_nf_mem_any(dw)) { in i5100_check_error()
562 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), in i5100_check_error()
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/Linux-v5.4/arch/arm64/boot/dts/synaptics/
Dberlin4ct.dtsi134 compatible = "snps,dw-apb-gpio";
140 compatible = "snps,dw-apb-gpio-port";
152 compatible = "snps,dw-apb-gpio";
158 compatible = "snps,dw-apb-gpio-port";
170 compatible = "snps,dw-apb-gpio";
176 compatible = "snps,dw-apb-gpio-port";
188 compatible = "snps,dw-apb-gpio";
194 compatible = "snps,dw-apb-gpio-port";
206 compatible = "snps,dw-apb-ictl";
233 compatible = "snps,dw-apb-ictl";
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/Linux-v5.4/drivers/scsi/be2iscsi/
Dbe.h167 u32 *dw = (u32 *) ptr + dw_offset; in amap_set() local
168 *dw &= ~(mask << offset); in amap_set()
169 *dw |= (mask & value) << offset; in amap_set()
181 u32 *dw = ptr; in amap_get() local
182 return mask & (*(dw + dw_offset) >> offset); in amap_get()
196 u32 *dw = wrb; in swap_dws() local
199 *dw = cpu_to_le32(*dw); in swap_dws()
200 dw++; in swap_dws()
/Linux-v5.4/arch/x86/crypto/
Dcamellia_glue.c801 u32 dw, tl, tr; in camellia_setup_tail() local
813 dw = (subRL[1] & subRL[9]) >> 32; in camellia_setup_tail()
814 subRL[1] ^= rol32(dw, 1); in camellia_setup_tail()
825 dw = (subRL[1] & subRL[17]) >> 32; in camellia_setup_tail()
826 subRL[1] ^= rol32(dw, 1); in camellia_setup_tail()
844 dw = (subRL[1] & subRL[25]) >> 32; in camellia_setup_tail()
845 subRL[1] ^= rol32(dw, 1); in camellia_setup_tail()
867 dw = (kw4 & subRL[24]) >> 32; in camellia_setup_tail()
868 kw4 ^= rol32(dw, 1); in camellia_setup_tail()
880 dw = (kw4 & subRL[16]) >> 32; in camellia_setup_tail()
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