Searched refs:dst_info (Results 1 – 5 of 5) sorted by relevance
53 l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS; in d40_log_cfg()54 l3 |= d40_width_to_bits(cfg->dst_info.data_width) in d40_log_cfg()89 if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL) in d40_phy_cfg()106 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) { in d40_phy_cfg()108 dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS; in d40_phy_cfg()114 dst |= d40_width_to_bits(cfg->dst_info.data_width) in d40_phy_cfg()125 if (cfg->dst_info.big_endian) in d40_phy_cfg()
90 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,91 .dst_info.psize = STEDMA40_PSIZE_PHY_1,92 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,104 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,105 .dst_info.psize = STEDMA40_PSIZE_LOG_1,106 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,1397 return num_elt * d40c->dma_cfg.dst_info.data_width; in d40_residue()1731 d40_psize_2_burst_size(is_log, conf->dst_info.psize) * in d40_validate_conf()1732 conf->dst_info.data_width) { in d40_validate_conf()2117 struct stedma40_half_channel_info *dst_info = &cfg->dst_info; in d40_prep_sg_log() local[all …]
168 union rga_dst_info dst_info; in rga_cmd_set_trans_info() local190 dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2]; in rga_cmd_set_trans_info()200 dst_info.data.format = ctx->out.fmt->hw_format; in rga_cmd_set_trans_info()201 dst_info.data.swap = ctx->out.fmt->color_swap; in rga_cmd_set_trans_info()221 dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0; in rga_cmd_set_trans_info()224 dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0; in rga_cmd_set_trans_info()349 dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val; in rga_cmd_set_trans_info()
75 dma_cfg->dst_info.data_width = per_data_width; in ux500_pcm_request_chan()78 dma_cfg->dst_info.data_width = mem_data_width; in ux500_pcm_request_chan()
115 struct stedma40_half_channel_info dst_info; member
