Searched refs:dprefclk_khz (Results 1 – 9 of 9) sorted by relevance
322 s->dprefclk_khz = sb.dprefclk; in rn_get_clk_states()538 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()550 clk_mgr->base.dprefclk_khz = s.dprefclk; in rn_clk_mgr_construct()552 if (clk_mgr->base.dprefclk_khz != 600000) { in rn_clk_mgr_construct()553 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()558 if (clk_mgr->base.dprefclk_khz == 0) in rn_clk_mgr_construct()559 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()
116 clk_mgr->base.dprefclk_khz / 1000); in rn_vbios_smu_set_dprefclk()
159 uint32_t dprefclk_khz; member189 …int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where th… member
136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
121 clk_mgr->base.dprefclk_khz / 1000); in rv1_vbios_smu_set_dprefclk()
266 clk_mgr->base.dprefclk_khz = 600000; in rv1_clk_mgr_construct()
178 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); in dce12_get_dp_ref_freq_khz()930 clk_mgr_dce->dprefclk_khz = 600000; in dce120_clk_mgr_create()951 clk_mgr_dce->dprefclk_khz = 625000; in dce121_clk_mgr_create()
441 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn20_clk_mgr_construct()476 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn20_clk_mgr_construct()
159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
