Searched refs:divsel (Results 1 – 3 of 3) sorted by relevance
504 u32 divsel; member511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,1424 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()1578 u32 divsel; in dsiclk_rate() local1581 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()1582 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()1584 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()1585 divsel = dsiclk[n].divsel; in dsiclk_rate()1587 dsiclk[n].divsel = divsel; in dsiclk_rate()[all …]
741 u32 divsel:1; member764 pll_div->divsel = 1; in pll_factors()773 pll_div->divsel = 0; in pll_factors()834 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()839 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
4997 u32 divsel, phaseinc, auxdiv, phasedir = 0; in lpt_program_iclkip() local5015 divsel = (desired_divisor / iclk_pi_range) - 2; in lpt_program_iclkip()5022 if (divsel <= 0x7f) in lpt_program_iclkip()5027 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & in lpt_program_iclkip()5035 divsel, in lpt_program_iclkip()5044 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); in lpt_program_iclkip()5072 u32 divsel, phaseinc, auxdiv; in lpt_get_iclkip() local5090 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> in lpt_get_iclkip()5101 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; in lpt_get_iclkip()
