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Searched refs:divp_shift (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/drivers/clk/tegra/
Dclk-tegra124.c130 .divp_shift = 20,
226 .divp_shift = 20,
300 .divp_shift = 20,
390 .divp_shift = 20,
448 .divp_shift = 24,
487 .divp_shift = 16,
515 .divp_shift = 20,
580 .divp_shift = 20,
697 .divp_shift = 20,
Dclk-tegra114.c144 .divp_shift = 20,
206 .divp_shift = 20,
279 .divp_shift = 20,
326 .divp_shift = 20,
452 .divp_shift = 20,
550 .divp_shift = 24,
579 .divp_shift = 16,
Dclk-tegra210.c1329 #define divp_shift(p) ((p)->params->div_nmp->divp_shift) macro
1333 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1494 .divp_shift = 20,
1616 .divp_shift = 20,
1662 .divp_shift = 20,
1731 .divp_shift = 19,
1810 .divp_shift = 20,
1883 .divp_shift = 24,
1920 .divp_shift = 16,
1953 .divp_shift = 20,
[all …]
Dclk-pll.c254 #define divp_shift(p) (p)->params->div_nmp->divp_shift macro
258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
272 .divp_shift = PLL_BASE_DIVP_SHIFT,
671 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
702 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
969 val |= sel.p << divp_shift(pll); in clk_plle_enable()
1001 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1885 .divp_shift = PLLE_BASE_DIVP_SHIFT,
Dclk.h144 u8 divp_shift; member
Dclk-tegra30.c375 .divp_shift = 20,