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/Linux-v5.4/drivers/clk/tegra/
Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg) >> divider->shift; in clk_frac_div_recalc_rate()
44 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
46 mul = get_mul(divider); in clk_frac_div_recalc_rate()
59 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
66 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
70 mul = get_mul(divider); in clk_frac_div_round_rate()
[all …]
/Linux-v5.4/drivers/clk/qcom/
Dclk-regmap-divider.c21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
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/Linux-v5.4/drivers/clk/ti/
Ddivider.c42 static unsigned int _get_maxdiv(struct clk_omap_divider *divider) in _get_maxdiv() argument
44 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
45 return div_mask(divider); in _get_maxdiv()
46 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _get_maxdiv()
47 return 1 << div_mask(divider); in _get_maxdiv()
48 if (divider->table) in _get_maxdiv()
49 return _get_table_maxdiv(divider->table); in _get_maxdiv()
50 return div_mask(divider) + 1; in _get_maxdiv()
64 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
66 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
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Dclk-dra7-atl.c57 u32 divider; /* Cached divider value */ member
93 cdesc->divider - 1); in atl_clk_enable()
128 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
134 unsigned divider; in atl_clk_round_rate() local
136 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
137 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
138 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
140 return *parent_rate / divider; in atl_clk_round_rate()
147 u32 divider; in atl_clk_set_rate() local
153 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
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/Linux-v5.4/drivers/clk/mvebu/
Ddove-divider.c53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
90 if (divider >= max) in dove_calc_divider()
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/Linux-v5.4/drivers/clk/rockchip/
Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
120 if (divider->lock) in clk_half_divider_set_rate()
121 spin_lock_irqsave(divider->lock, flags); in clk_half_divider_set_rate()
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/Linux-v5.4/drivers/clk/mxs/
Dclk-div.c22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
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/Linux-v5.4/drivers/clk/
Dclk-divider.c28 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
30 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
31 return ioread32be(divider->reg); in clk_div_readl()
33 return readl(divider->reg); in clk_div_readl()
36 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
38 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
39 iowrite32be(val, divider->reg); in clk_div_writel()
41 writel(val, divider->reg); in clk_div_writel()
151 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
154 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
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Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
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/Linux-v5.4/drivers/clk/imx/
Dclk-fixup-div.c24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
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Dclk-composite-8m.c29 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
34 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
35 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
38 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
39 divider->width); in imx8m_clk_composite_divider_recalc_rate()
41 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
45 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
93 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
105 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
107 val = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
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Dclk-divider-gate.c15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_divider_gate()
203 div_gate->divider.width = width; in imx_clk_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_divider_gate()
205 div_gate->divider.table = table; in imx_clk_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_divider_gate()
/Linux-v5.4/drivers/clk/zynqmp/
Ddivider.c62 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
64 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
65 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
82 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
103 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
105 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
106 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
112 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
128 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) in zynqmp_clk_divider_round_rate()
146 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_set_rate() local
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/Linux-v5.4/Documentation/devicetree/bindings/iio/afe/
Dvoltage-divider.txt1 Voltage divider
4 When an io-channel measures the midpoint of a voltage divider, the
6 of the divider. This binding describes the voltage divider in such
24 - compatible : "voltage-divider"
28 - full-ohms : Resistance R + Rout for the full divider. The io-channel
33 voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
36 compatible = "voltage-divider";
/Linux-v5.4/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
78 - ti,latch-bit : latch the divider value to HW, only needed if the register
79 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
85 compatible = "ti,divider-clock";
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/Linux-v5.4/drivers/clk/davinci/
Dpll.c244 struct clk_divider *divider; in davinci_pll_div_register() local
255 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
256 if (!divider) { in davinci_pll_div_register()
261 divider->reg = reg; in davinci_pll_div_register()
262 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
263 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
266 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
271 NULL, NULL, &divider->hw, divider_ops, in davinci_pll_div_register()
281 kfree(divider); in davinci_pll_div_register()
579 struct clk_divider *divider; in davinci_pll_obsclk_register() local
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/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
/Linux-v5.4/drivers/media/i2c/cx25840/
Dcx25840-ir.c145 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
148 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
158 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
160 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
170 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
174 (divider + 1) * rollovers); in clock_divider_to_freq()
215 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
222 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
226 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
235 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
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/Linux-v5.4/drivers/i2c/busses/
Di2c-bcm2835.c87 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
94 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
95 divider++; in clk_bcm2835_i2c_calc_divider()
96 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
97 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
100 return divider; in clk_bcm2835_i2c_calc_divider()
108 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); in clk_bcm2835_i2c_set_rate() local
110 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
113 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); in clk_bcm2835_i2c_set_rate()
120 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
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/Linux-v5.4/drivers/media/pci/cx23885/
Dcx23888-ir.c184 static inline unsigned int clock_divider_to_ns(unsigned int divider) in clock_divider_to_ns() argument
187 return DIV_ROUND_CLOSEST((divider + 1) * 1000, in clock_divider_to_ns()
197 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
199 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
209 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
213 (divider + 1) * rollovers); in clock_divider_to_freq()
254 static u32 clock_divider_to_resolution(u16 divider) in clock_divider_to_resolution() argument
261 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, in clock_divider_to_resolution()
265 static u64 pulse_width_count_to_ns(u16 count, u16 divider) in pulse_width_count_to_ns() argument
274 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ in pulse_width_count_to_ns()
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/Linux-v5.4/arch/arm/boot/dts/
Ddra7xx-clocks.dtsi211 compatible = "ti,divider-clock";
222 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
274 compatible = "ti,divider-clock";
300 compatible = "ti,divider-clock";
344 compatible = "ti,divider-clock";
382 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
433 compatible = "ti,divider-clock";
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Domap54xx-clocks.dtsi117 compatible = "ti,divider-clock";
134 compatible = "ti,divider-clock";
143 compatible = "ti,divider-clock";
160 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
233 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
251 compatible = "ti,divider-clock";
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/regulator/
Dltc3676.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <127000 200000>;
48 lltc,fb-voltage-divider = <301000 200000>;
57 lltc,fb-voltage-divider = <127000 200000>;
66 lltc,fb-voltage-divider = <221000 200000>;
75 lltc,fb-voltage-divider = <487000 200000>;
89 lltc,fb-voltage-divider = <634000 200000>;

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