| /Linux-v5.4/drivers/clk/ |
| D | clk-vt8500.c | 456 int div1, div2; in wm8750_find_pll_bits() local
463 for (div2 = 7; div2 >= 0; div2--) in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
474 *divisor2 = div2; in wm8750_find_pll_bits()
482 *divisor2 = div2; in wm8750_find_pll_bits()
504 int div1, div2; in wm8850_find_pll_bits() local
511 for (div2 = 3; div2 >= 0; div2--) in wm8850_find_pll_bits()
514 ((div1 + 1) * (1 << div2)); in wm8850_find_pll_bits()
522 *divisor2 = div2; in wm8850_find_pll_bits()
530 *divisor2 = div2; in wm8850_find_pll_bits()
[all …]
|
| /Linux-v5.4/drivers/clk/imx/ |
| D | clk-composite-8m.c | 52 int div1, div2; in imx8m_clk_composite_compute_dividers() local
60 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { in imx8m_clk_composite_compute_dividers()
61 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
65 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
|
| /Linux-v5.4/drivers/clk/uniphier/ |
| D | clk-uniphier.h | 114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
116 UNIPHIER_CLK_DIV(parent, div2)
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
120 UNIPHIER_CLK_DIV2(parent, div2, div3)
|
| /Linux-v5.4/arch/microblaze/lib/ |
| D | divsi3.S | 38 blti r5, div2 /* this traps r5 == 0x80000000 */
43 div2: label
56 bri div2 /* div2 */
|
| D | udivsi3.S | 52 blti r5, div2
57 div2: label
70 bri div2 /* div2 */
|
| D | umodsi3.S | 54 blti r5, div2
59 div2: label
72 bri div2 /* div2 */
|
| D | modsi3.S | 43 div2: label
56 bri div2 /* div2 */
|
| /Linux-v5.4/arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7264.c | 63 static int div2[] = { 1, 2, 3, 4, 6, 8, 12 }; variable
66 .divisors = div2,
67 .nr_divisors = ARRAY_SIZE(div2),
|
| D | clock-sh7269.c | 91 static int div2[] = { 1, 2, 0, 4 }; variable
94 .divisors = div2,
95 .nr_divisors = ARRAY_SIZE(div2),
|
| /Linux-v5.4/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7757.c | 48 static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, variable
52 .divisors = div2,
53 .nr_divisors = ARRAY_SIZE(div2),
|
| D | clock-shx3.c | 47 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
51 .divisors = div2,
52 .nr_divisors = ARRAY_SIZE(div2),
|
| D | clock-sh7785.c | 51 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
|
| D | clock-sh7786.c | 53 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
57 .divisors = div2,
58 .nr_divisors = ARRAY_SIZE(div2),
|
| /Linux-v5.4/drivers/media/tuners/ |
| D | mt2131.c | 89 u32 div1, num1, div2, num2; in mt2131_set_params() local
111 div2 = num2 / 8192; in mt2131_set_params()
140 b[6] = div2; in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
|
| D | mt2060.c | 196 u32 div1,num1,div2,num2; in mt2060_set_params() local
233 div2 = num2 / 8192; in mt2060_set_params()
252 b[5] = ((num2 >>12) & 1) | (div2 << 1); in mt2060_set_params()
256 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); in mt2060_set_params()
|
| /Linux-v5.4/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 164 clock-output-names = "pll0", "pll0-div2";
172 clock-output-names = "pll1", "pll1-div2";
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
198 clock-output-names = "platform-pll", "platform-pll-div2";
|
| /Linux-v5.4/drivers/spi/ |
| D | spi-omap-uwire.c | 318 int div2; in uwire_setup_transfer() local
375 div2 = (rate / div1 + hz - 1) / hz; in uwire_setup_transfer()
376 if (div2 <= 8) in uwire_setup_transfer()
394 switch (div2) { in uwire_setup_transfer()
|
| /Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | sorgf119.c | 125 u32 div2 = sor->asy.link == 3; in gf119_sor_clock() local
130 div2 = 1; in gf119_sor_clock()
132 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1); in gf119_sor_clock()
|
| /Linux-v5.4/sound/soc/codecs/ |
| D | wm8978.c | 403 u8 div2; member
417 pll_div->div2 = 1; in pll_factors()
420 pll_div->div2 = 0; in pll_factors()
539 __func__, pll_div.n, pll_div.k, pll_div.div2); in wm8978_configure_pll()
544 snd_soc_component_write(component, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); in wm8978_configure_pll()
|
| D | wm8983.c | 744 u32 div2:1; member
756 pll_div->div2 = 0; in pll_factors()
760 pll_div->div2 = 1; in pll_factors()
809 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) in wm8983_set_pll()
|
| D | wm8990.c | 884 u32 div2; member
903 pll_div->div2 = 1; in pll_factors()
906 pll_div->div2 = 0; in pll_factors()
949 (pll_div.div2?WM8990_PRESCALE:0)); in wm8990_set_dai_pll()
|
| D | wm8985.c | 841 u32 div2:1; member
853 pll_div->div2 = 0; in pll_factors()
857 pll_div->div2 = 1; in pll_factors()
902 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) in wm8985_set_pll()
|
| /Linux-v5.4/arch/mips/alchemy/common/ |
| D | clock.c | 372 long div1, div2; in alchemy_calc_div() local
383 div2 = (div1 / scale) - 1; /* value to write to register */ in alchemy_calc_div()
385 if (div2 > maxdiv) in alchemy_calc_div()
386 div2 = maxdiv; in alchemy_calc_div()
388 *rv = div2; in alchemy_calc_div()
390 div1 = ((div2 + 1) * scale); in alchemy_calc_div()
|
| /Linux-v5.4/drivers/staging/comedi/drivers/ |
| D | adl_pci9118.c | 533 unsigned int *div1, unsigned int *div2, in pci9118_calc_divisors() argument
540 *div2 = *tim1 / pacer->osc_base; /* scan timer */ in pci9118_calc_divisors()
541 *div2 = *div2 / *div1; /* major timer is c1*c2 */ in pci9118_calc_divisors()
542 if (*div2 < chans) in pci9118_calc_divisors()
543 *div2 = chans; in pci9118_calc_divisors()
549 if (*div2 < (chans + 2)) in pci9118_calc_divisors()
550 *div2 = chans + 2; in pci9118_calc_divisors()
553 *tim1 = *div1 * *div2 * pacer->osc_base; in pci9118_calc_divisors()
|
| /Linux-v5.4/drivers/video/fbdev/ |
| D | cyber2000fb.c | 666 u_int div2, t_div1, best_div1, best_mult; in cyber2000fb_decode_clock() local
675 for (div2 = 0; div2 < 4; div2++) { in cyber2000fb_decode_clock()
678 new_pll = pll_ps / cfb->divisors[div2]; in cyber2000fb_decode_clock()
685 if (div2 == 4) in cyber2000fb_decode_clock()
741 hw->clock_div = div2 << 6 | (best_div1 - 1); in cyber2000fb_decode_clock()
|
