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Searched refs:disp_int (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Drs600.c720 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
721 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
725 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
729 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
734 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
740 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
780 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
785 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
792 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
801 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
[all …]
Dr600.c3920 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3931 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3948 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3950 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3952 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3963 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
4138 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4148 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
[all …]
Devergreen.c4616 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_ack() local
4620 disp_int[i] = RREG32(evergreen_disp_int_status[i]); in evergreen_irq_ack()
4635 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) in evergreen_irq_ack()
4638 if (disp_int[j] & LB_D1_VLINE_INTERRUPT) in evergreen_irq_ack()
4645 if (disp_int[i] & DC_HPD1_INTERRUPT) in evergreen_irq_ack()
4650 if (disp_int[i] & DC_HPD1_RX_INTERRUPT) in evergreen_irq_ack()
4703 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_process() local
4775 if (!(disp_int[crtc_idx] & mask)) { in evergreen_irq_process()
4780 disp_int[crtc_idx] &= ~mask; in evergreen_irq_process()
4813 if (!(disp_int[hpd_idx] & mask)) in evergreen_irq_process()
[all …]
Dsi.c6148 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_ack() local
6155 disp_int[i] = RREG32(si_disp_int_status[i]); in si_irq_ack()
6169 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) in si_irq_ack()
6172 if (disp_int[j] & LB_D1_VLINE_INTERRUPT) in si_irq_ack()
6179 if (disp_int[i] & DC_HPD1_INTERRUPT) in si_irq_ack()
6184 if (disp_int[i] & DC_HPD1_RX_INTERRUPT) in si_irq_ack()
6247 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_process() local
6318 if (!(disp_int[crtc_idx] & mask)) { in si_irq_process()
6323 disp_int[crtc_idx] &= ~mask; in si_irq_process()
6356 if (!(disp_int[hpd_idx] & mask)) in si_irq_process()
[all …]
Dcik.c7304 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7335 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) in cik_irq_ack()
7337 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) in cik_irq_ack()
7378 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { in cik_irq_ack()
7408 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { in cik_irq_ack()
7599 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)) in cik_irq_process()
7609 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in cik_irq_process()
7614 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)) in cik_irq_process()
7617 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; in cik_irq_process()
7789 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT)) in cik_irq_process()
[all …]
Dradeon.h749 u32 disp_int; member
754 u32 disp_int; member
764 u32 disp_int[6]; member
770 u32 disp_int; member
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c3025 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq() local
3031 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()
3042 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
3137 uint32_t disp_int, mask, tmp; in dce_v8_0_hpd_irq() local
3146 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3149 if (disp_int & mask) { in dce_v8_0_hpd_irq()
Ddce_v6_0.c2933 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq() local
2939 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()
2950 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
3045 uint32_t disp_int, mask, tmp; in dce_v6_0_hpd_irq() local
3054 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3057 if (disp_int & mask) { in dce_v6_0_hpd_irq()
Ddce_v10_0.c3214 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq() local
3219 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3231 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3251 uint32_t disp_int, mask; in dce_v10_0_hpd_irq() local
3260 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3263 if (disp_int & mask) { in dce_v10_0_hpd_irq()
Ddce_v11_0.c3340 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq() local
3346 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()
3358 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()
3378 uint32_t disp_int, mask; in dce_v11_0_hpd_irq() local
3387 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3390 if (disp_int & mask) { in dce_v11_0_hpd_irq()