Searched refs:default_ctrl (Results 1 – 4 of 4) sorted by relevance
42 if (bw < r->membw.min_bw || bw > r->default_ctrl) { in bw_validate_amd()44 r->membw.min_bw, r->default_ctrl); in bw_validate_amd()96 if ((bw < r->membw.min_bw || bw > r->default_ctrl) && in bw_validate()99 r->membw.min_bw, r->default_ctrl); in bw_validate()143 if (val == 0 || val > r->default_ctrl) { in cbm_validate_intel()181 if (val > r->default_ctrl) { in cbm_validate_amd()
214 r->default_ctrl = max_cbm; in cache_alloc_hsw_probe()262 r->default_ctrl = MAX_MBA_BW; in __get_mem_config_intel()287 r->default_ctrl = MAX_MBA_BW_AMD; in __rdt_get_mem_config_amd()312 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; in rdt_get_cache_alloc_cfg()313 r->cache.shareable_bits = ebx & r->default_ctrl; in rdt_get_cache_alloc_cfg()326 r->default_ctrl = r_l->default_ctrl; in rdt_get_cdp_config()382 return r->default_ctrl; in delay_bw_map()478 *dc = r->default_ctrl; in setup_default_ctrlval()
446 u32 default_ctrl; member
757 seq_printf(seq, "%x\n", r->default_ctrl); in rdt_default_ctrl_show()2134 d->ctrl_val[i] = r->default_ctrl; in reset_all_ctrls()2605 d->new_ctrl = is_mba_sc(r) ? MBA_MAX_MBPS : r->default_ctrl; in rdtgroup_init_mba()
