Searched refs:dct_sel_lo (Results 1 – 2 of 2) sorted by relevance
197 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))198 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))200 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))202 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))203 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))372 u32 dct_sel_lo; /* DRAM Controller Select Low */ member442 ((pvt->dct_sel_lo >> 6) & 0x3); in dct_sel_interleave_addr()444 return ((pvt)->dct_sel_lo >> 6) & 0x3; in dct_sel_interleave_addr()540 return (pvt)->dct_sel_lo & 0xFFFFF800; in dct_sel_baseaddr()
1646 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()1648 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()1708 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
