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Searched refs:dbi_base (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.4/drivers/pci/controller/dwc/
Dpcie-spear13xx.c92 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); in spear13xx_pcie_establish_link()
94 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); in spear13xx_pcie_establish_link()
96 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A); in spear13xx_pcie_establish_link()
97 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); in spear13xx_pcie_establish_link()
104 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, in spear13xx_pcie_establish_link()
109 dw_pcie_write(pci->dbi_base + exp_cap_off + in spear13xx_pcie_establish_link()
113 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, in spear13xx_pcie_establish_link()
118 dw_pcie_write(pci->dbi_base + exp_cap_off + in spear13xx_pcie_establish_link()
234 struct resource *dbi_base; in spear13xx_pcie_probe() local
273 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in spear13xx_pcie_probe()
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Dpci-layerscape.c61 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_is_bridge()
72 iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_clear_multifunction()
81 val = ioread32(pci->dbi_base + PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
83 iowrite32(val, pci->dbi_base + PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
131 iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); in ls_pcie_fix_error_response()
298 struct resource *dbi_base; in ls_pcie_probe() local
316 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_probe()
317 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); in ls_pcie_probe()
318 if (IS_ERR(pci->dbi_base)) in ls_pcie_probe()
319 return PTR_ERR(pci->dbi_base); in ls_pcie_probe()
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Dpci-layerscape-ep.c122 struct resource *dbi_base; in ls_pcie_ep_probe() local
133 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_ep_probe()
134 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); in ls_pcie_ep_probe()
135 if (IS_ERR(pci->dbi_base)) in ls_pcie_ep_probe()
136 return PTR_ERR(pci->dbi_base); in ls_pcie_ep_probe()
138 pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET; in ls_pcie_ep_probe()
Dpcie-al.c19 void __iomem *dbi_base; member
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus() local
37 return dbi_base + where; in al_pcie_map_bus()
69 al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res); in al_pcie_init()
70 if (IS_ERR(al_pcie->dbi_base)) { in al_pcie_init()
71 long err = PTR_ERR(al_pcie->dbi_base); in al_pcie_init()
410 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); in al_pcie_probe()
411 if (IS_ERR(pci->dbi_base)) { in al_pcie_probe()
413 return PTR_ERR(pci->dbi_base); in al_pcie_probe()
Dpci-dra7xx.c153 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, in dra7xx_pcie_establish_link()
158 dw_pcie_write(pci->dbi_base + exp_cap_off + in dra7xx_pcie_establish_link()
162 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, in dra7xx_pcie_establish_link()
167 dw_pcie_write(pci->dbi_base + exp_cap_off + in dra7xx_pcie_establish_link()
430 pci->dbi_base = devm_ioremap_resource(dev, res); in dra7xx_add_pcie_ep()
431 if (IS_ERR(pci->dbi_base)) in dra7xx_add_pcie_ep()
432 return PTR_ERR(pci->dbi_base); in dra7xx_add_pcie_ep()
483 pci->dbi_base = devm_ioremap_resource(dev, res); in dra7xx_add_pcie_port()
484 if (IS_ERR(pci->dbi_base)) in dra7xx_add_pcie_port()
485 return PTR_ERR(pci->dbi_base); in dra7xx_add_pcie_port()
Dpcie-designware.c143 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
145 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
158 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
162 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
472 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); in dw_pcie_link_up()
500 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_setup()
Dpcie-designware-plat.c212 pci->dbi_base = devm_ioremap_resource(dev, res); in dw_plat_pcie_probe()
213 if (IS_ERR(pci->dbi_base)) in dw_plat_pcie_probe()
214 return PTR_ERR(pci->dbi_base); in dw_plat_pcie_probe()
Dpcie-histb.c132 ret = dw_pcie_read(pci->dbi_base + where, size, val); in histb_pcie_rd_own_conf()
145 ret = dw_pcie_write(pci->dbi_base + where, size, val); in histb_pcie_wr_own_conf()
335 pci->dbi_base = devm_ioremap_resource(dev, res); in histb_pcie_probe()
336 if (IS_ERR(pci->dbi_base)) { in histb_pcie_probe()
338 return PTR_ERR(pci->dbi_base); in histb_pcie_probe()
Dpcie-artpec6.c490 struct resource *dbi_base; in artpec6_pcie_probe() local
521 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in artpec6_pcie_probe()
522 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); in artpec6_pcie_probe()
523 if (IS_ERR(pci->dbi_base)) in artpec6_pcie_probe()
524 return PTR_ERR(pci->dbi_base); in artpec6_pcie_probe()
Dpcie-qcom.c357 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_init_2_1_0()
359 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_init_2_1_0()
1039 writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); in qcom_pcie_init_2_3_3()
1040 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); in qcom_pcie_init_2_3_3()
1041 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); in qcom_pcie_init_2_3_3()
1043 val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); in qcom_pcie_init_2_3_3()
1045 writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); in qcom_pcie_init_2_3_3()
1047 writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + in qcom_pcie_init_2_3_3()
1073 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1220 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); in qcom_pcie_probe()
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Dpcie-kirin.c166 kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); in kirin_pcie_get_resource()
167 if (IS_ERR(kirin_pcie->pci->dbi_base)) in kirin_pcie_get_resource()
168 return PTR_ERR(kirin_pcie->pci->dbi_base); in kirin_pcie_get_resource()
346 ret = dw_pcie_read(pci->dbi_base + where, size, val); in kirin_pcie_rd_own_conf()
360 ret = dw_pcie_write(pci->dbi_base + where, size, val); in kirin_pcie_wr_own_conf()
Dpcie-armada8k.c318 pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); in armada8k_pcie_probe()
319 if (IS_ERR(pci->dbi_base)) { in armada8k_pcie_probe()
321 ret = PTR_ERR(pci->dbi_base); in armada8k_pcie_probe()
Dpcie-hisi.c293 pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg); in hisi_pcie_probe()
294 if (IS_ERR(pci->dbi_base)) in hisi_pcie_probe()
295 return PTR_ERR(pci->dbi_base); in hisi_pcie_probe()
Dpci-imx6.c1017 struct resource *dbi_base; in imx6_pcie_probe() local
1053 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); in imx6_pcie_probe()
1054 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); in imx6_pcie_probe()
1055 if (IS_ERR(pci->dbi_base)) in imx6_pcie_probe()
1056 return PTR_ERR(pci->dbi_base); in imx6_pcie_probe()
1112 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) in imx6_pcie_probe()
Dpcie-tegra194.c439 return dw_pcie_read(pci->dbi_base + where, size, val); in tegra_pcie_dw_rd_own_conf()
456 return dw_pcie_write(pci->dbi_base + where, size, val); in tegra_pcie_dw_wr_own_conf()
682 dw_pcie_read(pci->dbi_base + CAP_SPCIE_CAP_OFF in config_gen3_gen4_eq_presets()
689 dw_pcie_write(pci->dbi_base + CAP_SPCIE_CAP_OFF in config_gen3_gen4_eq_presets()
695 dw_pcie_read(pci->dbi_base + offset + i, 1, &val); in config_gen3_gen4_eq_presets()
701 dw_pcie_write(pci->dbi_base + offset + i, 1, val); in config_gen3_gen4_eq_presets()
1530 pci->dbi_base = devm_ioremap_resource(dev, dbi_res); in tegra_pcie_dw_probe()
1531 if (IS_ERR(pci->dbi_base)) in tegra_pcie_dw_probe()
1532 return PTR_ERR(pci->dbi_base); in tegra_pcie_dw_probe()
1535 pci->dbi_base2 = pci->dbi_base + 0x1000; in tegra_pcie_dw_probe()
Dpcie-designware-host.c32 return dw_pcie_read(pci->dbi_base + where, size, val); in dw_pcie_rd_own_conf()
44 return dw_pcie_write(pci->dbi_base + where, size, val); in dw_pcie_wr_own_conf()
390 if (!pci->dbi_base) { in dw_pcie_host_init()
391 pci->dbi_base = devm_pci_remap_cfgspace(dev, in dw_pcie_host_init()
394 if (!pci->dbi_base) { in dw_pcie_host_init()
Dpcie-uniphier.c419 priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res); in uniphier_pcie_probe()
420 if (IS_ERR(priv->pci.dbi_base)) in uniphier_pcie_probe()
421 return PTR_ERR(priv->pci.dbi_base); in uniphier_pcie_probe()
Dpci-meson.c404 ret = dw_pcie_read(pci->dbi_base + where, size, val); in meson_pcie_rd_own_conf()
430 return dw_pcie_write(pci->dbi_base + where, size, val); in meson_pcie_wr_own_conf()
510 pci->dbi_base = mp->mem_res.elbi_base; in meson_add_pcie_port()
Dpci-exynos.c349 ret = dw_pcie_read(pci->dbi_base + where, size, val); in exynos_pcie_rd_own_conf()
362 ret = dw_pcie_write(pci->dbi_base + where, size, val); in exynos_pcie_wr_own_conf()
Dpcie-designware.h246 void __iomem *dbi_base; member
Dpci-keystone.c823 pci->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
1243 pci->dbi_base = base; in ks_pcie_probe()
Dpcie-designware-ep.c509 if (!pci->dbi_base || !pci->dbi_base2) { in dw_pcie_ep_init()