| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_color.c | 102 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) in crtc_state_is_legacy_gamma() argument
104 return !crtc_state->base.degamma_lut && in crtc_state_is_legacy_gamma()
105 !crtc_state->base.ctm && in crtc_state_is_legacy_gamma()
106 crtc_state->base.gamma_lut && in crtc_state_is_legacy_gamma()
107 lut_is_legacy(crtc_state->base.gamma_lut); in crtc_state_is_legacy_gamma()
190 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) in ilk_csc_limited_range() argument
192 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); in ilk_csc_limited_range()
198 return crtc_state->limited_color_range && in ilk_csc_limited_range()
203 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, in ilk_csc_convert_ctm() argument
206 const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; in ilk_csc_convert_ctm()
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| D | intel_atomic.c | 129 struct drm_crtc_state *crtc_state; in intel_digital_connector_atomic_check() local
136 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); in intel_digital_connector_atomic_check()
150 crtc_state->mode_changed = true; in intel_digital_connector_atomic_check()
189 struct intel_crtc_state *crtc_state; in intel_crtc_duplicate_state() local
191 crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
192 if (!crtc_state) in intel_crtc_duplicate_state()
195 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); in intel_crtc_duplicate_state()
197 crtc_state->update_pipe = false; in intel_crtc_duplicate_state()
198 crtc_state->disable_lp_wm = false; in intel_crtc_duplicate_state()
199 crtc_state->disable_cxsr = false; in intel_crtc_duplicate_state()
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| D | intel_vdsc.c | 460 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) in intel_dsc_power_domain() argument
462 struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev); in intel_dsc_power_domain()
463 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_power_domain()
484 const struct intel_crtc_state *crtc_state) in intel_configure_pps_for_dsc_encoder() argument
486 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in intel_configure_pps_for_dsc_encoder()
488 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; in intel_configure_pps_for_dsc_encoder()
490 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_configure_pps_for_dsc_encoder()
494 u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; in intel_configure_pps_for_dsc_encoder()
517 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
521 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
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| D | intel_ddi.h | 26 const struct intel_crtc_state *crtc_state);
29 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
30 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
31 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
32 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
33 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
37 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
40 struct intel_crtc_state *crtc_state);
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| D | intel_hdmi.c | 205 const struct intel_crtc_state *crtc_state, in g4x_write_infoframe() argument
240 const struct intel_crtc_state *crtc_state, in g4x_read_infoframe() argument
276 const struct intel_crtc_state *crtc_state, in ibx_write_infoframe() argument
282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in ibx_write_infoframe()
313 const struct intel_crtc_state *crtc_state, in ibx_read_infoframe() argument
318 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in ibx_read_infoframe()
353 const struct intel_crtc_state *crtc_state, in cpt_write_infoframe() argument
359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in cpt_write_infoframe()
393 const struct intel_crtc_state *crtc_state, in cpt_read_infoframe() argument
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in cpt_read_infoframe()
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| D | intel_dpll_mgr.c | 137 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state) in intel_prepare_shared_dpll() argument
139 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in intel_prepare_shared_dpll()
141 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_prepare_shared_dpll()
164 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) in intel_enable_shared_dpll() argument
166 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in intel_enable_shared_dpll()
168 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
209 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) in intel_disable_shared_dpll() argument
211 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in intel_disable_shared_dpll()
213 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
450 struct intel_crtc_state *crtc_state = in ibx_get_dpll() local
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| D | intel_ddi.c | 920 const struct intel_crtc_state *crtc_state) in intel_prepare_dp_ddi_buffers() argument
928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) in intel_prepare_dp_ddi_buffers()
931 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) in intel_prepare_dp_ddi_buffers()
1020 const struct intel_crtc_state *crtc_state) in icl_pll_to_ddi_clk_sel() argument
1022 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1023 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
1066 const struct intel_crtc_state *crtc_state) in hsw_fdi_link_train() argument
1075 intel_prepare_dp_ddi_buffers(encoder, crtc_state); in hsw_fdi_link_train()
1092 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in hsw_fdi_link_train()
1102 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); in hsw_fdi_link_train()
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| D | intel_display.c | 125 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
126 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
127 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
130 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
131 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
132 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
133 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
141 struct intel_crtc_state *crtc_state);
142 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
144 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
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| D | intel_atomic_plane.c | 118 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, in intel_plane_data_rate() argument
138 return cpp * crtc_state->pixel_rate; in intel_plane_data_rate()
232 struct intel_crtc_state *crtc_state = in skl_next_plane_to_commit() local
248 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
251 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], in skl_next_plane_to_commit()
257 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
258 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_next_plane_to_commit()
270 const struct intel_crtc_state *crtc_state, in intel_update_plane() argument
273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in intel_update_plane()
276 plane->update_plane(plane, crtc_state, plane_state); in intel_update_plane()
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| D | intel_atomic_plane.h | 21 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
24 const struct intel_crtc_state *crtc_state,
27 const struct intel_crtc_state *crtc_state,
30 const struct intel_crtc_state *crtc_state);
41 struct intel_crtc_state *crtc_state,
45 struct intel_crtc_state *crtc_state,
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| D | intel_psr.c | 76 const struct intel_crtc_state *crtc_state) in intel_psr2_enabled() argument
79 WARN_ON(crtc_state->dsc_params.compression_enable && in intel_psr2_enabled()
80 crtc_state->has_psr2); in intel_psr2_enabled()
87 return crtc_state->has_psr2; in intel_psr2_enabled()
342 const struct intel_crtc_state *crtc_state) in intel_psr_setup_vsc() argument
370 crtc_state, in intel_psr_setup_vsc()
537 struct intel_crtc_state *crtc_state) in intel_psr2_config_valid() argument
540 int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
541 int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
552 if (crtc_state->dsc_params.compression_enable) { in intel_psr2_config_valid()
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| D | intel_audio.c | 123 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) in audio_config_dp_get_n_m() argument
129 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
233 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) in audio_config_hdmi_pixel_clock() argument
236 &crtc_state->base.adjusted_mode; in audio_config_hdmi_pixel_clock()
257 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, in audio_config_hdmi_get_n() argument
263 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
266 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
276 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
332 const struct intel_crtc_state *crtc_state, in g4x_audio_codec_enable() argument
373 const struct intel_crtc_state *crtc_state) in hsw_dp_audio_config_update() argument
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| D | intel_color.h | 13 int intel_color_check(struct intel_crtc_state *crtc_state);
14 void intel_color_commit(const struct intel_crtc_state *crtc_state);
15 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
16 void intel_color_get_config(struct intel_crtc_state *crtc_state);
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| D | intel_lspcon.c | 188 struct intel_crtc_state *crtc_state) in lspcon_ycbcr420_config() argument
192 &crtc_state->base.adjusted_mode; in lspcon_ycbcr420_config()
196 crtc_state->port_clock /= 2; in lspcon_ycbcr420_config()
197 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; in lspcon_ycbcr420_config()
198 crtc_state->lspcon_downsampling = true; in lspcon_ycbcr420_config()
432 const struct intel_crtc_state *crtc_state, in lspcon_write_infoframe() argument
460 const struct intel_crtc_state *crtc_state, in lspcon_read_infoframe() argument
469 const struct intel_crtc_state *crtc_state, in lspcon_set_infoframes() argument
478 &crtc_state->base.adjusted_mode; in lspcon_set_infoframes()
495 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { in lspcon_set_infoframes()
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| D | intel_dp_mst.c | 41 struct intel_crtc_state *crtc_state, in intel_dp_mst_compute_link_config() argument
45 struct drm_atomic_state *state = crtc_state->base.state; in intel_dp_mst_compute_link_config()
51 &crtc_state->base.adjusted_mode; in intel_dp_mst_compute_link_config()
57 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_compute_link_config()
58 crtc_state->port_clock = limits->max_clock; in intel_dp_mst_compute_link_config()
61 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
63 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, in intel_dp_mst_compute_link_config()
64 crtc_state->pipe_bpp); in intel_dp_mst_compute_link_config()
67 port, crtc_state->pbn); in intel_dp_mst_compute_link_config()
79 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
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| /Linux-v5.4/drivers/gpu/drm/gma500/ |
| D | gma_display.c | 499 kfree(gma_crtc->crtc_state); in gma_crtc_destroy()
529 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_save() local
534 if (!crtc_state) { in gma_crtc_save()
539 crtc_state->saveDSPCNTR = REG_READ(map->cntr); in gma_crtc_save()
540 crtc_state->savePIPECONF = REG_READ(map->conf); in gma_crtc_save()
541 crtc_state->savePIPESRC = REG_READ(map->src); in gma_crtc_save()
542 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
543 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
544 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
545 crtc_state->saveHTOTAL = REG_READ(map->htotal); in gma_crtc_save()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_crc.c | 141 struct dm_crtc_state *crtc_state; in amdgpu_dm_crtc_set_crc_source() local
179 crtc_state = to_dm_crtc_state(crtc->state); in amdgpu_dm_crtc_set_crc_source()
196 dm_is_crc_source_dprx(crtc_state->crc_src))) { in amdgpu_dm_crtc_set_crc_source()
226 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { in amdgpu_dm_crtc_set_crc_source()
235 enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); in amdgpu_dm_crtc_set_crc_source()
259 crtc_state->crc_src = source; in amdgpu_dm_crtc_set_crc_source()
262 crtc_state->crc_skip_count = 0; in amdgpu_dm_crtc_set_crc_source()
282 struct dm_crtc_state *crtc_state; in amdgpu_dm_crtc_handle_crc_irq() local
289 crtc_state = to_dm_crtc_state(crtc->state); in amdgpu_dm_crtc_handle_crc_irq()
290 stream_state = crtc_state->stream; in amdgpu_dm_crtc_handle_crc_irq()
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| /Linux-v5.4/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 78 struct drm_crtc_state *crtc_state; in drm_self_refresh_helper_entry_work() local
92 crtc_state = drm_atomic_get_crtc_state(state, crtc); in drm_self_refresh_helper_entry_work()
93 if (IS_ERR(crtc_state)) { in drm_self_refresh_helper_entry_work()
94 ret = PTR_ERR(crtc_state); in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
110 crtc_state->active = false; in drm_self_refresh_helper_entry_work()
111 crtc_state->self_refresh_active = true; in drm_self_refresh_helper_entry_work()
190 struct drm_crtc_state *crtc_state; in drm_self_refresh_helper_alter_state() local
194 for_each_old_crtc_in_state(state, crtc, crtc_state, i) { in drm_self_refresh_helper_alter_state()
195 if (crtc_state->self_refresh_active) { in drm_self_refresh_helper_alter_state()
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| D | drm_atomic_helper.c | 78 struct drm_crtc_state *crtc_state; in drm_atomic_helper_plane_changed() local
81 crtc_state = drm_atomic_get_new_crtc_state(state, in drm_atomic_helper_plane_changed()
84 if (WARN_ON(!crtc_state)) in drm_atomic_helper_plane_changed()
87 crtc_state->planes_changed = true; in drm_atomic_helper_plane_changed()
91 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); in drm_atomic_helper_plane_changed()
93 if (WARN_ON(!crtc_state)) in drm_atomic_helper_plane_changed()
96 crtc_state->planes_changed = true; in drm_atomic_helper_plane_changed()
169 struct drm_crtc_state *crtc_state; in handle_conflicting_encoders() local
199 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); in handle_conflicting_encoders()
205 if (!crtc_state->connector_mask) { in handle_conflicting_encoders()
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| D | drm_atomic.c | 294 struct drm_crtc_state *crtc_state; in drm_atomic_get_crtc_state() local
298 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); in drm_atomic_get_crtc_state()
299 if (crtc_state) in drm_atomic_get_crtc_state()
300 return crtc_state; in drm_atomic_get_crtc_state()
306 crtc_state = crtc->funcs->atomic_duplicate_state(crtc); in drm_atomic_get_crtc_state()
307 if (!crtc_state) in drm_atomic_get_crtc_state()
310 state->crtcs[index].state = crtc_state; in drm_atomic_get_crtc_state()
312 state->crtcs[index].new_state = crtc_state; in drm_atomic_get_crtc_state()
314 crtc_state->state = state; in drm_atomic_get_crtc_state()
317 crtc->base.id, crtc->name, crtc_state, state); in drm_atomic_get_crtc_state()
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| /Linux-v5.4/drivers/gpu/drm/tilcdc/ |
| D | tilcdc_plane.c | 26 struct drm_crtc_state *crtc_state; in tilcdc_plane_atomic_check() local
42 crtc_state = drm_atomic_get_existing_crtc_state(state->state, in tilcdc_plane_atomic_check()
45 if (WARN_ON(!crtc_state)) in tilcdc_plane_atomic_check()
48 if (crtc_state->mode.hdisplay != state->crtc_w || in tilcdc_plane_atomic_check()
49 crtc_state->mode.vdisplay != state->crtc_h) { in tilcdc_plane_atomic_check()
52 crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, in tilcdc_plane_atomic_check()
57 pitch = crtc_state->mode.hdisplay * in tilcdc_plane_atomic_check()
70 crtc_state->mode_changed = true; in tilcdc_plane_atomic_check()
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| /Linux-v5.4/drivers/gpu/drm/selftests/ |
| D | test-drm_plane_helper.c | 80 const struct drm_crtc_state crtc_state = { in igt_check_plane_state() local
103 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
114 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
127 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
133 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
145 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
150 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
160 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
164 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
175 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
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| /Linux-v5.4/drivers/gpu/drm/vkms/ |
| D | vkms_composer.c | 153 struct vkms_crtc_state *crtc_state = container_of(work, in vkms_composer_worker() local
156 struct drm_crtc *crtc = crtc_state->base.crtc; in vkms_composer_worker()
165 frame_start = crtc_state->frame_start; in vkms_composer_worker()
166 frame_end = crtc_state->frame_end; in vkms_composer_worker()
167 crc_pending = crtc_state->crc_pending; in vkms_composer_worker()
168 crtc_state->frame_start = 0; in vkms_composer_worker()
169 crtc_state->frame_end = 0; in vkms_composer_worker()
170 crtc_state->crc_pending = false; in vkms_composer_worker()
180 if (crtc_state->num_active_planes >= 1) in vkms_composer_worker()
181 primary_composer = crtc_state->active_planes[0]->composer; in vkms_composer_worker()
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | intel_pm.c | 493 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) in vlv_get_fifo_size() argument
495 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_get_fifo_size()
497 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
823 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, in intel_wm_plane_visible() argument
829 if (!crtc_state->base.active) in intel_wm_plane_visible()
1111 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, in g4x_compute_wm() argument
1118 &crtc_state->base.adjusted_mode; in g4x_compute_wm()
1125 if (!intel_wm_plane_visible(crtc_state, plane_state)) in g4x_compute_wm()
1175 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state, in g4x_raw_plane_wm_set() argument
1178 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); in g4x_raw_plane_wm_set()
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| /Linux-v5.4/include/drm/ |
| D | drm_atomic_helper.h | 44 const struct drm_crtc_state *crtc_state,
176 #define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \ argument
177 drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)
194 #define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \ argument
195 drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) \
197 __drm_atomic_get_current_plane_state((crtc_state)->state, \
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