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Searched refs:crtc_offsets (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Drv515.c48 static const u32 crtc_offsets[2] = variable
310 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; in rv515_mc_stop()
313 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
316 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
318 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
319 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
330 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
331 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
333 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
334 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
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Devergreen.c115 static const u32 crtc_offsets[6] = variable
1353 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1363 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1364 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1387 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
2679 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2683 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2686 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2688 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2689 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
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Drs600.c55 static const u32 crtc_offsets[2] = variable
63 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
73 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
74 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
97 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
Dsi.c146 static const u32 crtc_offsets[] = variable
5965 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
5967 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state()
6119 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, in si_irq_set()
6125 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in si_irq_set()
6157 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); in si_irq_ack()
6164 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in si_irq_ack()
6170 WREG32(VBLANK_STATUS + crtc_offsets[j], in si_irq_ack()
6173 WREG32(VLINE_STATUS + crtc_offsets[j], in si_irq_ack()
Dr600.c100 static const u32 crtc_offsets[2] = variable
1594 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1595 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1603 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c53 static const u32 crtc_offsets[] = variable
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
266 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
267 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
414 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
416 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
424 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
485 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_disable_dce()
488 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_disable_dce()
489 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
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Ddce_v11_0.c53 static const u32 crtc_offsets[] = variable
222 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v11_0_vblank_get_counter()
284 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
285 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
430 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
432 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
440 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
511 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_disable_dce()
514 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_disable_dce()
515 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce()
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Ddce_v8_0.c54 static const u32 crtc_offsets[6] = variable
152 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v8_0_vblank_get_counter()
211 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
212 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
348 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung()
349 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v8_0_is_display_hung()
357 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v8_0_is_display_hung()
425 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_disable_dce()
428 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_disable_dce()
429 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_disable_dce()
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Ddce_v6_0.c57 static const u32 crtc_offsets[6] = variable
156 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v6_0_vblank_get_counter()
217 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v6_0_crtc_get_scanoutpos()
218 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v6_0_crtc_get_scanoutpos()
382 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & in dce_v6_0_disable_dce()
385 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v6_0_disable_dce()
386 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v6_0_disable_dce()
388 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v6_0_disable_dce()
389 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v6_0_disable_dce()
2580 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
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Dgmc_v6_0.c65 static const u32 crtc_offsets[6] = variable