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Searched refs:cpg (Results 1 – 25 of 99) sorted by relevance

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/Linux-v5.4/drivers/clk/renesas/
DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
16 obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
17 obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
[all …]
Dclk-sh73a0.c75 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, in sh73a0_cpg_register_clock() argument
86 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; in sh73a0_cpg_register_clock()
91 void __iomem *enable_reg = cpg->reg; in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
120 void __iomem *dsi_reg = cpg->reg + in sh73a0_cpg_register_clock()
157 cpg->reg + reg, shift, width, 0, in sh73a0_cpg_register_clock()
158 table, &cpg->lock); in sh73a0_cpg_register_clock()
164 struct sh73a0_cpg *cpg; in sh73a0_cpg_clocks_init() local
175 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in sh73a0_cpg_clocks_init()
177 if (cpg == NULL || clks == NULL) { in sh73a0_cpg_clocks_init()
[all …]
Dclk-r8a73a4.c61 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
72 u32 ckscr = readl(cpg->reg + CPG_CKSCR); in r8a73a4_cpg_register_clock()
96 u32 value = readl(cpg->reg + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
103 u32 value = readl(cpg->reg + CPG_PLL1CR); in r8a73a4_cpg_register_clock()
126 value = readl(cpg->reg + cr); in r8a73a4_cpg_register_clock()
162 mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); in r8a73a4_cpg_register_clock()
184 cpg->reg + reg, shift, 4, 0, in r8a73a4_cpg_register_clock()
185 table, &cpg->lock); in r8a73a4_cpg_register_clock()
191 struct r8a73a4_cpg *cpg; in r8a73a4_cpg_clocks_init() local
202 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a73a4_cpg_clocks_init()
[all …]
Dclk-r8a7740.c63 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, in r8a7740_cpg_register_clock() argument
99 u32 value = readl(cpg->reg + CPG_FRQCRC); in r8a7740_cpg_register_clock()
103 u32 value = readl(cpg->reg + CPG_FRQCRA); in r8a7740_cpg_register_clock()
108 u32 value = readl(cpg->reg + CPG_PLLC2CR); in r8a7740_cpg_register_clock()
112 u32 value = readl(cpg->reg + CPG_USBCKCR); in r8a7740_cpg_register_clock()
140 cpg->reg + reg, shift, 4, 0, in r8a7740_cpg_register_clock()
141 table, &cpg->lock); in r8a7740_cpg_register_clock()
147 struct r8a7740_cpg *cpg; in r8a7740_cpg_clocks_init() local
161 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in r8a7740_cpg_clocks_init()
163 if (cpg == NULL || clks == NULL) { in r8a7740_cpg_clocks_init()
[all …]
Dclk-rcar-gen2.c136 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) in cpg_z_clk_register() argument
153 zclk->reg = cpg->reg + CPG_FRQCRC; in cpg_z_clk_register()
154 zclk->kick_reg = cpg->reg + CPG_FRQCRB; in cpg_z_clk_register()
164 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg, in cpg_rcan_clk_register() argument
185 gate->reg = cpg->reg + CPG_RCANCKCR; in cpg_rcan_clk_register()
188 gate->lock = &cpg->lock; in cpg_rcan_clk_register()
208 static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg) in cpg_adsp_clk_register() argument
219 div->reg = cpg->reg + CPG_ADSPCKCR; in cpg_adsp_clk_register()
222 div->lock = &cpg->lock; in cpg_adsp_clk_register()
230 gate->reg = cpg->reg + CPG_ADSPCKCR; in cpg_adsp_clk_register()
[all …]
Dclk-rz.c52 rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name) in rz_cpg_register_clock() argument
68 if (!cpg->reg) in rz_cpg_register_clock()
76 val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; in rz_cpg_register_clock()
78 val = readl(cpg->reg + CPG_FRQCR2) & 3; in rz_cpg_register_clock()
88 struct rz_cpg *cpg; in rz_cpg_clocks_init() local
97 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); in rz_cpg_clocks_init()
99 BUG_ON(!cpg || !clks); in rz_cpg_clocks_init()
101 cpg->data.clks = clks; in rz_cpg_clocks_init()
102 cpg->data.clk_num = num_clks; in rz_cpg_clocks_init()
104 cpg->reg = of_iomap(np, 0); in rz_cpg_clocks_init()
[all …]
/Linux-v5.4/arch/arm64/boot/dts/renesas/
Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
146 clocks = <&cpg CPG_MOD 402>;
148 resets = <&cpg 402>;
162 clocks = <&cpg CPG_MOD 912>;
164 resets = <&cpg 912>;
177 clocks = <&cpg CPG_MOD 911>;
179 resets = <&cpg 911>;
192 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 402>;
82 resets = <&cpg 402>;
96 clocks = <&cpg CPG_MOD 912>;
98 resets = <&cpg 912>;
111 clocks = <&cpg CPG_MOD 911>;
113 resets = <&cpg 911>;
126 clocks = <&cpg CPG_MOD 910>;
128 resets = <&cpg 910>;
141 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
92 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
103 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
159 clocks = <&cpg CPG_MOD 402>;
161 resets = <&cpg 402>;
175 clocks = <&cpg CPG_MOD 912>;
177 resets = <&cpg 912>;
190 clocks = <&cpg CPG_MOD 911>;
192 resets = <&cpg 911>;
205 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a774a1.dtsi10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
139 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
152 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
167 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
179 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
191 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
203 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
283 clocks = <&cpg CPG_MOD 402>;
285 resets = <&cpg 402>;
299 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a7795.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
159 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
172 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
185 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
198 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
213 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
225 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
237 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
249 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
337 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr8a77980.dtsi9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
141 clocks = <&cpg CPG_MOD 402>;
143 resets = <&cpg 402>;
157 clocks = <&cpg CPG_MOD 912>;
159 resets = <&cpg 912>;
172 clocks = <&cpg CPG_MOD 911>;
[all …]
Dr8a7796.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
164 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
177 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
192 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
204 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
216 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
228 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
308 clocks = <&cpg CPG_MOD 402>;
310 resets = <&cpg 402>;
324 clocks = <&cpg CPG_MOD 912>;
[all …]
Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
116 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
127 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
191 clocks = <&cpg CPG_MOD 402>;
193 resets = <&cpg 402>;
207 clocks = <&cpg CPG_MOD 912>;
209 resets = <&cpg 912>;
222 clocks = <&cpg CPG_MOD 911>;
224 resets = <&cpg 911>;
237 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a77970.dtsi9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
42 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
52 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
111 clocks = <&cpg CPG_MOD 402>;
113 resets = <&cpg 402>;
127 clocks = <&cpg CPG_MOD 912>;
129 resets = <&cpg 912>;
142 clocks = <&cpg CPG_MOD 911>;
144 resets = <&cpg 911>;
157 clocks = <&cpg CPG_MOD 910>;
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
93 clocks = <&cpg CPG_MOD 402>;
95 resets = <&cpg 402>;
109 clocks = <&cpg CPG_MOD 912>;
111 resets = <&cpg 912>;
124 clocks = <&cpg CPG_MOD 911>;
126 resets = <&cpg 911>;
139 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
138 clocks = <&cpg CPG_MOD 912>;
140 resets = <&cpg 912>;
153 clocks = <&cpg CPG_MOD 911>;
155 resets = <&cpg 911>;
168 clocks = <&cpg CPG_MOD 910>;
170 resets = <&cpg 910>;
183 clocks = <&cpg CPG_MOD 909>;
[all …]
Dr8a7743.dtsi10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
142 clocks = <&cpg CPG_MOD 402>;
144 resets = <&cpg 402>;
158 clocks = <&cpg CPG_MOD 912>;
160 resets = <&cpg 912>;
173 clocks = <&cpg CPG_MOD 911>;
175 resets = <&cpg 911>;
188 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
130 clocks = <&cpg CPG_MOD 402>;
132 resets = <&cpg 402>;
146 clocks = <&cpg CPG_MOD 912>;
148 resets = <&cpg 912>;
161 clocks = <&cpg CPG_MOD 911>;
163 resets = <&cpg 911>;
176 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
113 clocks = <&cpg CPG_MOD 402>;
115 resets = <&cpg 402>;
129 clocks = <&cpg CPG_MOD 912>;
131 resets = <&cpg 912>;
144 clocks = <&cpg CPG_MOD 911>;
146 resets = <&cpg 911>;
159 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7744.dtsi10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
59 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
142 clocks = <&cpg CPG_MOD 402>;
144 resets = <&cpg 402>;
158 clocks = <&cpg CPG_MOD 912>;
160 resets = <&cpg 912>;
173 clocks = <&cpg CPG_MOD 911>;
175 resets = <&cpg 911>;
188 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
163 clocks = <&cpg CPG_MOD 402>;
165 resets = <&cpg 402>;
179 clocks = <&cpg CPG_MOD 912>;
181 resets = <&cpg 912>;
194 clocks = <&cpg CPG_MOD 911>;
196 resets = <&cpg 911>;
209 clocks = <&cpg CPG_MOD 910>;
[all …]
Dr8a7790.dtsi10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
121 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
142 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
163 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
174 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
185 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
196 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
270 clocks = <&cpg CPG_MOD 402>;
[all …]
Dr7s9210.dtsi10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
82 clocks = <&cpg CPG_MOD 47>;
84 power-domains = <&cpg>;
99 clocks = <&cpg CPG_MOD 46>;
101 power-domains = <&cpg>;
116 clocks = <&cpg CPG_MOD 45>;
118 power-domains = <&cpg>;
133 clocks = <&cpg CPG_MOD 44>;
135 power-domains = <&cpg>;
150 clocks = <&cpg CPG_MOD 43>;
[all …]

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