Searched refs:cp_int_cntl (Results 1 – 8 of 8) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 3239 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local
3243 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3244 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3245 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3248 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3249 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3250 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3261 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local
3265 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3266 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_compute_eop_interrupt_state()
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| D | gfx_v7_0.c | 4705 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
4709 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4710 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4711 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4714 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4715 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4716 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4779 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
4783 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4784 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state()
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| D | gfx_v10_0.c | 4818 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
4839 cp_int_cntl = RREG32(cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
4840 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
4842 WREG32(cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
4845 cp_int_cntl = RREG32(cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
4846 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
4848 WREG32(cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
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| /Linux-v5.4/drivers/gpu/drm/radeon/ |
| D | evergreen.c | 217 int ring, u32 cp_int_cntl);
4494 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4525 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4538 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4539 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4562 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4566 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
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| D | ni.c | 1393 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1396 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
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| D | r600.c | 3766 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3824 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3825 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3876 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
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| D | si.c | 6053 u32 cp_int_cntl; in si_irq_set() local
6071 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6083 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6103 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
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| D | cik.c | 7032 u32 cp_int_cntl; in cik_irq_set() local
7052 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7054 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7078 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7232 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
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