Home
last modified time | relevance | path

Searched refs:cp_hqd_pq_control (Results 1 – 15 of 15) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdkfd/
Dkfd_mqd_manager_cik.c193 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
197 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
205 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
215 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
319 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
328 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
Dkfd_mqd_manager_v10.c182 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
183 m->cp_hqd_pq_control |= in update_mqd()
185 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
223 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
305 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
Dkfd_mqd_manager_v9.c201 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
202 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
203 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
242 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
323 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
Dkfd_mqd_manager_vi.c177 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | in __update_mqd()
180 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
181 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in __update_mqd()
224 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in __update_mqd()
308 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
/Linux-v5.4/drivers/gpu/drm/amd/include/
Dcik_structs.h96 uint32_t cp_hqd_pq_control; member
Dvi_structs.h305 uint32_t cp_hqd_pq_control; member
Dv9_structs.h305 uint32_t cp_hqd_pq_control; member
Dv10_structs.h822 uint32_t cp_hqd_pq_control; member
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2854 u32 cp_hqd_pq_control; member
2967 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2968 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2972 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2974 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2977 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2980 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2984 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
Damdgpu_amdkfd_gfx_v9.c320 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_hqd_load()
Damdgpu_amdkfd_gfx_v10.c419 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
Dgfx_v10_0.c3298 mqd->cp_hqd_pq_control = tmp; in gfx_v10_0_compute_mqd_init()
3409 mqd->cp_hqd_pq_control); in gfx_v10_0_kiq_init_register()
Dgfx_v9_0.c3502 mqd->cp_hqd_pq_control = tmp; in gfx_v9_0_mqd_init()
3612 mqd->cp_hqd_pq_control); in gfx_v9_0_kiq_init_register()
Dgfx_v8_0.c4521 mqd->cp_hqd_pq_control = tmp; in gfx_v8_0_mqd_init()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dcik.c4465 u32 cp_hqd_pq_control; member
4672 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4673 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4676 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4678 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4681 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; in cik_cp_compute_resume()
4683 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4685 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4687 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()